Added english description for lhzu instruction

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 500489b75b30014d57398a3da9e1da65d348f46d..0e2b6536ad9ed8b2af16c4226da9aca1eaa34695 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -152,6 +152,10 @@ Pseudo-code:
     RT <- ([0] * (XLEN-16)) || MEM(EA, 2)
     RA <- EA
 
+Description:Let the effective address (EA) be the sum
+(RA|0)+ (RB). The halfword in storage addressed by
+EA is loaded into RT 48:63. RT 0:47 are set to 0.
+
 Special Registers Altered:
 
     None