Don't use VHDL 2008 condition operator in multiply

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/multiply.vhdl b/multiply.vhdl
index 9aa43169d9902d30e45a51d4a716ba97ea904c5a..3e76b4360408554421feecdf838b4861369e3e79 100644 (file)
--- a/multiply.vhdl
+++ b/multiply.vhdl
@@ -85,7 +85,7 @@ begin
                m_out.write_reg_data <= d2;
                m_out.write_reg_nr <= v.multiply_pipeline(PIPELINE_DEPTH-1).write_reg;
 
-               if v.multiply_pipeline(PIPELINE_DEPTH-1).valid then
+               if v.multiply_pipeline(PIPELINE_DEPTH-1).valid = '1' then
                        m_out.valid <= '1';
                        m_out.write_reg_enable <= '1';