PN is expected, and vice versa, so the issue at this point is
"predicate-like" vs. "not predicate-like". */
return N_("expected an SVE predicate register at operand %d");
+ if (mask == reg_type_masks[REG_TYPE_PN])
+ return N_("expected an SVE predicate-as-counter register at operand %d");
if (mask == reg_type_masks[REG_TYPE_VZ])
return N_("expected a vector register at operand %d");
if (mask == reg_type_masks[REG_TYPE_ZP])
if (!(flags & PTR_FULL_REG) && skip_past_char (&str, '['))
{
/* Reject Sn[index] syntax. */
- if (!is_typed_vecreg)
+ if (reg->type != REG_TYPE_PN && !is_typed_vecreg)
{
first_error (_("this type of register can't be indexed"));
return NULL;
&& e1.index == e2.index);
}
+/* Return the register number mask for registers of type REG_TYPE. */
+
+static inline int
+reg_type_mask (aarch64_reg_type reg_type)
+{
+ return reg_type == REG_TYPE_P ? 15 : 31;
+}
+
/* This function parses a list of vector registers of type TYPE.
On success, it returns the parsed register list information in the
following encoded format:
char *str = *ccp;
int nb_regs;
struct vector_type_el typeinfo, typeinfo_first;
- int val, val_range;
+ int val, val_range, mask;
int in_range;
int ret_val;
bool error = false;
val = -1;
val_range = -1;
in_range = 0;
+ mask = reg_type_mask (type);
do
{
if (in_range)
(_("invalid range in vector register list"));
error = true;
}
- val_range = (val_range + 1) & 0x1f;
+ val_range = (val_range + 1) & mask;
}
else
{
nb_regs++;
if (val_range == val)
break;
- val_range = (val_range + 1) & 0x1f;
+ val_range = (val_range + 1) & mask;
}
in_range = 0;
ptr_flags |= PTR_GOOD_MATCH;
/* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
of SIZE tokens in which index I gives the token for field value I,
- or is null if field value I is invalid. REG_TYPE says which register
- names should be treated as registers rather than as symbolic immediates.
+ or is null if field value I is invalid. If the symbolic operand
+ can also be given as a 0-based integer, REG_TYPE says which register
+ names should be treated as registers rather than as symbolic immediates
+ while parsing that integer. REG_TYPE is REG_TYPE_MAX otherwise.
Return true on success, moving *STR past the operand and storing the
field value in *VAL. */
return true;
}
+ if (reg_type == REG_TYPE_MAX)
+ return false;
+
if (!parse_immediate_expression (&p, &exp, reg_type))
return false;
goto failure; \
} while (0)
+#define po_strict_enum_or_fail(array) do { \
+ if (!parse_enum_string (&str, &val, array, \
+ ARRAY_SIZE (array), REG_TYPE_MAX)) \
+ goto failure; \
+ } while (0)
+
#define po_misc_or_fail(expr) do { \
if (!expr) \
goto failure; \
return reloc_ldst_lo12[inst.reloc.type - BFD_RELOC_AARCH64_LDST_LO12][logsz];
}
-/* Check whether a register list REGINFO is valid. The registers must be
- numbered in increasing order (modulo 32). They must also have a
- consistent stride.
+/* Check whether a register list REGINFO is valid. The registers have type
+ REG_TYPE and must be numbered in increasing order (modulo the register
+ bank size). They must have a consistent stride.
Return true if the list is valid, describing it in LIST if so. */
static bool
-reg_list_valid_p (uint32_t reginfo, struct aarch64_reglist *list)
+reg_list_valid_p (uint32_t reginfo, struct aarch64_reglist *list,
+ aarch64_reg_type reg_type)
{
- uint32_t i, nb_regs, prev_regno, incr;
+ uint32_t i, nb_regs, prev_regno, incr, mask;
+ mask = reg_type_mask (reg_type);
nb_regs = 1 + (reginfo & 0x3);
reginfo >>= 2;
uint32_t curr_regno, curr_incr;
reginfo >>= 5;
curr_regno = reginfo & 0x1f;
- curr_incr = (curr_regno - prev_regno) & 0x1f;
+ curr_incr = (curr_regno - prev_regno) & mask;
if (curr_incr == 0)
return false;
else if (i == 1)
case AARCH64_OPND_SVE_PNg4_10:
case AARCH64_OPND_SVE_PNn:
case AARCH64_OPND_SVE_PNt:
+ case AARCH64_OPND_SME_PNd3:
case AARCH64_OPND_SME_PNg3:
+ case AARCH64_OPND_SME_PNn:
reg_type = REG_TYPE_PN;
goto vector_reg;
case AARCH64_OPND_SVE_ZtxN:
case AARCH64_OPND_SME_Zdnx2:
case AARCH64_OPND_SME_Zdnx4:
+ case AARCH64_OPND_SME_Zmx2:
+ case AARCH64_OPND_SME_Zmx4:
case AARCH64_OPND_SME_Znx2:
case AARCH64_OPND_SME_Znx4:
case AARCH64_OPND_SME_Ztx2_STRIDED:
reg_type = REG_TYPE_Z;
goto vector_reg_list;
+ case AARCH64_OPND_SME_Pdx2:
+ case AARCH64_OPND_SME_PdxN:
+ reg_type = REG_TYPE_P;
+ goto vector_reg_list;
+
case AARCH64_OPND_LVn:
case AARCH64_OPND_LVt:
case AARCH64_OPND_LVt_AL:
if (val == PARSE_FAIL)
goto failure;
- if (! reg_list_valid_p (val, &info->reglist))
+ if (! reg_list_valid_p (val, &info->reglist, reg_type))
{
set_fatal_syntax_error (_("invalid register list"));
goto failure;
goto failure;
if (!(vectype.defined & NTA_HASTYPE))
{
- if (reg_type == REG_TYPE_Z)
+ if (reg_type == REG_TYPE_Z || reg_type == REG_TYPE_P)
set_fatal_syntax_error (_("missing type suffix"));
goto failure;
}
goto failure;
break;
+ case AARCH64_OPND_SME_PNn3_INDEX1:
+ case AARCH64_OPND_SME_PNn3_INDEX2:
+ reg = aarch64_reg_parse (&str, REG_TYPE_PN, &vectype);
+ if (!reg)
+ goto failure;
+ if (!(vectype.defined & NTA_HASINDEX))
+ {
+ set_syntax_error (_("missing register index"));
+ goto failure;
+ }
+ info->reglane.regno = reg->number;
+ info->reglane.index = vectype.index;
+ if (vectype.type == NT_invtype)
+ info->qualifier = AARCH64_OPND_QLF_NIL;
+ else
+ info->qualifier = vectype_to_qualifier (&vectype);
+ break;
+
case AARCH64_OPND_BTI_TARGET:
val = parse_bti_operand (&str, &(info->hint_option));
if (val == PARSE_FAIL)
info->qualifier = qualifier;
break;
+ case AARCH64_OPND_SME_VLxN_10:
+ case AARCH64_OPND_SME_VLxN_13:
+ po_strict_enum_or_fail (aarch64_sme_vlxn_array);
+ info->imm.value = val;
+ break;
+
case AARCH64_OPND_MOPS_ADDR_Rd:
case AARCH64_OPND_MOPS_ADDR_Rs:
po_char_or_fail ('[');
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: usubwt z0\.s, z0\.s, z0\.h
[^ :]+:[0-9]+: Info: usubwt z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilege p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilege p16\.b,x0,x0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,x32,x0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,x0,x32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0/m,x0,x0'
[^ :]+:[0-9]+: Info: whilege p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilege p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilege p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilege p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilege p16\.b,w0,w0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,w32,w0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,w0,w32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0/m,w0,w0'
[^ :]+:[0-9]+: Info: whilege p0\.d, w0, w0
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,w31,w0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,w0,w31'
-[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilegt p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilegt p16\.b,x0,x0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,x32,x0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,x0,x32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0/m,x0,x0'
[^ :]+:[0-9]+: Info: whilegt p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilegt p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilegt p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilegt p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilegt p16\.b,w0,w0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,w32,w0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,w0,w32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0/m,w0,w0'
[^ :]+:[0-9]+: Info: whilegt p0\.d, w0, w0
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,w31,w0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,w0,w31'
-[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehi p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilehi p16\.b,x0,x0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,x32,x0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,x0,x32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0/m,x0,x0'
[^ :]+:[0-9]+: Info: whilehi p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilehi p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilehi p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehi p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilehi p16\.b,w0,w0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,w32,w0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,w0,w32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0/m,w0,w0'
[^ :]+:[0-9]+: Info: whilehi p0\.d, w0, w0
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,w31,w0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,w0,w31'
-[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehs p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilehs p16\.b,x0,x0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehs p0\.b,x32,x0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,x0,x32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0/m,x0,x0'
[^ :]+:[0-9]+: Info: whilehs p0\.h, x0, x0
[^ :]+:[0-9]+: Info: whilehs p0\.s, x0, x0
[^ :]+:[0-9]+: Info: whilehs p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehs p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilehs p16\.b,w0,w0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehs p0\.b,w32,w0'
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,w0,w32'
[^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0/m,w0,w0'
f8: 25277c61 psel p1, p15, p3.b\[w15, 0\]
fc: 252778a2 psel p2, p14, p5.b\[w15, 0\]
100: 25244200 \.inst 0x25244200 ; undefined
- 104: 25244010 \.inst 0x25244010 ; undefined
- 108: 25244210 \.inst 0x25244210 ; undefined
+ 104: 25244010 whilege pn8.b, x0, x4, vlx2
+ 108: 25244210 whilege pn8.b, x16, x4, vlx2
--- /dev/null
+#as: -march=armv8-a
+#source: sme2-6-invalid.s
+#error_output: sme2-6-invalid.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `cntp 0,pn0\.b,vlx2'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 2 -- `cntp x0,0,vlx2'
+[^ :]+:[0-9]+: Error: operand 3 must be VLx2 or VLx4 -- `cntp x0,pn0\.b,0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `cntp xsp,pn0\.b,vlx2'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `cntp sp,pn0\.b,vlx2'
+[^ :]+:[0-9]+: Error: operand mismatch -- `cntp w0,pn0\.b,vlx2'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: cntp x0, pn0\.b, vlx2
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: cntp x0, pn0\.h, vlx2
+[^ :]+:[0-9]+: Info: cntp x0, pn0\.s, vlx2
+[^ :]+:[0-9]+: Info: cntp x0, pn0\.d, vlx2
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 3 -- `cntp x0,p0\.b,vlx2'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 2 -- `cntp x0,pn16\.b,vlx2'
+[^ :]+:[0-9]+: Error: operand 3 must be VLx2 or VLx4 -- `cntp x0,pn0\.b,#0'
+[^ :]+:[0-9]+: Error: operand 3 must be VLx2 or VLx4 -- `cntp x0,pn0\.b,vl'
+[^ :]+:[0-9]+: Error: operand 3 must be VLx2 or VLx4 -- `cntp x0,pn0\.b,vlx3'
+[^ :]+:[0-9]+: Error: operand mismatch -- `cntp x0,pn0,vlx2'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: cntp x0, pn0\.b, vlx2
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: cntp x0, pn0\.h, vlx2
+[^ :]+:[0-9]+: Info: cntp x0, pn0\.s, vlx2
+[^ :]+:[0-9]+: Info: cntp x0, pn0\.d, vlx2
+[^ :]+:[0-9]+: Error: operand mismatch -- `cntp x0,pn0\.q,vlx2'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: cntp x0, pn0\.b, vlx2
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: cntp x0, pn0\.h, vlx2
+[^ :]+:[0-9]+: Info: cntp x0, pn0\.s, vlx2
+[^ :]+:[0-9]+: Info: cntp x0, pn0\.d, vlx2
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `pext 0,pn8\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE predicate-as-counter register at operand 2 -- `pext p0\.b,0'
+[^ :]+:[0-9]+: Error: expected a predicate-as-mask rather than predicate-as-counter register at operand 1 -- `pext pn8\.b,pn0\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `pext z0\.b,pn8\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE predicate-as-counter register at operand 2 -- `pext p8\.b,z8\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE predicate-as-counter register at operand 2 -- `pext p8\.b,x8'
+[^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `pext p8\.b,p8\[0\]'
+[^ :]+:[0-9]+: Error: missing register index at operand 2 -- `pext p8\.b,pn8'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 2 -- `pext p8\.b,pn8\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 2 -- `pext p8\.b,pn8\[4\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 2 -- `pext p8\.b,pn8\[1<<32\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `pext p8\.b,pn8\.b\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: pext p8\.b, pn8\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: pext p8\.h, pn8\[0\]
+[^ :]+:[0-9]+: Info: pext p8\.s, pn8\[0\]
+[^ :]+:[0-9]+: Info: pext p8\.d, pn8\[0\]
+[^ :]+:[0-9]+: Error: operand mismatch -- `pext p8\.q,pn8\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: pext p8\.b, pn8\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: pext p8\.h, pn8\[0\]
+[^ :]+:[0-9]+: Info: pext p8\.s, pn8\[0\]
+[^ :]+:[0-9]+: Info: pext p8\.d, pn8\[0\]
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `pext {p0\.b-p2\.b},pn8\[0\]'
+[^ :]+:[0-9]+: Error: missing type suffix at operand 1 -- `pext {p0-p1},pn8\[0\]'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `pext {p0\.b-p1\.b},pn7\[0\]'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `pext {p0\.b-p1\.b},pn0\[0\]'
+[^ :]+:[0-9]+: Error: missing register index at operand 2 -- `pext {p0\.b-p1\.b},pn8'
+[^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `pext {p0\.b-p1\.b},p0\[0\]'
+[^ :]+:[0-9]+: Error: operand mismatch -- `pext {p0\.b-p1\.b},pn8\.b\[0\]'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: pext {p0\.b-p1\.b}, pn8\[0\]
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: pext {p0\.h-p1\.h}, pn8\[0\]
+[^ :]+:[0-9]+: Info: pext {p0\.s-p1\.s}, pn8\[0\]
+[^ :]+:[0-9]+: Info: pext {p0\.d-p1\.d}, pn8\[0\]
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 2 -- `pext {p0\.b-p1\.b},pn8\[-1\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 2 -- `pext {p0\.b-p1\.b},pn8\[2\]'
+[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 2 -- `pext {p0\.b-p1\.b},pn8\[1<<32\]'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `ptrue 0'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn0\.b'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn7\.b'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn0\.h'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn7\.h'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn0\.s'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn7\.s'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn0\.d'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn7\.d'
+[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `ptrue pn8\.b,all'
+[^ :]+:[0-9]+: Error: operand mismatch -- `ptrue pn8\.q'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: ptrue pn8\.b
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: ptrue pn8\.h
+[^ :]+:[0-9]+: Info: ptrue pn8\.s
+[^ :]+:[0-9]+: Info: ptrue pn8\.d
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `sel 0,pn8,{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: expected an SVE predicate-as-counter register at operand 2 -- `sel {z0\.b-z1\.b},0,{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: expected '{' at operand 3 -- `sel {z0\.b-z1\.b},pn8,0,{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: expected '{' at operand 4 -- `sel {z0\.b-z1\.b},pn8,{z0\.b-z1\.b},0'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `sel {z1\.b-z2\.b},pn8,{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `sel {z0\.b-z1\.b},p8,{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `sel {z0\.b-z1\.b},pn7,{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sel {z0\.b-z1\.b},pn8/z,{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: sel {z0\.b-z1\.b}, pn8, {z0\.b-z1\.b}, {z0\.b-z1\.b}
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: sel {z0\.h-z1\.h}, pn8, {z0\.h-z1\.h}, {z0\.h-z1\.h}
+[^ :]+:[0-9]+: Info: sel {z0\.s-z1\.s}, pn8, {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Info: sel {z0\.d-z1\.d}, pn8, {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^ :]+:[0-9]+: Error: operand mismatch -- `sel {z0\.b-z1\.b},pn8/m,{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: sel {z0\.b-z1\.b}, pn8, {z0\.b-z1\.b}, {z0\.b-z1\.b}
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: sel {z0\.h-z1\.h}, pn8, {z0\.h-z1\.h}, {z0\.h-z1\.h}
+[^ :]+:[0-9]+: Info: sel {z0\.s-z1\.s}, pn8, {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Info: sel {z0\.d-z1\.d}, pn8, {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `sel {z0\.b-z1\.b},pn0,{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sel {z0\.b-z1\.b},pn8,{z11\.b-z12\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 4 -- `sel {z0\.b-z1\.b},pn8,{z0\.b-z1\.b},{z17\.b-z18\.b}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `sel {z1\.b-z4\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `sel {z10\.b-z13\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `sel {z15\.b-z18\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sel {z0\.b-z3\.b},pn8,{z1\.b-z4\.b},{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sel {z0\.b-z3\.b},pn8,{z22\.b-z25\.b},{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sel {z0\.b-z3\.b},pn8,{z27\.b-z30\.b},{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 4 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z5\.b-z8\.b}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 4 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z14\.b-z17\.b}'
+[^ :]+:[0-9]+: Error: start register out of range at operand 4 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z19\.b-z22\.b}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `sel {z0\.b-z1\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z1\.b},{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 4 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `sel {z0\.b-z2\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z2\.b},{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 4 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z0\.b-z2\.b}'
+[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `sel {z0\.b-z2\.b},pn8,{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `sel {z0\.b-z1\.b},pn8,{z0\.b-z2\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 4 -- `sel {z0\.b-z1\.b},pn8,{z0\.b-z1\.b},{z0\.b-z2\.b}'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sel {z0\.q-z1\.q},pn8,{z0\.q-z1\.q},{z0\.q-z1\.q}'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: sel {z0\.b-z1\.b}, pn8, {z0\.b-z1\.b}, {z0\.b-z1\.b}
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: sel {z0\.h-z1\.h}, pn8, {z0\.h-z1\.h}, {z0\.h-z1\.h}
+[^ :]+:[0-9]+: Info: sel {z0\.s-z1\.s}, pn8, {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^ :]+:[0-9]+: Info: sel {z0\.d-z1\.d}, pn8, {z0\.d-z1\.d}, {z0\.d-z1\.d}
--- /dev/null
+ cntp 0, pn0.b, vlx2
+ cntp x0, 0, vlx2
+ cntp x0, pn0.b, 0
+
+ cntp xsp, pn0.b, vlx2
+ cntp sp, pn0.b, vlx2
+ cntp w0, pn0.b, vlx2
+ cntp x0, p0.b, vlx2
+ cntp x0, pn16.b, vlx2
+ cntp x0, pn0.b, #0
+ cntp x0, pn0.b, vl
+ cntp x0, pn0.b, vlx3
+
+ cntp x0, pn0, vlx2
+ cntp x0, pn0.q, vlx2
+
+ pext 0, pn8[0]
+ pext p0.b, 0
+
+ pext pn8.b, pn0[0]
+ pext z0.b, pn8[0]
+ pext p8.b, z8[0]
+ pext p8.b, x8
+ pext p8.b, p8[0]
+ pext p8.b, pn8
+ pext p8.b, pn8[-1]
+ pext p8.b, pn8[4]
+ pext p8.b, pn8[1 << 32]
+ pext p8.b, pn8.b[0]
+ pext p8.q, pn8[0]
+
+ pext { p0.b - p2.b }, pn8[0]
+ pext { p0 - p1 }, pn8[0]
+ pext { p0.b - p1.b }, pn7[0]
+ pext { p0.b - p1.b }, pn0[0]
+ pext { p0.b - p1.b }, pn8
+ pext { p0.b - p1.b }, p0[0]
+ pext { p0.b - p1.b }, pn8.b[0]
+ pext { p0.b - p1.b }, pn8[-1]
+ pext { p0.b - p1.b }, pn8[2]
+ pext { p0.b - p1.b }, pn8[1 << 32]
+
+ ptrue 0
+
+ ptrue pn0.b
+ ptrue pn7.b
+ ptrue pn0.h
+ ptrue pn7.h
+ ptrue pn0.s
+ ptrue pn7.s
+ ptrue pn0.d
+ ptrue pn7.d
+ ptrue pn8.b, all
+ ptrue pn8.q
+
+ sel 0, pn8, { z0.b - z1.b }, { z0.b - z1.b }
+ sel { z0.b - z1.b }, 0, { z0.b - z1.b }, { z0.b - z1.b }
+ sel { z0.b - z1.b }, pn8, 0, { z0.b - z1.b }
+ sel { z0.b - z1.b }, pn8, { z0.b - z1.b }, 0
+
+ sel { z1.b - z2.b }, pn8, { z0.b - z1.b }, { z0.b - z1.b }
+ sel { z0.b - z1.b }, p8, { z0.b - z1.b }, { z0.b - z1.b }
+ sel { z0.b - z1.b }, pn7, { z0.b - z1.b }, { z0.b - z1.b }
+ sel { z0.b - z1.b }, pn8/z, { z0.b - z1.b }, { z0.b - z1.b }
+ sel { z0.b - z1.b }, pn8/m, { z0.b - z1.b }, { z0.b - z1.b }
+ sel { z0.b - z1.b }, pn0, { z0.b - z1.b }, { z0.b - z1.b }
+ sel { z0.b - z1.b }, pn8, { z11.b - z12.b }, { z0.b - z1.b }
+ sel { z0.b - z1.b }, pn8, { z0.b - z1.b }, { z17.b - z18.b }
+
+ sel { z1.b - z4.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }
+ sel { z10.b - z13.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }
+ sel { z15.b - z18.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }
+ sel { z0.b - z3.b }, pn8, { z1.b - z4.b }, { z0.b - z3.b }
+ sel { z0.b - z3.b }, pn8, { z22.b - z25.b }, { z0.b - z3.b }
+ sel { z0.b - z3.b }, pn8, { z27.b - z30.b }, { z0.b - z3.b }
+ sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z5.b - z8.b }
+ sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z14.b - z17.b }
+ sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z19.b - z22.b }
+
+ sel { z0.b - z1.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }
+ sel { z0.b - z3.b }, pn8, { z0.b - z1.b }, { z0.b - z3.b }
+ sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z0.b - z1.b }
+
+ sel { z0.b - z2.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }
+ sel { z0.b - z3.b }, pn8, { z0.b - z2.b }, { z0.b - z3.b }
+ sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z0.b - z2.b }
+
+ sel { z0.b - z2.b }, pn8, { z0.b - z1.b }, { z0.b - z1.b }
+ sel { z0.b - z1.b }, pn8, { z0.b - z2.b }, { z0.b - z1.b }
+ sel { z0.b - z1.b }, pn8, { z0.b - z1.b }, { z0.b - z2.b }
+
+ sel { z0.q - z1.q }, pn8, { z0.q - z1.q }, { z0.q - z1.q }
--- /dev/null
+#as: -march=armv8-a+sme
+#source: sme2-6.s
+#error_output: sme2-6-noarch.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.b,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp X0,PN0\.B,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x30,pn0\.b,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp xzr,pn0\.b,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn15\.b,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.b,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp X11,PN13\.b,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.h,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp X0,PN0\.H,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x30,pn0\.h,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp xzr,pn0\.h,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn15\.h,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.h,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp X20,PN9\.h,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.s,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp X0,PN0\.s,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x30,pn0\.s,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp xzr,pn0\.s,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn15\.s,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.s,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp X15,PN8\.s,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.d,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp X0,PN0\.d,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x30,pn0\.d,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp xzr,pn0\.d,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn15\.d,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.d,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `cntp X4,PN5\.d,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.b,pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext P0\.B,PN8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p15\.b,pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.b,pn15\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.b,pn8\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p4\.b,pn11\[2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.h,pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext P0\.H,PN8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p15\.h,pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.h,pn15\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.h,pn8\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p5\.h,pn14\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.s,pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext P0\.S,PN8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p15\.s,pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.s,pn15\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.s,pn8\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p6\.s,pn10\[2\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.d,pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext P0\.D,PN8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p15\.d,pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.d,pn15\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.d,pn8\[3\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext p7\.d,pn9\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.b,p1\.b},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.b-p1\.b},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {P0\.B-P1\.B},PN8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p14\.b-p15\.b},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.b,p0\.b},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.b-p0\.b},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.b-p1\.b},pn15\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.b-p1\.b},pn8\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p7\.b-p8\.b},pn12\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.h,p1\.h},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.h-p1\.h},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {P0\.H-P1\.H},PN8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p14\.h-p15\.h},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.h,p0\.h},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.h-p0\.h},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.h-p1\.h},pn15\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.h-p1\.h},pn8\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p2\.h-p3\.h},pn14\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.s,p1\.s},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.s-p1\.s},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {P0\.S-P1\.S},PN8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p14\.s-p15\.s},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.s,p0\.s},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.s-p0\.s},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.s-p1\.s},pn15\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.s-p1\.s},pn8\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p5\.s-p6\.s},pn13\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.d,p1\.d},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.d-p1\.d},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {P0\.D-P1\.D},PN8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p14\.d-p15\.d},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.d,p0\.d},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.d-p0\.d},pn8\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.d-p1\.d},pn15\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.d-p1\.d},pn8\[1\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `pext {p12\.d-p13\.d},pn9\[0\]'
+[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn8\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn11\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn15\.b'
+[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn8\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn9\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn15\.h'
+[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn8\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn14\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn15\.s'
+[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn8\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn12\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn15\.d'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z1\.b},pn8,{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z30\.b-z31\.b},pn8,{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z1\.b},pn15,{z0\.b-z1\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z1\.b},pn8,{z30\.b-z31\.b},{z0\.b-z1\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z1\.b},pn8,{z0\.b-z1\.b},{z30\.b-z31\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z2\.b-z3\.b},pn12,{z6\.b-z7\.b},{z10\.b-z11\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z1\.h},pn8,{z0\.h-z1\.h},{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z30\.h-z31\.h},pn8,{z0\.h-z1\.h},{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z1\.h},pn15,{z0\.h-z1\.h},{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z1\.h},pn8,{z30\.h-z31\.h},{z0\.h-z1\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z1\.h},pn8,{z0\.h-z1\.h},{z30\.h-z31\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z12\.h-z13\.h},pn9,{z14\.h-z15\.h},{z16\.h-z17\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z1\.s},pn8,{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z30\.s-z31\.s},pn8,{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z1\.s},pn15,{z0\.s-z1\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z1\.s},pn8,{z30\.s-z31\.s},{z0\.s-z1\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z1\.s},pn8,{z0\.s-z1\.s},{z30\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z18\.s-z19\.s},pn11,{z22\.s-z23\.s},{z24\.s-z25\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z1\.d},pn8,{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z30\.d-z31\.d},pn8,{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z1\.d},pn15,{z0\.d-z1\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z1\.d},pn8,{z30\.d-z31\.d},{z0\.d-z1\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z1\.d},pn8,{z0\.d-z1\.d},{z30\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z8\.d-z9\.d},pn14,{z26\.d-z27\.d},{z28\.d-z29\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z28\.b-z31\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z3\.b},pn8,{z28\.b-z31\.b},{z0\.b-z3\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z28\.b-z31\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z4\.b-z7\.b},pn10,{z8\.b-z11\.b},{z12\.b-z15\.b}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z3\.h},pn8,{z0\.h-z3\.h},{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z28\.h-z31\.h},pn8,{z0\.h-z3\.h},{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z3\.h},pn8,{z28\.h-z31\.h},{z0\.h-z3\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z3\.h},pn8,{z0\.h-z3\.h},{z28\.h-z31\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z8\.h-z11\.h},pn10,{z16\.h-z19\.h},{z20\.h-z23\.h}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z3\.s},pn8,{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z28\.s-z31\.s},pn8,{z0\.s-z3\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z3\.s},pn8,{z28\.s-z31\.s},{z0\.s-z3\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z3\.s},pn8,{z0\.s-z3\.s},{z28\.s-z31\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z16\.s-z19\.s},pn10,{z20\.s-z23\.s},{z24\.s-z27\.s}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z3\.d},pn8,{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z28\.d-z31\.d},pn8,{z0\.d-z3\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z3\.d},pn8,{z28\.d-z31\.d},{z0\.d-z3\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z3\.d},pn8,{z0\.d-z3\.d},{z28\.d-z31\.d}'
+[^ :]+:[0-9]+: Error: selected processor does not support `sel {z20\.d-z23\.d},pn10,{z4\.d-z7\.d},{z8\.d-z11\.d}'
--- /dev/null
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: 25208200 cntp x0, pn0\.b, vlx2
+[^:]+: 25208200 cntp x0, pn0\.b, vlx2
+[^:]+: 2520821e cntp x30, pn0\.b, vlx2
+[^:]+: 2520821f cntp xzr, pn0\.b, vlx2
+[^:]+: 252083e0 cntp x0, pn15\.b, vlx2
+[^:]+: 25208600 cntp x0, pn0\.b, vlx4
+[^:]+: 252087ab cntp x11, pn13\.b, vlx4
+[^:]+: 25608200 cntp x0, pn0\.h, vlx2
+[^:]+: 25608200 cntp x0, pn0\.h, vlx2
+[^:]+: 2560821e cntp x30, pn0\.h, vlx2
+[^:]+: 2560821f cntp xzr, pn0\.h, vlx2
+[^:]+: 256083e0 cntp x0, pn15\.h, vlx2
+[^:]+: 25608600 cntp x0, pn0\.h, vlx4
+[^:]+: 25608334 cntp x20, pn9\.h, vlx2
+[^:]+: 25a08200 cntp x0, pn0\.s, vlx2
+[^:]+: 25a08200 cntp x0, pn0\.s, vlx2
+[^:]+: 25a0821e cntp x30, pn0\.s, vlx2
+[^:]+: 25a0821f cntp xzr, pn0\.s, vlx2
+[^:]+: 25a083e0 cntp x0, pn15\.s, vlx2
+[^:]+: 25a08600 cntp x0, pn0\.s, vlx4
+[^:]+: 25a0870f cntp x15, pn8\.s, vlx4
+[^:]+: 25e08200 cntp x0, pn0\.d, vlx2
+[^:]+: 25e08200 cntp x0, pn0\.d, vlx2
+[^:]+: 25e0821e cntp x30, pn0\.d, vlx2
+[^:]+: 25e0821f cntp xzr, pn0\.d, vlx2
+[^:]+: 25e083e0 cntp x0, pn15\.d, vlx2
+[^:]+: 25e08600 cntp x0, pn0\.d, vlx4
+[^:]+: 25e082a4 cntp x4, pn5\.d, vlx2
+[^:]+: 25207010 pext p0\.b, pn8\[0\]
+[^:]+: 25207010 pext p0\.b, pn8\[0\]
+[^:]+: 2520701f pext p15\.b, pn8\[0\]
+[^:]+: 252070f0 pext p0\.b, pn15\[0\]
+[^:]+: 25207310 pext p0\.b, pn8\[3\]
+[^:]+: 25207274 pext p4\.b, pn11\[2\]
+[^:]+: 25607010 pext p0\.h, pn8\[0\]
+[^:]+: 25607010 pext p0\.h, pn8\[0\]
+[^:]+: 2560701f pext p15\.h, pn8\[0\]
+[^:]+: 256070f0 pext p0\.h, pn15\[0\]
+[^:]+: 25607310 pext p0\.h, pn8\[3\]
+[^:]+: 256071d5 pext p5\.h, pn14\[1\]
+[^:]+: 25a07010 pext p0\.s, pn8\[0\]
+[^:]+: 25a07010 pext p0\.s, pn8\[0\]
+[^:]+: 25a0701f pext p15\.s, pn8\[0\]
+[^:]+: 25a070f0 pext p0\.s, pn15\[0\]
+[^:]+: 25a07310 pext p0\.s, pn8\[3\]
+[^:]+: 25a07256 pext p6\.s, pn10\[2\]
+[^:]+: 25e07010 pext p0\.d, pn8\[0\]
+[^:]+: 25e07010 pext p0\.d, pn8\[0\]
+[^:]+: 25e0701f pext p15\.d, pn8\[0\]
+[^:]+: 25e070f0 pext p0\.d, pn15\[0\]
+[^:]+: 25e07310 pext p0\.d, pn8\[3\]
+[^:]+: 25e07137 pext p7\.d, pn9\[1\]
+[^:]+: 25207410 pext {p0\.b-p1\.b}, pn8\[0\]
+[^:]+: 25207410 pext {p0\.b-p1\.b}, pn8\[0\]
+[^:]+: 25207410 pext {p0\.b-p1\.b}, pn8\[0\]
+[^:]+: 2520741e pext {p14\.b-p15\.b}, pn8\[0\]
+[^:]+: 2520741f pext {p15\.b-p0\.b}, pn8\[0\]
+[^:]+: 2520741f pext {p15\.b-p0\.b}, pn8\[0\]
+[^:]+: 252074f0 pext {p0\.b-p1\.b}, pn15\[0\]
+[^:]+: 25207510 pext {p0\.b-p1\.b}, pn8\[1\]
+[^:]+: 25207497 pext {p7\.b-p8\.b}, pn12\[0\]
+[^:]+: 25607410 pext {p0\.h-p1\.h}, pn8\[0\]
+[^:]+: 25607410 pext {p0\.h-p1\.h}, pn8\[0\]
+[^:]+: 25607410 pext {p0\.h-p1\.h}, pn8\[0\]
+[^:]+: 2560741e pext {p14\.h-p15\.h}, pn8\[0\]
+[^:]+: 2560741f pext {p15\.h-p0\.h}, pn8\[0\]
+[^:]+: 2560741f pext {p15\.h-p0\.h}, pn8\[0\]
+[^:]+: 256074f0 pext {p0\.h-p1\.h}, pn15\[0\]
+[^:]+: 25607510 pext {p0\.h-p1\.h}, pn8\[1\]
+[^:]+: 256074d2 pext {p2\.h-p3\.h}, pn14\[0\]
+[^:]+: 25a07410 pext {p0\.s-p1\.s}, pn8\[0\]
+[^:]+: 25a07410 pext {p0\.s-p1\.s}, pn8\[0\]
+[^:]+: 25a07410 pext {p0\.s-p1\.s}, pn8\[0\]
+[^:]+: 25a0741e pext {p14\.s-p15\.s}, pn8\[0\]
+[^:]+: 25a0741f pext {p15\.s-p0\.s}, pn8\[0\]
+[^:]+: 25a0741f pext {p15\.s-p0\.s}, pn8\[0\]
+[^:]+: 25a074f0 pext {p0\.s-p1\.s}, pn15\[0\]
+[^:]+: 25a07510 pext {p0\.s-p1\.s}, pn8\[1\]
+[^:]+: 25a074b5 pext {p5\.s-p6\.s}, pn13\[0\]
+[^:]+: 25e07410 pext {p0\.d-p1\.d}, pn8\[0\]
+[^:]+: 25e07410 pext {p0\.d-p1\.d}, pn8\[0\]
+[^:]+: 25e07410 pext {p0\.d-p1\.d}, pn8\[0\]
+[^:]+: 25e0741e pext {p14\.d-p15\.d}, pn8\[0\]
+[^:]+: 25e0741f pext {p15\.d-p0\.d}, pn8\[0\]
+[^:]+: 25e0741f pext {p15\.d-p0\.d}, pn8\[0\]
+[^:]+: 25e074f0 pext {p0\.d-p1\.d}, pn15\[0\]
+[^:]+: 25e07510 pext {p0\.d-p1\.d}, pn8\[1\]
+[^:]+: 25e0743c pext {p12\.d-p13\.d}, pn9\[0\]
+[^:]+: 25207810 ptrue pn8\.b
+[^:]+: 25207813 ptrue pn11\.b
+[^:]+: 25207817 ptrue pn15\.b
+[^:]+: 25607810 ptrue pn8\.h
+[^:]+: 25607811 ptrue pn9\.h
+[^:]+: 25607817 ptrue pn15\.h
+[^:]+: 25a07810 ptrue pn8\.s
+[^:]+: 25a07816 ptrue pn14\.s
+[^:]+: 25a07817 ptrue pn15\.s
+[^:]+: 25e07810 ptrue pn8\.d
+[^:]+: 25e07814 ptrue pn12\.d
+[^:]+: 25e07817 ptrue pn15\.d
+[^:]+: c1208000 sel {z0\.b-z1\.b}, pn8, {z0\.b-z1\.b}, {z0\.b-z1\.b}
+[^:]+: c120801e sel {z30\.b-z31\.b}, pn8, {z0\.b-z1\.b}, {z0\.b-z1\.b}
+[^:]+: c1209c00 sel {z0\.b-z1\.b}, pn15, {z0\.b-z1\.b}, {z0\.b-z1\.b}
+[^:]+: c12083c0 sel {z0\.b-z1\.b}, pn8, {z30\.b-z31\.b}, {z0\.b-z1\.b}
+[^:]+: c13e8000 sel {z0\.b-z1\.b}, pn8, {z0\.b-z1\.b}, {z30\.b-z31\.b}
+[^:]+: c12a90c2 sel {z2\.b-z3\.b}, pn12, {z6\.b-z7\.b}, {z10\.b-z11\.b}
+[^:]+: c1608000 sel {z0\.h-z1\.h}, pn8, {z0\.h-z1\.h}, {z0\.h-z1\.h}
+[^:]+: c160801e sel {z30\.h-z31\.h}, pn8, {z0\.h-z1\.h}, {z0\.h-z1\.h}
+[^:]+: c1609c00 sel {z0\.h-z1\.h}, pn15, {z0\.h-z1\.h}, {z0\.h-z1\.h}
+[^:]+: c16083c0 sel {z0\.h-z1\.h}, pn8, {z30\.h-z31\.h}, {z0\.h-z1\.h}
+[^:]+: c17e8000 sel {z0\.h-z1\.h}, pn8, {z0\.h-z1\.h}, {z30\.h-z31\.h}
+[^:]+: c17085cc sel {z12\.h-z13\.h}, pn9, {z14\.h-z15\.h}, {z16\.h-z17\.h}
+[^:]+: c1a08000 sel {z0\.s-z1\.s}, pn8, {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+: c1a0801e sel {z30\.s-z31\.s}, pn8, {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+: c1a09c00 sel {z0\.s-z1\.s}, pn15, {z0\.s-z1\.s}, {z0\.s-z1\.s}
+[^:]+: c1a083c0 sel {z0\.s-z1\.s}, pn8, {z30\.s-z31\.s}, {z0\.s-z1\.s}
+[^:]+: c1be8000 sel {z0\.s-z1\.s}, pn8, {z0\.s-z1\.s}, {z30\.s-z31\.s}
+[^:]+: c1b88ed2 sel {z18\.s-z19\.s}, pn11, {z22\.s-z23\.s}, {z24\.s-z25\.s}
+[^:]+: c1e08000 sel {z0\.d-z1\.d}, pn8, {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+: c1e0801e sel {z30\.d-z31\.d}, pn8, {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+: c1e09c00 sel {z0\.d-z1\.d}, pn15, {z0\.d-z1\.d}, {z0\.d-z1\.d}
+[^:]+: c1e083c0 sel {z0\.d-z1\.d}, pn8, {z30\.d-z31\.d}, {z0\.d-z1\.d}
+[^:]+: c1fe8000 sel {z0\.d-z1\.d}, pn8, {z0\.d-z1\.d}, {z30\.d-z31\.d}
+[^:]+: c1fc9b48 sel {z8\.d-z9\.d}, pn14, {z26\.d-z27\.d}, {z28\.d-z29\.d}
+[^:]+: c1218000 sel {z0\.b-z3\.b}, pn8, {z0\.b-z3\.b}, {z0\.b-z3\.b}
+[^:]+: c121801c sel {z28\.b-z31\.b}, pn8, {z0\.b-z3\.b}, {z0\.b-z3\.b}
+[^:]+: c1218380 sel {z0\.b-z3\.b}, pn8, {z28\.b-z31\.b}, {z0\.b-z3\.b}
+[^:]+: c13d8000 sel {z0\.b-z3\.b}, pn8, {z0\.b-z3\.b}, {z28\.b-z31\.b}
+[^:]+: c12d8904 sel {z4\.b-z7\.b}, pn10, {z8\.b-z11\.b}, {z12\.b-z15\.b}
+[^:]+: c1618000 sel {z0\.h-z3\.h}, pn8, {z0\.h-z3\.h}, {z0\.h-z3\.h}
+[^:]+: c161801c sel {z28\.h-z31\.h}, pn8, {z0\.h-z3\.h}, {z0\.h-z3\.h}
+[^:]+: c1618380 sel {z0\.h-z3\.h}, pn8, {z28\.h-z31\.h}, {z0\.h-z3\.h}
+[^:]+: c17d8000 sel {z0\.h-z3\.h}, pn8, {z0\.h-z3\.h}, {z28\.h-z31\.h}
+[^:]+: c1758a08 sel {z8\.h-z11\.h}, pn10, {z16\.h-z19\.h}, {z20\.h-z23\.h}
+[^:]+: c1a18000 sel {z0\.s-z3\.s}, pn8, {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+: c1a1801c sel {z28\.s-z31\.s}, pn8, {z0\.s-z3\.s}, {z0\.s-z3\.s}
+[^:]+: c1a18380 sel {z0\.s-z3\.s}, pn8, {z28\.s-z31\.s}, {z0\.s-z3\.s}
+[^:]+: c1bd8000 sel {z0\.s-z3\.s}, pn8, {z0\.s-z3\.s}, {z28\.s-z31\.s}
+[^:]+: c1b98a90 sel {z16\.s-z19\.s}, pn10, {z20\.s-z23\.s}, {z24\.s-z27\.s}
+[^:]+: c1e18000 sel {z0\.d-z3\.d}, pn8, {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+: c1e1801c sel {z28\.d-z31\.d}, pn8, {z0\.d-z3\.d}, {z0\.d-z3\.d}
+[^:]+: c1e18380 sel {z0\.d-z3\.d}, pn8, {z28\.d-z31\.d}, {z0\.d-z3\.d}
+[^:]+: c1fd8000 sel {z0\.d-z3\.d}, pn8, {z0\.d-z3\.d}, {z28\.d-z31\.d}
+[^:]+: c1e98894 sel {z20\.d-z23\.d}, pn10, {z4\.d-z7\.d}, {z8\.d-z11\.d}
--- /dev/null
+ cntp x0, pn0.b, vlx2
+ CNTP X0, PN0.B, VLx2
+ cntp x30, pn0.b, vlx2
+ cntp xzr, pn0.b, vlx2
+ cntp x0, pn15.b, vlx2
+ cntp x0, pn0.b, vlx4
+ CNTP X11, PN13.b, VLx4
+
+ cntp x0, pn0.h, vlx2
+ CNTP X0, PN0.H, VLx2
+ cntp x30, pn0.h, vlx2
+ cntp xzr, pn0.h, vlx2
+ cntp x0, pn15.h, vlx2
+ cntp x0, pn0.h, vlx4
+ CNTP X20, PN9.h, VLx2
+
+ cntp x0, pn0.s, vlx2
+ CNTP X0, PN0.s, VLx2
+ cntp x30, pn0.s, vlx2
+ cntp xzr, pn0.s, vlx2
+ cntp x0, pn15.s, vlx2
+ cntp x0, pn0.s, vlx4
+ CNTP X15, PN8.s, VLx4
+
+ cntp x0, pn0.d, vlx2
+ CNTP X0, PN0.d, VLx2
+ cntp x30, pn0.d, vlx2
+ cntp xzr, pn0.d, vlx2
+ cntp x0, pn15.d, vlx2
+ cntp x0, pn0.d, vlx4
+ CNTP X4, PN5.d, VLx2
+
+ pext p0.b, pn8[0]
+ PEXT P0.B, PN8[0]
+ pext p15.b, pn8[0]
+ pext p0.b, pn15[0]
+ pext p0.b, pn8[3]
+ pext p4.b, pn11[2]
+
+ pext p0.h, pn8[0]
+ PEXT P0.H, PN8[0]
+ pext p15.h, pn8[0]
+ pext p0.h, pn15[0]
+ pext p0.h, pn8[3]
+ pext p5.h, pn14[1]
+
+ pext p0.s, pn8[0]
+ PEXT P0.S, PN8[0]
+ pext p15.s, pn8[0]
+ pext p0.s, pn15[0]
+ pext p0.s, pn8[3]
+ pext p6.s, pn10[2]
+
+ pext p0.d, pn8[0]
+ PEXT P0.D, PN8[0]
+ pext p15.d, pn8[0]
+ pext p0.d, pn15[0]
+ pext p0.d, pn8[3]
+ pext p7.d, pn9[1]
+
+ pext { p0.b, p1.b }, pn8[0]
+ pext { p0.b - p1.b }, pn8[0]
+ PEXT { P0.B - P1.B }, PN8[0]
+ pext { p14.b - p15.b }, pn8[0]
+ pext { p15.b, p0.b }, pn8[0]
+ pext { p15.b - p0.b }, pn8[0]
+ pext { p0.b - p1.b }, pn15[0]
+ pext { p0.b - p1.b }, pn8[1]
+ pext { p7.b - p8.b }, pn12[0]
+
+ pext { p0.h, p1.h }, pn8[0]
+ pext { p0.h - p1.h }, pn8[0]
+ PEXT { P0.H - P1.H }, PN8[0]
+ pext { p14.h - p15.h }, pn8[0]
+ pext { p15.h, p0.h }, pn8[0]
+ pext { p15.h - p0.h }, pn8[0]
+ pext { p0.h - p1.h }, pn15[0]
+ pext { p0.h - p1.h }, pn8[1]
+ pext { p2.h - p3.h }, pn14[0]
+
+ pext { p0.s, p1.s }, pn8[0]
+ pext { p0.s - p1.s }, pn8[0]
+ PEXT { P0.S - P1.S }, PN8[0]
+ pext { p14.s - p15.s }, pn8[0]
+ pext { p15.s, p0.s }, pn8[0]
+ pext { p15.s - p0.s }, pn8[0]
+ pext { p0.s - p1.s }, pn15[0]
+ pext { p0.s - p1.s }, pn8[1]
+ pext { p5.s - p6.s }, pn13[0]
+
+ pext { p0.d, p1.d }, pn8[0]
+ pext { p0.d - p1.d }, pn8[0]
+ PEXT { P0.D - P1.D }, PN8[0]
+ pext { p14.d - p15.d }, pn8[0]
+ pext { p15.d, p0.d }, pn8[0]
+ pext { p15.d - p0.d }, pn8[0]
+ pext { p0.d - p1.d }, pn15[0]
+ pext { p0.d - p1.d }, pn8[1]
+ pext { p12.d - p13.d }, pn9[0]
+
+ ptrue pn8.b
+ ptrue pn11.b
+ ptrue pn15.b
+ ptrue pn8.h
+ ptrue pn9.h
+ ptrue pn15.h
+ ptrue pn8.s
+ ptrue pn14.s
+ ptrue pn15.s
+ ptrue pn8.d
+ ptrue pn12.d
+ ptrue pn15.d
+
+ sel { z0.b - z1.b }, pn8, { z0.b - z1.b }, { z0.b - z1.b }
+ sel { z30.b - z31.b }, pn8, { z0.b - z1.b }, { z0.b - z1.b }
+ sel { z0.b - z1.b }, pn15, { z0.b - z1.b }, { z0.b - z1.b }
+ sel { z0.b - z1.b }, pn8, { z30.b - z31.b }, { z0.b - z1.b }
+ sel { z0.b - z1.b }, pn8, { z0.b - z1.b }, { z30.b - z31.b }
+ sel { z2.b - z3.b }, pn12, { z6.b - z7.b }, { z10.b - z11.b }
+
+ sel { z0.h - z1.h }, pn8, { z0.h - z1.h }, { z0.h - z1.h }
+ sel { z30.h - z31.h }, pn8, { z0.h - z1.h }, { z0.h - z1.h }
+ sel { z0.h - z1.h }, pn15, { z0.h - z1.h }, { z0.h - z1.h }
+ sel { z0.h - z1.h }, pn8, { z30.h - z31.h }, { z0.h - z1.h }
+ sel { z0.h - z1.h }, pn8, { z0.h - z1.h }, { z30.h - z31.h }
+ sel { z12.h - z13.h }, pn9, { z14.h - z15.h }, { z16.h - z17.h }
+
+ sel { z0.s - z1.s }, pn8, { z0.s - z1.s }, { z0.s - z1.s }
+ sel { z30.s - z31.s }, pn8, { z0.s - z1.s }, { z0.s - z1.s }
+ sel { z0.s - z1.s }, pn15, { z0.s - z1.s }, { z0.s - z1.s }
+ sel { z0.s - z1.s }, pn8, { z30.s - z31.s }, { z0.s - z1.s }
+ sel { z0.s - z1.s }, pn8, { z0.s - z1.s }, { z30.s - z31.s }
+ sel { z18.s - z19.s }, pn11, { z22.s - z23.s }, { z24.s - z25.s }
+
+ sel { z0.d - z1.d }, pn8, { z0.d - z1.d }, { z0.d - z1.d }
+ sel { z30.d - z31.d }, pn8, { z0.d - z1.d }, { z0.d - z1.d }
+ sel { z0.d - z1.d }, pn15, { z0.d - z1.d }, { z0.d - z1.d }
+ sel { z0.d - z1.d }, pn8, { z30.d - z31.d }, { z0.d - z1.d }
+ sel { z0.d - z1.d }, pn8, { z0.d - z1.d }, { z30.d - z31.d }
+ sel { z8.d - z9.d }, pn14, { z26.d - z27.d }, { z28.d - z29.d }
+
+ sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }
+ sel { z28.b - z31.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }
+ sel { z0.b - z3.b }, pn8, { z28.b - z31.b }, { z0.b - z3.b }
+ sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z28.b - z31.b }
+ sel { z4.b - z7.b }, pn10, { z8.b - z11.b }, { z12.b - z15.b }
+
+ sel { z0.h - z3.h }, pn8, { z0.h - z3.h }, { z0.h - z3.h }
+ sel { z28.h - z31.h }, pn8, { z0.h - z3.h }, { z0.h - z3.h }
+ sel { z0.h - z3.h }, pn8, { z28.h - z31.h }, { z0.h - z3.h }
+ sel { z0.h - z3.h }, pn8, { z0.h - z3.h }, { z28.h - z31.h }
+ sel { z8.h - z11.h }, pn10, { z16.h - z19.h }, { z20.h - z23.h }
+
+ sel { z0.s - z3.s }, pn8, { z0.s - z3.s }, { z0.s - z3.s }
+ sel { z28.s - z31.s }, pn8, { z0.s - z3.s }, { z0.s - z3.s }
+ sel { z0.s - z3.s }, pn8, { z28.s - z31.s }, { z0.s - z3.s }
+ sel { z0.s - z3.s }, pn8, { z0.s - z3.s }, { z28.s - z31.s }
+ sel { z16.s - z19.s }, pn10, { z20.s - z23.s }, { z24.s - z27.s }
+
+ sel { z0.d - z3.d }, pn8, { z0.d - z3.d }, { z0.d - z3.d }
+ sel { z28.d - z31.d }, pn8, { z0.d - z3.d }, { z0.d - z3.d }
+ sel { z0.d - z3.d }, pn8, { z28.d - z31.d }, { z0.d - z3.d }
+ sel { z0.d - z3.d }, pn8, { z0.d - z3.d }, { z28.d - z31.d }
+ sel { z20.d - z23.d }, pn10, { z4.d - z7.d }, { z8.d - z11.d }
--- /dev/null
+#as: -march=armv8-a
+#source: sme2-7-invalid.s
+#error_output: sme2-7-invalid.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilege 0,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege pn8\.b,0,x0,vlx2'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege pn8\.b,x0,0,vlx2'
+[^ :]+:[0-9]+: Error: operand 4 must be VLx2 or VLx4 -- `whilege pn8\.b,x0,x0,0'
+[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `whilege pn0\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `whilege p8\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilege z8\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: comma expected between operands at operand 4 -- `whilege pn8\.b,x0,x0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilege pn8\.b,w0,w0,vlx2'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: whilege pn8\.b, x0, x0, vlx2
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: whilege pn8\.h, x0, x0, vlx2
+[^ :]+:[0-9]+: Info: whilege pn8\.s, x0, x0, vlx2
+[^ :]+:[0-9]+: Info: whilege pn8\.d, x0, x0, vlx2
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege pn8\.b,sp,x0,vlx2'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege pn8\.b,x0,sp,vlx2'
+[^ :]+:[0-9]+: Error: operand 4 must be VLx2 or VLx4 -- `whilege pn8\.b,x0,x0,#0'
+[^ :]+:[0-9]+: Error: operand 4 must be VLx2 or VLx4 -- `whilege pn8\.b,x0,x0,1'
--- /dev/null
+ whilege 0, x0, x0, vlx2
+ whilege pn8.b, 0, x0, vlx2
+ whilege pn8.b, x0, 0, vlx2
+ whilege pn8.b, x0, x0, 0
+
+ whilege pn0.b, x0, x0, vlx2
+ whilege p8.b, x0, x0, vlx2
+ whilege z8.b, x0, x0, vlx2
+ whilege pn8.b, x0, x0
+ whilege pn8.b, w0, w0, vlx2
+ whilege pn8.b, sp, x0, vlx2
+ whilege pn8.b, x0, sp, vlx2
+ whilege pn8.b, x0, x0, #0
+ whilege pn8.b, x0, x0, 1
--- /dev/null
+#as: -march=armv8-a+sme
+#source: sme2-7.s
+#error_output: sme2-7-noarch.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.B,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.B,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn15\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn11\.b,x20,x1,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.h,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.h,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn15\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn14\.h,x14,x25,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.s,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.s,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn15\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn9\.s,x4,x27,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.d,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.d,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn15\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn13\.d,x26,x9,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.B,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.B,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn15\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn11\.b,x20,x1,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.h,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.h,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn15\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn14\.h,x14,x25,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.s,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.s,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn15\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn9\.s,x4,x27,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.d,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.d,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn15\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn13\.d,x26,x9,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.B,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.B,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn15\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn11\.b,x20,x1,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.h,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.h,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn15\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn14\.h,x14,x25,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.s,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.s,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn15\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn9\.s,x4,x27,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.d,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.d,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn15\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn13\.d,x26,x9,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.B,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.B,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn15\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn11\.b,x20,x1,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.h,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.h,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn15\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn14\.h,x14,x25,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.s,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.s,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn15\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn9\.s,x4,x27,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.d,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.d,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn15\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn13\.d,x26,x9,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.B,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.B,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn15\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn11\.b,x20,x1,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.h,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.h,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn15\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn14\.h,x14,x25,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.s,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.s,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn15\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn9\.s,x4,x27,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.d,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.d,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn15\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn13\.d,x26,x9,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.B,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.B,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn15\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn11\.b,x20,x1,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.h,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.h,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn15\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn14\.h,x14,x25,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.s,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.s,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn15\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn9\.s,x4,x27,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.d,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.d,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn15\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn13\.d,x26,x9,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.B,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.B,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn15\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn11\.b,x20,x1,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.h,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.h,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn15\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn14\.h,x14,x25,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.s,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.s,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn15\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn9\.s,x4,x27,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.d,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.d,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn15\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn13\.d,x26,x9,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.B,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.B,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn15\.b,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn11\.b,x20,x1,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.h,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.h,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn15\.h,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn14\.h,x14,x25,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.s,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.s,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn15\.s,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn9\.s,x4,x27,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,x0,x0,vlx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.d,X0,X0,VLx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.d,X0,X0,VLx4'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn15\.d,x0,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,x30,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,xzr,x0,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,x0,x30,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,x0,xzr,vlx2'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn13\.d,x26,x9,vlx4'
--- /dev/null
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
+[^:]+:
+[^:]+: 25204010 whilege pn8\.b, x0, x0, vlx2
+[^:]+: 25206010 whilege pn8\.b, x0, x0, vlx4
+[^:]+: 25204010 whilege pn8\.b, x0, x0, vlx2
+[^:]+: 25206010 whilege pn8\.b, x0, x0, vlx4
+[^:]+: 25204017 whilege pn15\.b, x0, x0, vlx2
+[^:]+: 252043d0 whilege pn8\.b, x30, x0, vlx2
+[^:]+: 252043f0 whilege pn8\.b, xzr, x0, vlx2
+[^:]+: 253e4010 whilege pn8\.b, x0, x30, vlx2
+[^:]+: 253f4010 whilege pn8\.b, x0, xzr, vlx2
+[^:]+: 25216293 whilege pn11\.b, x20, x1, vlx4
+[^:]+: 25604010 whilege pn8\.h, x0, x0, vlx2
+[^:]+: 25606010 whilege pn8\.h, x0, x0, vlx4
+[^:]+: 25604010 whilege pn8\.h, x0, x0, vlx2
+[^:]+: 25606010 whilege pn8\.h, x0, x0, vlx4
+[^:]+: 25604017 whilege pn15\.h, x0, x0, vlx2
+[^:]+: 256043d0 whilege pn8\.h, x30, x0, vlx2
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+[^:]+: 25204018 whilegt pn8\.b, x0, x0, vlx2
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+[^:]+: 25604018 whilegt pn8\.h, x0, x0, vlx2
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+[^:]+: 25a06c18 whilels pn8\.s, x0, x0, vlx4
+[^:]+: 25a04c18 whilels pn8\.s, x0, x0, vlx2
+[^:]+: 25a06c18 whilels pn8\.s, x0, x0, vlx4
+[^:]+: 25a04c1f whilels pn15\.s, x0, x0, vlx2
+[^:]+: 25a04fd8 whilels pn8\.s, x30, x0, vlx2
+[^:]+: 25a04ff8 whilels pn8\.s, xzr, x0, vlx2
+[^:]+: 25be4c18 whilels pn8\.s, x0, x30, vlx2
+[^:]+: 25bf4c18 whilels pn8\.s, x0, xzr, vlx2
+[^:]+: 25bb4c99 whilels pn9\.s, x4, x27, vlx2
+[^:]+: 25e04c18 whilels pn8\.d, x0, x0, vlx2
+[^:]+: 25e06c18 whilels pn8\.d, x0, x0, vlx4
+[^:]+: 25e04c18 whilels pn8\.d, x0, x0, vlx2
+[^:]+: 25e06c18 whilels pn8\.d, x0, x0, vlx4
+[^:]+: 25e04c1f whilels pn15\.d, x0, x0, vlx2
+[^:]+: 25e04fd8 whilels pn8\.d, x30, x0, vlx2
+[^:]+: 25e04ff8 whilels pn8\.d, xzr, x0, vlx2
+[^:]+: 25fe4c18 whilels pn8\.d, x0, x30, vlx2
+[^:]+: 25ff4c18 whilels pn8\.d, x0, xzr, vlx2
+[^:]+: 25e96f5d whilels pn13\.d, x26, x9, vlx4
--- /dev/null
+ whilege pn8.b, x0, x0, vlx2
+ whilege pn8.b, x0, x0, vlx4
+ WHILEGE PN8.B, X0, X0, VLx2
+ WHILEGE PN8.B, X0, X0, VLx4
+ whilege pn15.b, x0, x0, vlx2
+ whilege pn8.b, x30, x0, vlx2
+ whilege pn8.b, xzr, x0, vlx2
+ whilege pn8.b, x0, x30, vlx2
+ whilege pn8.b, x0, xzr, vlx2
+ whilege pn11.b, x20, x1, vlx4
+
+ whilege pn8.h, x0, x0, vlx2
+ whilege pn8.h, x0, x0, vlx4
+ WHILEGE PN8.h, X0, X0, VLx2
+ WHILEGE PN8.h, X0, X0, VLx4
+ whilege pn15.h, x0, x0, vlx2
+ whilege pn8.h, x30, x0, vlx2
+ whilege pn8.h, xzr, x0, vlx2
+ whilege pn8.h, x0, x30, vlx2
+ whilege pn8.h, x0, xzr, vlx2
+ whilege pn14.h, x14, x25, vlx4
+
+ whilege pn8.s, x0, x0, vlx2
+ whilege pn8.s, x0, x0, vlx4
+ WHILEGE PN8.s, X0, X0, VLx2
+ WHILEGE PN8.s, X0, X0, VLx4
+ whilege pn15.s, x0, x0, vlx2
+ whilege pn8.s, x30, x0, vlx2
+ whilege pn8.s, xzr, x0, vlx2
+ whilege pn8.s, x0, x30, vlx2
+ whilege pn8.s, x0, xzr, vlx2
+ whilege pn9.s, x4, x27, vlx2
+
+ whilege pn8.d, x0, x0, vlx2
+ whilege pn8.d, x0, x0, vlx4
+ WHILEGE PN8.d, X0, X0, VLx2
+ WHILEGE PN8.d, X0, X0, VLx4
+ whilege pn15.d, x0, x0, vlx2
+ whilege pn8.d, x30, x0, vlx2
+ whilege pn8.d, xzr, x0, vlx2
+ whilege pn8.d, x0, x30, vlx2
+ whilege pn8.d, x0, xzr, vlx2
+ whilege pn13.d, x26, x9, vlx4
+
+ whilegt pn8.b, x0, x0, vlx2
+ whilegt pn8.b, x0, x0, vlx4
+ WHILEGT PN8.B, X0, X0, VLx2
+ WHILEGT PN8.B, X0, X0, VLx4
+ whilegt pn15.b, x0, x0, vlx2
+ whilegt pn8.b, x30, x0, vlx2
+ whilegt pn8.b, xzr, x0, vlx2
+ whilegt pn8.b, x0, x30, vlx2
+ whilegt pn8.b, x0, xzr, vlx2
+ whilegt pn11.b, x20, x1, vlx4
+
+ whilegt pn8.h, x0, x0, vlx2
+ whilegt pn8.h, x0, x0, vlx4
+ WHILEGT PN8.h, X0, X0, VLx2
+ WHILEGT PN8.h, X0, X0, VLx4
+ whilegt pn15.h, x0, x0, vlx2
+ whilegt pn8.h, x30, x0, vlx2
+ whilegt pn8.h, xzr, x0, vlx2
+ whilegt pn8.h, x0, x30, vlx2
+ whilegt pn8.h, x0, xzr, vlx2
+ whilegt pn14.h, x14, x25, vlx4
+
+ whilegt pn8.s, x0, x0, vlx2
+ whilegt pn8.s, x0, x0, vlx4
+ WHILEGT PN8.s, X0, X0, VLx2
+ WHILEGT PN8.s, X0, X0, VLx4
+ whilegt pn15.s, x0, x0, vlx2
+ whilegt pn8.s, x30, x0, vlx2
+ whilegt pn8.s, xzr, x0, vlx2
+ whilegt pn8.s, x0, x30, vlx2
+ whilegt pn8.s, x0, xzr, vlx2
+ whilegt pn9.s, x4, x27, vlx2
+
+ whilegt pn8.d, x0, x0, vlx2
+ whilegt pn8.d, x0, x0, vlx4
+ WHILEGT PN8.d, X0, X0, VLx2
+ WHILEGT PN8.d, X0, X0, VLx4
+ whilegt pn15.d, x0, x0, vlx2
+ whilegt pn8.d, x30, x0, vlx2
+ whilegt pn8.d, xzr, x0, vlx2
+ whilegt pn8.d, x0, x30, vlx2
+ whilegt pn8.d, x0, xzr, vlx2
+ whilegt pn13.d, x26, x9, vlx4
+
+ whilehi pn8.b, x0, x0, vlx2
+ whilehi pn8.b, x0, x0, vlx4
+ WHILEHI PN8.B, X0, X0, VLx2
+ WHILEHI PN8.B, X0, X0, VLx4
+ whilehi pn15.b, x0, x0, vlx2
+ whilehi pn8.b, x30, x0, vlx2
+ whilehi pn8.b, xzr, x0, vlx2
+ whilehi pn8.b, x0, x30, vlx2
+ whilehi pn8.b, x0, xzr, vlx2
+ whilehi pn11.b, x20, x1, vlx4
+
+ whilehi pn8.h, x0, x0, vlx2
+ whilehi pn8.h, x0, x0, vlx4
+ WHILEHI PN8.h, X0, X0, VLx2
+ WHILEHI PN8.h, X0, X0, VLx4
+ whilehi pn15.h, x0, x0, vlx2
+ whilehi pn8.h, x30, x0, vlx2
+ whilehi pn8.h, xzr, x0, vlx2
+ whilehi pn8.h, x0, x30, vlx2
+ whilehi pn8.h, x0, xzr, vlx2
+ whilehi pn14.h, x14, x25, vlx4
+
+ whilehi pn8.s, x0, x0, vlx2
+ whilehi pn8.s, x0, x0, vlx4
+ WHILEHI PN8.s, X0, X0, VLx2
+ WHILEHI PN8.s, X0, X0, VLx4
+ whilehi pn15.s, x0, x0, vlx2
+ whilehi pn8.s, x30, x0, vlx2
+ whilehi pn8.s, xzr, x0, vlx2
+ whilehi pn8.s, x0, x30, vlx2
+ whilehi pn8.s, x0, xzr, vlx2
+ whilehi pn9.s, x4, x27, vlx2
+
+ whilehi pn8.d, x0, x0, vlx2
+ whilehi pn8.d, x0, x0, vlx4
+ WHILEHI PN8.d, X0, X0, VLx2
+ WHILEHI PN8.d, X0, X0, VLx4
+ whilehi pn15.d, x0, x0, vlx2
+ whilehi pn8.d, x30, x0, vlx2
+ whilehi pn8.d, xzr, x0, vlx2
+ whilehi pn8.d, x0, x30, vlx2
+ whilehi pn8.d, x0, xzr, vlx2
+ whilehi pn13.d, x26, x9, vlx4
+
+ whilehs pn8.b, x0, x0, vlx2
+ whilehs pn8.b, x0, x0, vlx4
+ WHILEHS PN8.B, X0, X0, VLx2
+ WHILEHS PN8.B, X0, X0, VLx4
+ whilehs pn15.b, x0, x0, vlx2
+ whilehs pn8.b, x30, x0, vlx2
+ whilehs pn8.b, xzr, x0, vlx2
+ whilehs pn8.b, x0, x30, vlx2
+ whilehs pn8.b, x0, xzr, vlx2
+ whilehs pn11.b, x20, x1, vlx4
+
+ whilehs pn8.h, x0, x0, vlx2
+ whilehs pn8.h, x0, x0, vlx4
+ WHILEHS PN8.h, X0, X0, VLx2
+ WHILEHS PN8.h, X0, X0, VLx4
+ whilehs pn15.h, x0, x0, vlx2
+ whilehs pn8.h, x30, x0, vlx2
+ whilehs pn8.h, xzr, x0, vlx2
+ whilehs pn8.h, x0, x30, vlx2
+ whilehs pn8.h, x0, xzr, vlx2
+ whilehs pn14.h, x14, x25, vlx4
+
+ whilehs pn8.s, x0, x0, vlx2
+ whilehs pn8.s, x0, x0, vlx4
+ WHILEHS PN8.s, X0, X0, VLx2
+ WHILEHS PN8.s, X0, X0, VLx4
+ whilehs pn15.s, x0, x0, vlx2
+ whilehs pn8.s, x30, x0, vlx2
+ whilehs pn8.s, xzr, x0, vlx2
+ whilehs pn8.s, x0, x30, vlx2
+ whilehs pn8.s, x0, xzr, vlx2
+ whilehs pn9.s, x4, x27, vlx2
+
+ whilehs pn8.d, x0, x0, vlx2
+ whilehs pn8.d, x0, x0, vlx4
+ WHILEHS PN8.d, X0, X0, VLx2
+ WHILEHS PN8.d, X0, X0, VLx4
+ whilehs pn15.d, x0, x0, vlx2
+ whilehs pn8.d, x30, x0, vlx2
+ whilehs pn8.d, xzr, x0, vlx2
+ whilehs pn8.d, x0, x30, vlx2
+ whilehs pn8.d, x0, xzr, vlx2
+ whilehs pn13.d, x26, x9, vlx4
+
+ whilele pn8.b, x0, x0, vlx2
+ whilele pn8.b, x0, x0, vlx4
+ WHILELE PN8.B, X0, X0, VLx2
+ WHILELE PN8.B, X0, X0, VLx4
+ whilele pn15.b, x0, x0, vlx2
+ whilele pn8.b, x30, x0, vlx2
+ whilele pn8.b, xzr, x0, vlx2
+ whilele pn8.b, x0, x30, vlx2
+ whilele pn8.b, x0, xzr, vlx2
+ whilele pn11.b, x20, x1, vlx4
+
+ whilele pn8.h, x0, x0, vlx2
+ whilele pn8.h, x0, x0, vlx4
+ WHILELE PN8.h, X0, X0, VLx2
+ WHILELE PN8.h, X0, X0, VLx4
+ whilele pn15.h, x0, x0, vlx2
+ whilele pn8.h, x30, x0, vlx2
+ whilele pn8.h, xzr, x0, vlx2
+ whilele pn8.h, x0, x30, vlx2
+ whilele pn8.h, x0, xzr, vlx2
+ whilele pn14.h, x14, x25, vlx4
+
+ whilele pn8.s, x0, x0, vlx2
+ whilele pn8.s, x0, x0, vlx4
+ WHILELE PN8.s, X0, X0, VLx2
+ WHILELE PN8.s, X0, X0, VLx4
+ whilele pn15.s, x0, x0, vlx2
+ whilele pn8.s, x30, x0, vlx2
+ whilele pn8.s, xzr, x0, vlx2
+ whilele pn8.s, x0, x30, vlx2
+ whilele pn8.s, x0, xzr, vlx2
+ whilele pn9.s, x4, x27, vlx2
+
+ whilele pn8.d, x0, x0, vlx2
+ whilele pn8.d, x0, x0, vlx4
+ WHILELE PN8.d, X0, X0, VLx2
+ WHILELE PN8.d, X0, X0, VLx4
+ whilele pn15.d, x0, x0, vlx2
+ whilele pn8.d, x30, x0, vlx2
+ whilele pn8.d, xzr, x0, vlx2
+ whilele pn8.d, x0, x30, vlx2
+ whilele pn8.d, x0, xzr, vlx2
+ whilele pn13.d, x26, x9, vlx4
+
+ whilelt pn8.b, x0, x0, vlx2
+ whilelt pn8.b, x0, x0, vlx4
+ WHILELT PN8.B, X0, X0, VLx2
+ WHILELT PN8.B, X0, X0, VLx4
+ whilelt pn15.b, x0, x0, vlx2
+ whilelt pn8.b, x30, x0, vlx2
+ whilelt pn8.b, xzr, x0, vlx2
+ whilelt pn8.b, x0, x30, vlx2
+ whilelt pn8.b, x0, xzr, vlx2
+ whilelt pn11.b, x20, x1, vlx4
+
+ whilelt pn8.h, x0, x0, vlx2
+ whilelt pn8.h, x0, x0, vlx4
+ WHILELT PN8.h, X0, X0, VLx2
+ WHILELT PN8.h, X0, X0, VLx4
+ whilelt pn15.h, x0, x0, vlx2
+ whilelt pn8.h, x30, x0, vlx2
+ whilelt pn8.h, xzr, x0, vlx2
+ whilelt pn8.h, x0, x30, vlx2
+ whilelt pn8.h, x0, xzr, vlx2
+ whilelt pn14.h, x14, x25, vlx4
+
+ whilelt pn8.s, x0, x0, vlx2
+ whilelt pn8.s, x0, x0, vlx4
+ WHILELT PN8.s, X0, X0, VLx2
+ WHILELT PN8.s, X0, X0, VLx4
+ whilelt pn15.s, x0, x0, vlx2
+ whilelt pn8.s, x30, x0, vlx2
+ whilelt pn8.s, xzr, x0, vlx2
+ whilelt pn8.s, x0, x30, vlx2
+ whilelt pn8.s, x0, xzr, vlx2
+ whilelt pn9.s, x4, x27, vlx2
+
+ whilelt pn8.d, x0, x0, vlx2
+ whilelt pn8.d, x0, x0, vlx4
+ WHILELT PN8.d, X0, X0, VLx2
+ WHILELT PN8.d, X0, X0, VLx4
+ whilelt pn15.d, x0, x0, vlx2
+ whilelt pn8.d, x30, x0, vlx2
+ whilelt pn8.d, xzr, x0, vlx2
+ whilelt pn8.d, x0, x30, vlx2
+ whilelt pn8.d, x0, xzr, vlx2
+ whilelt pn13.d, x26, x9, vlx4
+
+ whilelo pn8.b, x0, x0, vlx2
+ whilelo pn8.b, x0, x0, vlx4
+ WHILELO PN8.B, X0, X0, VLx2
+ WHILELO PN8.B, X0, X0, VLx4
+ whilelo pn15.b, x0, x0, vlx2
+ whilelo pn8.b, x30, x0, vlx2
+ whilelo pn8.b, xzr, x0, vlx2
+ whilelo pn8.b, x0, x30, vlx2
+ whilelo pn8.b, x0, xzr, vlx2
+ whilelo pn11.b, x20, x1, vlx4
+
+ whilelo pn8.h, x0, x0, vlx2
+ whilelo pn8.h, x0, x0, vlx4
+ WHILELO PN8.h, X0, X0, VLx2
+ WHILELO PN8.h, X0, X0, VLx4
+ whilelo pn15.h, x0, x0, vlx2
+ whilelo pn8.h, x30, x0, vlx2
+ whilelo pn8.h, xzr, x0, vlx2
+ whilelo pn8.h, x0, x30, vlx2
+ whilelo pn8.h, x0, xzr, vlx2
+ whilelo pn14.h, x14, x25, vlx4
+
+ whilelo pn8.s, x0, x0, vlx2
+ whilelo pn8.s, x0, x0, vlx4
+ WHILELO PN8.s, X0, X0, VLx2
+ WHILELO PN8.s, X0, X0, VLx4
+ whilelo pn15.s, x0, x0, vlx2
+ whilelo pn8.s, x30, x0, vlx2
+ whilelo pn8.s, xzr, x0, vlx2
+ whilelo pn8.s, x0, x30, vlx2
+ whilelo pn8.s, x0, xzr, vlx2
+ whilelo pn9.s, x4, x27, vlx2
+
+ whilelo pn8.d, x0, x0, vlx2
+ whilelo pn8.d, x0, x0, vlx4
+ WHILELO PN8.d, X0, X0, VLx2
+ WHILELO PN8.d, X0, X0, VLx4
+ whilelo pn15.d, x0, x0, vlx2
+ whilelo pn8.d, x30, x0, vlx2
+ whilelo pn8.d, xzr, x0, vlx2
+ whilelo pn8.d, x0, x30, vlx2
+ whilelo pn8.d, x0, xzr, vlx2
+ whilelo pn13.d, x26, x9, vlx4
+
+ whilels pn8.b, x0, x0, vlx2
+ whilels pn8.b, x0, x0, vlx4
+ WHILELS PN8.B, X0, X0, VLx2
+ WHILELS PN8.B, X0, X0, VLx4
+ whilels pn15.b, x0, x0, vlx2
+ whilels pn8.b, x30, x0, vlx2
+ whilels pn8.b, xzr, x0, vlx2
+ whilels pn8.b, x0, x30, vlx2
+ whilels pn8.b, x0, xzr, vlx2
+ whilels pn11.b, x20, x1, vlx4
+
+ whilels pn8.h, x0, x0, vlx2
+ whilels pn8.h, x0, x0, vlx4
+ WHILELS PN8.h, X0, X0, VLx2
+ WHILELS PN8.h, X0, X0, VLx4
+ whilels pn15.h, x0, x0, vlx2
+ whilels pn8.h, x30, x0, vlx2
+ whilels pn8.h, xzr, x0, vlx2
+ whilels pn8.h, x0, x30, vlx2
+ whilels pn8.h, x0, xzr, vlx2
+ whilels pn14.h, x14, x25, vlx4
+
+ whilels pn8.s, x0, x0, vlx2
+ whilels pn8.s, x0, x0, vlx4
+ WHILELS PN8.s, X0, X0, VLx2
+ WHILELS PN8.s, X0, X0, VLx4
+ whilels pn15.s, x0, x0, vlx2
+ whilels pn8.s, x30, x0, vlx2
+ whilels pn8.s, xzr, x0, vlx2
+ whilels pn8.s, x0, x30, vlx2
+ whilels pn8.s, x0, xzr, vlx2
+ whilels pn9.s, x4, x27, vlx2
+
+ whilels pn8.d, x0, x0, vlx2
+ whilels pn8.d, x0, x0, vlx4
+ WHILELS PN8.d, X0, X0, VLx2
+ WHILELS PN8.d, X0, X0, VLx4
+ whilels pn15.d, x0, x0, vlx2
+ whilels pn8.d, x30, x0, vlx2
+ whilels pn8.d, xzr, x0, vlx2
+ whilels pn8.d, x0, x30, vlx2
+ whilels pn8.d, x0, xzr, vlx2
+ whilels pn13.d, x26, x9, vlx4
[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `psel 0,pn0,p0\.b\[w12,0\]'
+[^ :]+:[0-9]+: Error: expected an SVE predicate-as-counter register at operand 2 -- `psel pn0,0,p0\.b\[w12,0\]'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 3 -- `psel pn0,pn0,0'
[^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `psel pn0,p0,p0\.b\[w12,0\]'
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `psel pn,pn0,p0\.b\[w12,0\]'
[^ :]+:[0-9]+: Error: expected a predicate-as-mask rather than predicate-as-counter register at operand 3 -- `psel p0,p0,pn0\.b\[w12,0\]'
+ psel 0, pn0, p0.b[w12, 0]
+ psel pn0, 0, p0.b[w12, 0]
+ psel pn0, pn0, 0
+
psel pn0, p0, p0.b[w12, 0]
psel pn, pn0, p0.b[w12, 0]
psel p0, p0, pn0.b[w12, 0]
--- /dev/null
+#as: -march=armv8-a
+#source: sve2-sme2-2-invalid.s
+#error_output: sve2-sme2-2-invalid.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `whilege {p0\.b},x0,x0'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `whilege {p1\.b-p2\.b},x0,x0'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `whilege {p0\.b-p2\.b},x0,x0'
+[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `whilege {p0\.b-p3\.b},x0,x0'
+[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `whilege {p15\.b-p0\.b},x0,x0'
+[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 1 -- `whilege {p0\.b,p8\.b},x0,x0'
+[^ :]+:[0-9]+: Error: expected a predicate-as-mask rather than predicate-as-counter register at operand 1 -- `whilege {pn0\.b-pn1\.b},x0,x0'
+[^ :]+:[0-9]+: Error: missing type suffix at operand 1 -- `whilege {p0-p1},x0,x0'
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilege {p0\.q-p1\.q},x0,x0'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: whilege {p0\.b-p1\.b}, x0, x0
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: whilege {p0\.h-p1\.h}, x0, x0
+[^ :]+:[0-9]+: Info: whilege {p0\.s-p1\.s}, x0, x0
+[^ :]+:[0-9]+: Info: whilege {p0\.d-p1\.d}, x0, x0
+[^ :]+:[0-9]+: Error: operand mismatch -- `whilege {p0\.b-p1\.b},w0,w0'
+[^ :]+:[0-9]+: Info: did you mean this\?
+[^ :]+:[0-9]+: Info: whilege {p0\.b-p1\.b}, x0, x0
+[^ :]+:[0-9]+: Info: other valid variant\(s\):
+[^ :]+:[0-9]+: Info: whilege {p0\.h-p1\.h}, x0, x0
+[^ :]+:[0-9]+: Info: whilege {p0\.s-p1\.s}, x0, x0
+[^ :]+:[0-9]+: Info: whilege {p0\.d-p1\.d}, x0, x0
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege {p0\.b-p1\.b},sp,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege {p0\.b-p1\.b},x0,sp'
--- /dev/null
+ whilege { p0.b }, x0, x0
+ whilege { p1.b - p2.b }, x0, x0
+ whilege { p0.b - p2.b }, x0, x0
+ whilege { p0.b - p3.b }, x0, x0
+ whilege { p15.b - p0.b }, x0, x0
+ whilege { p0.b, p8.b }, x0, x0
+ whilege { pn0.b - pn1.b }, x0, x0
+ whilege { p0 - p1 }, x0, x0
+ whilege { p0.q - p1.q }, x0, x0
+ whilege { p0.b - p1.b }, w0, w0
+ whilege { p0.b - p1.b }, sp, x0
+ whilege { p0.b - p1.b }, x0, sp
--- /dev/null
+#as: -march=armv8-a+sme
+#source: sve2-sme2-2.s
+#error_output: sve2-sme2-2-noarch.l
--- /dev/null
+[^ :]+: Assembler messages:
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.b-p1\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {P0\.B-P1\.B},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p14\.b-p15\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.b-p1\.b},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.b-p1\.b},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.b-p1\.b},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.b-p1\.b},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p4\.b-p5\.b},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.h-p1\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {P0\.h-P1\.h},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p14\.h-p15\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.h-p1\.h},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.h-p1\.h},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.h-p1\.h},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.h-p1\.h},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p4\.h-p5\.h},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.s-p1\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {P0\.s-P1\.s},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p14\.s-p15\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.s-p1\.s},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.s-p1\.s},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.s-p1\.s},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.s-p1\.s},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p4\.s-p5\.s},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.d-p1\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {P0\.d-P1\.d},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p14\.d-p15\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.d-p1\.d},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.d-p1\.d},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.d-p1\.d},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.d-p1\.d},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p4\.d-p5\.d},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.b-p1\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {P0\.B-P1\.B},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p14\.b-p15\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.b-p1\.b},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.b-p1\.b},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.b-p1\.b},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.b-p1\.b},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p4\.b-p5\.b},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.h-p1\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {P0\.h-P1\.h},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p14\.h-p15\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.h-p1\.h},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.h-p1\.h},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.h-p1\.h},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.h-p1\.h},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p4\.h-p5\.h},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.s-p1\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {P0\.s-P1\.s},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p14\.s-p15\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.s-p1\.s},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.s-p1\.s},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.s-p1\.s},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.s-p1\.s},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p4\.s-p5\.s},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.d-p1\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {P0\.d-P1\.d},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p14\.d-p15\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.d-p1\.d},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.d-p1\.d},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.d-p1\.d},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.d-p1\.d},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p4\.d-p5\.d},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.b-p1\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {P0\.B-P1\.B},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p14\.b-p15\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.b-p1\.b},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.b-p1\.b},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.b-p1\.b},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.b-p1\.b},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p4\.b-p5\.b},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.h-p1\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {P0\.h-P1\.h},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p14\.h-p15\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.h-p1\.h},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.h-p1\.h},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.h-p1\.h},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.h-p1\.h},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p4\.h-p5\.h},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.s-p1\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {P0\.s-P1\.s},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p14\.s-p15\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.s-p1\.s},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.s-p1\.s},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.s-p1\.s},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.s-p1\.s},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p4\.s-p5\.s},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.d-p1\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {P0\.d-P1\.d},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p14\.d-p15\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.d-p1\.d},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.d-p1\.d},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.d-p1\.d},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.d-p1\.d},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p4\.d-p5\.d},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.b-p1\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {P0\.B-P1\.B},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p14\.b-p15\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.b-p1\.b},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.b-p1\.b},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.b-p1\.b},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.b-p1\.b},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p4\.b-p5\.b},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.h-p1\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {P0\.h-P1\.h},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p14\.h-p15\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.h-p1\.h},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.h-p1\.h},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.h-p1\.h},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.h-p1\.h},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p4\.h-p5\.h},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.s-p1\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {P0\.s-P1\.s},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p14\.s-p15\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.s-p1\.s},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.s-p1\.s},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.s-p1\.s},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.s-p1\.s},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p4\.s-p5\.s},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.d-p1\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {P0\.d-P1\.d},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p14\.d-p15\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.d-p1\.d},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.d-p1\.d},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.d-p1\.d},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.d-p1\.d},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p4\.d-p5\.d},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.b-p1\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {P0\.B-P1\.B},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p14\.b-p15\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.b-p1\.b},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.b-p1\.b},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.b-p1\.b},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.b-p1\.b},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p4\.b-p5\.b},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.h-p1\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {P0\.h-P1\.h},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p14\.h-p15\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.h-p1\.h},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.h-p1\.h},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.h-p1\.h},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.h-p1\.h},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p4\.h-p5\.h},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.s-p1\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {P0\.s-P1\.s},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p14\.s-p15\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.s-p1\.s},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.s-p1\.s},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.s-p1\.s},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.s-p1\.s},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p4\.s-p5\.s},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.d-p1\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {P0\.d-P1\.d},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p14\.d-p15\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.d-p1\.d},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.d-p1\.d},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.d-p1\.d},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.d-p1\.d},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p4\.d-p5\.d},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.b-p1\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {P0\.B-P1\.B},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p14\.b-p15\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.b-p1\.b},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.b-p1\.b},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.b-p1\.b},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.b-p1\.b},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p4\.b-p5\.b},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.h-p1\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {P0\.h-P1\.h},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p14\.h-p15\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.h-p1\.h},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.h-p1\.h},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.h-p1\.h},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.h-p1\.h},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p4\.h-p5\.h},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.s-p1\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {P0\.s-P1\.s},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p14\.s-p15\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.s-p1\.s},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.s-p1\.s},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.s-p1\.s},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.s-p1\.s},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p4\.s-p5\.s},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.d-p1\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {P0\.d-P1\.d},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p14\.d-p15\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.d-p1\.d},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.d-p1\.d},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.d-p1\.d},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.d-p1\.d},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p4\.d-p5\.d},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.b-p1\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {P0\.B-P1\.B},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p14\.b-p15\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.b-p1\.b},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.b-p1\.b},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.b-p1\.b},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.b-p1\.b},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p4\.b-p5\.b},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.h-p1\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {P0\.h-P1\.h},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p14\.h-p15\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.h-p1\.h},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.h-p1\.h},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.h-p1\.h},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.h-p1\.h},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p4\.h-p5\.h},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.s-p1\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {P0\.s-P1\.s},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p14\.s-p15\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.s-p1\.s},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.s-p1\.s},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.s-p1\.s},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.s-p1\.s},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p4\.s-p5\.s},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.d-p1\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {P0\.d-P1\.d},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p14\.d-p15\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.d-p1\.d},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.d-p1\.d},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.d-p1\.d},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.d-p1\.d},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p4\.d-p5\.d},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.b-p1\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {P0\.B-P1\.B},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p14\.b-p15\.b},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.b-p1\.b},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.b-p1\.b},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.b-p1\.b},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.b-p1\.b},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p4\.b-p5\.b},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.h-p1\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {P0\.h-P1\.h},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p14\.h-p15\.h},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.h-p1\.h},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.h-p1\.h},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.h-p1\.h},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.h-p1\.h},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p4\.h-p5\.h},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.s-p1\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {P0\.s-P1\.s},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p14\.s-p15\.s},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.s-p1\.s},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.s-p1\.s},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.s-p1\.s},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.s-p1\.s},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p4\.s-p5\.s},x17,x19'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.d-p1\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {P0\.d-P1\.d},X0,X0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p14\.d-p15\.d},x0,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.d-p1\.d},x30,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.d-p1\.d},xzr,x0'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.d-p1\.d},x0,x30'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.d-p1\.d},x0,xzr'
+[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p4\.d-p5\.d},x17,x19'
--- /dev/null
+#as: -march=armv8-a+sme2
+#objdump: -dr
+
+[^:]+: file format .*
+
+
+[^:]+:
+
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+[^:]+: 25e05ff0 whilelo {p0\.d-p1\.d}, xzr, x0
+[^:]+: 25fe5c10 whilelo {p0\.d-p1\.d}, x0, x30
+[^:]+: 25ff5c10 whilelo {p0\.d-p1\.d}, x0, xzr
+[^:]+: 25f35e34 whilelo {p4\.d-p5\.d}, x17, x19
+[^:]+: 25205c11 whilels {p0\.b-p1\.b}, x0, x0
+[^:]+: 25205c11 whilels {p0\.b-p1\.b}, x0, x0
+[^:]+: 25205c1f whilels {p14\.b-p15\.b}, x0, x0
+[^:]+: 25205fd1 whilels {p0\.b-p1\.b}, x30, x0
+[^:]+: 25205ff1 whilels {p0\.b-p1\.b}, xzr, x0
+[^:]+: 253e5c11 whilels {p0\.b-p1\.b}, x0, x30
+[^:]+: 253f5c11 whilels {p0\.b-p1\.b}, x0, xzr
+[^:]+: 25335e35 whilels {p4\.b-p5\.b}, x17, x19
+[^:]+: 25605c11 whilels {p0\.h-p1\.h}, x0, x0
+[^:]+: 25605c11 whilels {p0\.h-p1\.h}, x0, x0
+[^:]+: 25605c1f whilels {p14\.h-p15\.h}, x0, x0
+[^:]+: 25605fd1 whilels {p0\.h-p1\.h}, x30, x0
+[^:]+: 25605ff1 whilels {p0\.h-p1\.h}, xzr, x0
+[^:]+: 257e5c11 whilels {p0\.h-p1\.h}, x0, x30
+[^:]+: 257f5c11 whilels {p0\.h-p1\.h}, x0, xzr
+[^:]+: 25735e35 whilels {p4\.h-p5\.h}, x17, x19
+[^:]+: 25a05c11 whilels {p0\.s-p1\.s}, x0, x0
+[^:]+: 25a05c11 whilels {p0\.s-p1\.s}, x0, x0
+[^:]+: 25a05c1f whilels {p14\.s-p15\.s}, x0, x0
+[^:]+: 25a05fd1 whilels {p0\.s-p1\.s}, x30, x0
+[^:]+: 25a05ff1 whilels {p0\.s-p1\.s}, xzr, x0
+[^:]+: 25be5c11 whilels {p0\.s-p1\.s}, x0, x30
+[^:]+: 25bf5c11 whilels {p0\.s-p1\.s}, x0, xzr
+[^:]+: 25b35e35 whilels {p4\.s-p5\.s}, x17, x19
+[^:]+: 25e05c11 whilels {p0\.d-p1\.d}, x0, x0
+[^:]+: 25e05c11 whilels {p0\.d-p1\.d}, x0, x0
+[^:]+: 25e05c1f whilels {p14\.d-p15\.d}, x0, x0
+[^:]+: 25e05fd1 whilels {p0\.d-p1\.d}, x30, x0
+[^:]+: 25e05ff1 whilels {p0\.d-p1\.d}, xzr, x0
+[^:]+: 25fe5c11 whilels {p0\.d-p1\.d}, x0, x30
+[^:]+: 25ff5c11 whilels {p0\.d-p1\.d}, x0, xzr
+[^:]+: 25f35e35 whilels {p4\.d-p5\.d}, x17, x19
+[^:]+: 25205410 whilelt {p0\.b-p1\.b}, x0, x0
+[^:]+: 25205410 whilelt {p0\.b-p1\.b}, x0, x0
+[^:]+: 2520541e whilelt {p14\.b-p15\.b}, x0, x0
+[^:]+: 252057d0 whilelt {p0\.b-p1\.b}, x30, x0
+[^:]+: 252057f0 whilelt {p0\.b-p1\.b}, xzr, x0
+[^:]+: 253e5410 whilelt {p0\.b-p1\.b}, x0, x30
+[^:]+: 253f5410 whilelt {p0\.b-p1\.b}, x0, xzr
+[^:]+: 25335634 whilelt {p4\.b-p5\.b}, x17, x19
+[^:]+: 25605410 whilelt {p0\.h-p1\.h}, x0, x0
+[^:]+: 25605410 whilelt {p0\.h-p1\.h}, x0, x0
+[^:]+: 2560541e whilelt {p14\.h-p15\.h}, x0, x0
+[^:]+: 256057d0 whilelt {p0\.h-p1\.h}, x30, x0
+[^:]+: 256057f0 whilelt {p0\.h-p1\.h}, xzr, x0
+[^:]+: 257e5410 whilelt {p0\.h-p1\.h}, x0, x30
+[^:]+: 257f5410 whilelt {p0\.h-p1\.h}, x0, xzr
+[^:]+: 25735634 whilelt {p4\.h-p5\.h}, x17, x19
+[^:]+: 25a05410 whilelt {p0\.s-p1\.s}, x0, x0
+[^:]+: 25a05410 whilelt {p0\.s-p1\.s}, x0, x0
+[^:]+: 25a0541e whilelt {p14\.s-p15\.s}, x0, x0
+[^:]+: 25a057d0 whilelt {p0\.s-p1\.s}, x30, x0
+[^:]+: 25a057f0 whilelt {p0\.s-p1\.s}, xzr, x0
+[^:]+: 25be5410 whilelt {p0\.s-p1\.s}, x0, x30
+[^:]+: 25bf5410 whilelt {p0\.s-p1\.s}, x0, xzr
+[^:]+: 25b35634 whilelt {p4\.s-p5\.s}, x17, x19
+[^:]+: 25e05410 whilelt {p0\.d-p1\.d}, x0, x0
+[^:]+: 25e05410 whilelt {p0\.d-p1\.d}, x0, x0
+[^:]+: 25e0541e whilelt {p14\.d-p15\.d}, x0, x0
+[^:]+: 25e057d0 whilelt {p0\.d-p1\.d}, x30, x0
+[^:]+: 25e057f0 whilelt {p0\.d-p1\.d}, xzr, x0
+[^:]+: 25fe5410 whilelt {p0\.d-p1\.d}, x0, x30
+[^:]+: 25ff5410 whilelt {p0\.d-p1\.d}, x0, xzr
+[^:]+: 25f35634 whilelt {p4\.d-p5\.d}, x17, x19
--- /dev/null
+ whilege { p0.b - p1.b }, x0, x0
+ WHILEGE { P0.B - P1.B }, X0, X0
+ whilege { p14.b - p15.b }, x0, x0
+ whilege { p0.b - p1.b }, x30, x0
+ whilege { p0.b - p1.b }, xzr, x0
+ whilege { p0.b - p1.b }, x0, x30
+ whilege { p0.b - p1.b }, x0, xzr
+ whilege { p4.b - p5.b }, x17, x19
+
+ whilege { p0.h - p1.h }, x0, x0
+ WHILEGE { P0.h - P1.h }, X0, X0
+ whilege { p14.h - p15.h }, x0, x0
+ whilege { p0.h - p1.h }, x30, x0
+ whilege { p0.h - p1.h }, xzr, x0
+ whilege { p0.h - p1.h }, x0, x30
+ whilege { p0.h - p1.h }, x0, xzr
+ whilege { p4.h - p5.h }, x17, x19
+
+ whilege { p0.s - p1.s }, x0, x0
+ WHILEGE { P0.s - P1.s }, X0, X0
+ whilege { p14.s - p15.s }, x0, x0
+ whilege { p0.s - p1.s }, x30, x0
+ whilege { p0.s - p1.s }, xzr, x0
+ whilege { p0.s - p1.s }, x0, x30
+ whilege { p0.s - p1.s }, x0, xzr
+ whilege { p4.s - p5.s }, x17, x19
+
+ whilege { p0.d - p1.d }, x0, x0
+ WHILEGE { P0.d - P1.d }, X0, X0
+ whilege { p14.d - p15.d }, x0, x0
+ whilege { p0.d - p1.d }, x30, x0
+ whilege { p0.d - p1.d }, xzr, x0
+ whilege { p0.d - p1.d }, x0, x30
+ whilege { p0.d - p1.d }, x0, xzr
+ whilege { p4.d - p5.d }, x17, x19
+
+ whilegt { p0.b - p1.b }, x0, x0
+ WHILEGT { P0.B - P1.B }, X0, X0
+ whilegt { p14.b - p15.b }, x0, x0
+ whilegt { p0.b - p1.b }, x30, x0
+ whilegt { p0.b - p1.b }, xzr, x0
+ whilegt { p0.b - p1.b }, x0, x30
+ whilegt { p0.b - p1.b }, x0, xzr
+ whilegt { p4.b - p5.b }, x17, x19
+
+ whilegt { p0.h - p1.h }, x0, x0
+ WHILEGT { P0.h - P1.h }, X0, X0
+ whilegt { p14.h - p15.h }, x0, x0
+ whilegt { p0.h - p1.h }, x30, x0
+ whilegt { p0.h - p1.h }, xzr, x0
+ whilegt { p0.h - p1.h }, x0, x30
+ whilegt { p0.h - p1.h }, x0, xzr
+ whilegt { p4.h - p5.h }, x17, x19
+
+ whilegt { p0.s - p1.s }, x0, x0
+ WHILEGT { P0.s - P1.s }, X0, X0
+ whilegt { p14.s - p15.s }, x0, x0
+ whilegt { p0.s - p1.s }, x30, x0
+ whilegt { p0.s - p1.s }, xzr, x0
+ whilegt { p0.s - p1.s }, x0, x30
+ whilegt { p0.s - p1.s }, x0, xzr
+ whilegt { p4.s - p5.s }, x17, x19
+
+ whilegt { p0.d - p1.d }, x0, x0
+ WHILEGT { P0.d - P1.d }, X0, X0
+ whilegt { p14.d - p15.d }, x0, x0
+ whilegt { p0.d - p1.d }, x30, x0
+ whilegt { p0.d - p1.d }, xzr, x0
+ whilegt { p0.d - p1.d }, x0, x30
+ whilegt { p0.d - p1.d }, x0, xzr
+ whilegt { p4.d - p5.d }, x17, x19
+
+ whilehi { p0.b - p1.b }, x0, x0
+ WHILEHI { P0.B - P1.B }, X0, X0
+ whilehi { p14.b - p15.b }, x0, x0
+ whilehi { p0.b - p1.b }, x30, x0
+ whilehi { p0.b - p1.b }, xzr, x0
+ whilehi { p0.b - p1.b }, x0, x30
+ whilehi { p0.b - p1.b }, x0, xzr
+ whilehi { p4.b - p5.b }, x17, x19
+
+ whilehi { p0.h - p1.h }, x0, x0
+ WHILEHI { P0.h - P1.h }, X0, X0
+ whilehi { p14.h - p15.h }, x0, x0
+ whilehi { p0.h - p1.h }, x30, x0
+ whilehi { p0.h - p1.h }, xzr, x0
+ whilehi { p0.h - p1.h }, x0, x30
+ whilehi { p0.h - p1.h }, x0, xzr
+ whilehi { p4.h - p5.h }, x17, x19
+
+ whilehi { p0.s - p1.s }, x0, x0
+ WHILEHI { P0.s - P1.s }, X0, X0
+ whilehi { p14.s - p15.s }, x0, x0
+ whilehi { p0.s - p1.s }, x30, x0
+ whilehi { p0.s - p1.s }, xzr, x0
+ whilehi { p0.s - p1.s }, x0, x30
+ whilehi { p0.s - p1.s }, x0, xzr
+ whilehi { p4.s - p5.s }, x17, x19
+
+ whilehi { p0.d - p1.d }, x0, x0
+ WHILEHI { P0.d - P1.d }, X0, X0
+ whilehi { p14.d - p15.d }, x0, x0
+ whilehi { p0.d - p1.d }, x30, x0
+ whilehi { p0.d - p1.d }, xzr, x0
+ whilehi { p0.d - p1.d }, x0, x30
+ whilehi { p0.d - p1.d }, x0, xzr
+ whilehi { p4.d - p5.d }, x17, x19
+
+ whilehs { p0.b - p1.b }, x0, x0
+ WHILEHS { P0.B - P1.B }, X0, X0
+ whilehs { p14.b - p15.b }, x0, x0
+ whilehs { p0.b - p1.b }, x30, x0
+ whilehs { p0.b - p1.b }, xzr, x0
+ whilehs { p0.b - p1.b }, x0, x30
+ whilehs { p0.b - p1.b }, x0, xzr
+ whilehs { p4.b - p5.b }, x17, x19
+
+ whilehs { p0.h - p1.h }, x0, x0
+ WHILEHS { P0.h - P1.h }, X0, X0
+ whilehs { p14.h - p15.h }, x0, x0
+ whilehs { p0.h - p1.h }, x30, x0
+ whilehs { p0.h - p1.h }, xzr, x0
+ whilehs { p0.h - p1.h }, x0, x30
+ whilehs { p0.h - p1.h }, x0, xzr
+ whilehs { p4.h - p5.h }, x17, x19
+
+ whilehs { p0.s - p1.s }, x0, x0
+ WHILEHS { P0.s - P1.s }, X0, X0
+ whilehs { p14.s - p15.s }, x0, x0
+ whilehs { p0.s - p1.s }, x30, x0
+ whilehs { p0.s - p1.s }, xzr, x0
+ whilehs { p0.s - p1.s }, x0, x30
+ whilehs { p0.s - p1.s }, x0, xzr
+ whilehs { p4.s - p5.s }, x17, x19
+
+ whilehs { p0.d - p1.d }, x0, x0
+ WHILEHS { P0.d - P1.d }, X0, X0
+ whilehs { p14.d - p15.d }, x0, x0
+ whilehs { p0.d - p1.d }, x30, x0
+ whilehs { p0.d - p1.d }, xzr, x0
+ whilehs { p0.d - p1.d }, x0, x30
+ whilehs { p0.d - p1.d }, x0, xzr
+ whilehs { p4.d - p5.d }, x17, x19
+
+ whilele { p0.b - p1.b }, x0, x0
+ WHILELE { P0.B - P1.B }, X0, X0
+ whilele { p14.b - p15.b }, x0, x0
+ whilele { p0.b - p1.b }, x30, x0
+ whilele { p0.b - p1.b }, xzr, x0
+ whilele { p0.b - p1.b }, x0, x30
+ whilele { p0.b - p1.b }, x0, xzr
+ whilele { p4.b - p5.b }, x17, x19
+
+ whilele { p0.h - p1.h }, x0, x0
+ WHILELE { P0.h - P1.h }, X0, X0
+ whilele { p14.h - p15.h }, x0, x0
+ whilele { p0.h - p1.h }, x30, x0
+ whilele { p0.h - p1.h }, xzr, x0
+ whilele { p0.h - p1.h }, x0, x30
+ whilele { p0.h - p1.h }, x0, xzr
+ whilele { p4.h - p5.h }, x17, x19
+
+ whilele { p0.s - p1.s }, x0, x0
+ WHILELE { P0.s - P1.s }, X0, X0
+ whilele { p14.s - p15.s }, x0, x0
+ whilele { p0.s - p1.s }, x30, x0
+ whilele { p0.s - p1.s }, xzr, x0
+ whilele { p0.s - p1.s }, x0, x30
+ whilele { p0.s - p1.s }, x0, xzr
+ whilele { p4.s - p5.s }, x17, x19
+
+ whilele { p0.d - p1.d }, x0, x0
+ WHILELE { P0.d - P1.d }, X0, X0
+ whilele { p14.d - p15.d }, x0, x0
+ whilele { p0.d - p1.d }, x30, x0
+ whilele { p0.d - p1.d }, xzr, x0
+ whilele { p0.d - p1.d }, x0, x30
+ whilele { p0.d - p1.d }, x0, xzr
+ whilele { p4.d - p5.d }, x17, x19
+
+ whilelo { p0.b - p1.b }, x0, x0
+ WHILELO { P0.B - P1.B }, X0, X0
+ whilelo { p14.b - p15.b }, x0, x0
+ whilelo { p0.b - p1.b }, x30, x0
+ whilelo { p0.b - p1.b }, xzr, x0
+ whilelo { p0.b - p1.b }, x0, x30
+ whilelo { p0.b - p1.b }, x0, xzr
+ whilelo { p4.b - p5.b }, x17, x19
+
+ whilelo { p0.h - p1.h }, x0, x0
+ WHILELO { P0.h - P1.h }, X0, X0
+ whilelo { p14.h - p15.h }, x0, x0
+ whilelo { p0.h - p1.h }, x30, x0
+ whilelo { p0.h - p1.h }, xzr, x0
+ whilelo { p0.h - p1.h }, x0, x30
+ whilelo { p0.h - p1.h }, x0, xzr
+ whilelo { p4.h - p5.h }, x17, x19
+
+ whilelo { p0.s - p1.s }, x0, x0
+ WHILELO { P0.s - P1.s }, X0, X0
+ whilelo { p14.s - p15.s }, x0, x0
+ whilelo { p0.s - p1.s }, x30, x0
+ whilelo { p0.s - p1.s }, xzr, x0
+ whilelo { p0.s - p1.s }, x0, x30
+ whilelo { p0.s - p1.s }, x0, xzr
+ whilelo { p4.s - p5.s }, x17, x19
+
+ whilelo { p0.d - p1.d }, x0, x0
+ WHILELO { P0.d - P1.d }, X0, X0
+ whilelo { p14.d - p15.d }, x0, x0
+ whilelo { p0.d - p1.d }, x30, x0
+ whilelo { p0.d - p1.d }, xzr, x0
+ whilelo { p0.d - p1.d }, x0, x30
+ whilelo { p0.d - p1.d }, x0, xzr
+ whilelo { p4.d - p5.d }, x17, x19
+
+ whilels { p0.b - p1.b }, x0, x0
+ WHILELS { P0.B - P1.B }, X0, X0
+ whilels { p14.b - p15.b }, x0, x0
+ whilels { p0.b - p1.b }, x30, x0
+ whilels { p0.b - p1.b }, xzr, x0
+ whilels { p0.b - p1.b }, x0, x30
+ whilels { p0.b - p1.b }, x0, xzr
+ whilels { p4.b - p5.b }, x17, x19
+
+ whilels { p0.h - p1.h }, x0, x0
+ WHILELS { P0.h - P1.h }, X0, X0
+ whilels { p14.h - p15.h }, x0, x0
+ whilels { p0.h - p1.h }, x30, x0
+ whilels { p0.h - p1.h }, xzr, x0
+ whilels { p0.h - p1.h }, x0, x30
+ whilels { p0.h - p1.h }, x0, xzr
+ whilels { p4.h - p5.h }, x17, x19
+
+ whilels { p0.s - p1.s }, x0, x0
+ WHILELS { P0.s - P1.s }, X0, X0
+ whilels { p14.s - p15.s }, x0, x0
+ whilels { p0.s - p1.s }, x30, x0
+ whilels { p0.s - p1.s }, xzr, x0
+ whilels { p0.s - p1.s }, x0, x30
+ whilels { p0.s - p1.s }, x0, xzr
+ whilels { p4.s - p5.s }, x17, x19
+
+ whilels { p0.d - p1.d }, x0, x0
+ WHILELS { P0.d - P1.d }, X0, X0
+ whilels { p14.d - p15.d }, x0, x0
+ whilels { p0.d - p1.d }, x30, x0
+ whilels { p0.d - p1.d }, xzr, x0
+ whilels { p0.d - p1.d }, x0, x30
+ whilels { p0.d - p1.d }, x0, xzr
+ whilels { p4.d - p5.d }, x17, x19
+
+ whilelt { p0.b - p1.b }, x0, x0
+ WHILELT { P0.B - P1.B }, X0, X0
+ whilelt { p14.b - p15.b }, x0, x0
+ whilelt { p0.b - p1.b }, x30, x0
+ whilelt { p0.b - p1.b }, xzr, x0
+ whilelt { p0.b - p1.b }, x0, x30
+ whilelt { p0.b - p1.b }, x0, xzr
+ whilelt { p4.b - p5.b }, x17, x19
+
+ whilelt { p0.h - p1.h }, x0, x0
+ WHILELT { P0.h - P1.h }, X0, X0
+ whilelt { p14.h - p15.h }, x0, x0
+ whilelt { p0.h - p1.h }, x30, x0
+ whilelt { p0.h - p1.h }, xzr, x0
+ whilelt { p0.h - p1.h }, x0, x30
+ whilelt { p0.h - p1.h }, x0, xzr
+ whilelt { p4.h - p5.h }, x17, x19
+
+ whilelt { p0.s - p1.s }, x0, x0
+ WHILELT { P0.s - P1.s }, X0, X0
+ whilelt { p14.s - p15.s }, x0, x0
+ whilelt { p0.s - p1.s }, x30, x0
+ whilelt { p0.s - p1.s }, xzr, x0
+ whilelt { p0.s - p1.s }, x0, x30
+ whilelt { p0.s - p1.s }, x0, xzr
+ whilelt { p4.s - p5.s }, x17, x19
+
+ whilelt { p0.d - p1.d }, x0, x0
+ WHILELT { P0.d - P1.d }, X0, X0
+ whilelt { p14.d - p15.d }, x0, x0
+ whilelt { p0.d - p1.d }, x30, x0
+ whilelt { p0.d - p1.d }, xzr, x0
+ whilelt { p0.d - p1.d }, x0, x30
+ whilelt { p0.d - p1.d }, x0, xzr
+ whilelt { p4.d - p5.d }, x17, x19
AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */
AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */
+ AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */
+ AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */
AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */
AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */
AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */
AARCH64_OPND_SME_ZA_HV_idx_srcxN, /* SME N source ZA tile vectors. */
AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */
AARCH64_OPND_SME_ZA_HV_idx_destxN, /* SME N dest ZA tile vectors. */
+ AARCH64_OPND_SME_Pdx2, /* Predicate register list in [3:1]. */
+ AARCH64_OPND_SME_PdxN, /* Predicate register list in [3:0]. */
AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */
+ AARCH64_OPND_SME_PNd3, /* Predicate-as-counter register, bits [3:0]. */
AARCH64_OPND_SME_PNg3, /* Predicate-as-counter register, bits [12:10]. */
+ AARCH64_OPND_SME_PNn, /* Predicate-as-counter register, bits [8:5]. */
+ AARCH64_OPND_SME_PNn3_INDEX1, /* Indexed pred-as-counter reg, bits [8:5]. */
+ AARCH64_OPND_SME_PNn3_INDEX2, /* Indexed pred-as-counter reg, bits [9:5]. */
AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */
AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */
AARCH64_OPND_SME_ZA_array_off3_0, /* SME ZA[<Wv>{, #<imm3>}]. */
AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */
+ AARCH64_OPND_SME_VLxN_10, /* VLx2 or VLx4, in bit 10. */
+ AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */
extern const char *const aarch64_sve_pattern_array[32];
extern const char *const aarch64_sve_prfop_array[16];
+extern const char *const aarch64_sme_vlxn_array[2];
#ifdef __cplusplus
}
case 203:
case 209:
case 212:
- case 220:
- case 221:
- case 226:
- case 227:
+ case 222:
+ case 223:
+ case 230:
+ case 231:
+ case 232:
+ case 233:
return aarch64_ins_regno (self, info, code, inst, errors);
case 15:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
case 33:
case 34:
case 35:
- case 237:
+ case 247:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ins_reglist (self, info, code, inst, errors);
case 192:
case 193:
case 194:
- case 228:
case 236:
- case 241:
- case 242:
+ case 244:
+ case 245:
+ case 246:
+ case 251:
+ case 252:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 211:
case 213:
+ case 229:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 214:
case 215:
case 216:
case 217:
- return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 218:
case 219:
+ case 228:
+ return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
+ case 220:
+ case 221:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
- case 222:
case 224:
- case 229:
+ case 226:
+ case 237:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
- case 223:
case 225:
+ case 227:
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
- case 230:
- case 231:
- case 232:
- return aarch64_ins_sme_za_array (self, info, code, inst, errors);
- case 233:
- return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 234:
- return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 235:
- return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ins_simple_index (self, info, code, inst, errors);
case 238:
case 239:
case 240:
+ return aarch64_ins_sme_za_array (self, info, code, inst, errors);
+ case 241:
+ return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ case 242:
+ return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
+ case 243:
+ return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 248:
+ case 249:
+ case 250:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}
va_end (va);
}
-/* Insert a raw field value VALUE into all fields in SELF->fields.
+/* Insert a raw field value VALUE into all fields in SELF->fields after START.
The least significant bit goes in the final field. */
static void
-insert_all_fields (const aarch64_operand *self, aarch64_insn *code,
- aarch64_insn value)
+insert_all_fields_after (const aarch64_operand *self, unsigned int start,
+ aarch64_insn *code, aarch64_insn value)
{
unsigned int i;
enum aarch64_field_kind kind;
- for (i = ARRAY_SIZE (self->fields); i-- > 0; )
+ for (i = ARRAY_SIZE (self->fields); i-- > start; )
if (self->fields[i] != FLD_NIL)
{
kind = self->fields[i];
}
}
+/* Insert a raw field value VALUE into all fields in SELF->fields.
+ The least significant bit goes in the final field. */
+
+static void
+insert_all_fields (const aarch64_operand *self, aarch64_insn *code,
+ aarch64_insn value)
+{
+ return insert_all_fields_after (self, 0, code, value);
+}
+
/* Operand inserters. */
/* Insert nothing. */
return true;
}
+/* Insert an indexed register, with the first field being the register
+ number and the remaining fields being the index. */
+bool
+aarch64_ins_simple_index (const aarch64_operand *self,
+ const aarch64_opnd_info *info,
+ aarch64_insn *code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ int bias = get_operand_specific_data (self);
+ insert_field (self->fields[0], code, info->reglane.regno - bias, 0);
+ insert_all_fields_after (self, 1, code, info->reglane.index);
+ return true;
+}
+
/* Miscellaneous encoding functions. */
/* Encode size[0], i.e. bit 22, for
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1);
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2);
AARCH64_DECL_OPD_INSERTER (ins_x0_to_x30);
+AARCH64_DECL_OPD_INSERTER (ins_simple_index);
#undef AARCH64_DECL_OPD_INSERTER
10987654321098765432109876543210
x1000000xx0xx10xxxxx00xxxxxxxxxx
mov. */
- return 2490;
+ return 2499;
}
else
{
10987654321098765432109876543210
x1000000xx0xx10xxxxx10xxxxxxxxxx
mov. */
- return 2488;
+ return 2497;
}
}
else
10987654321098765432109876543210
x1000000xx0xx10xxxxx01xxxxxxxxxx
mov. */
- return 2491;
+ return 2500;
}
else
{
10987654321098765432109876543210
x1000000xx0xx10xxxxx11xxxxxxxxxx
mov. */
- return 2489;
+ return 2498;
}
}
}
10987654321098765432109876543210
x1000000xx0xx11xxxxx00xxxxxxxxxx
mov. */
- return 2486;
+ return 2495;
}
else
{
10987654321098765432109876543210
x1000000xx0xx11xxxxx10xxxxxxxxxx
mov. */
- return 2484;
+ return 2493;
}
}
else
10987654321098765432109876543210
x1000000xx0xx11xxxxx01xxxxxxxxxx
mov. */
- return 2487;
+ return 2496;
}
else
{
10987654321098765432109876543210
x1000000xx0xx11xxxxx11xxxxxxxxxx
mov. */
- return 2485;
+ return 2494;
}
}
}
10987654321098765432109876543210
x0100000000xxxxx000xxxxxxxxxxxx0
ld1b. */
- return 2424;
+ return 2433;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx100xxxxxxxxxxxx0
ld1b. */
- return 2425;
+ return 2434;
}
}
else
10987654321098765432109876543210
x0100000000xxxxx010xxxxxxxxxxxx0
ld1w. */
- return 2448;
+ return 2457;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx110xxxxxxxxxxxx0
ld1w. */
- return 2449;
+ return 2458;
}
}
}
10987654321098765432109876543210
x0100000000xxxxx001xxxxxxxxxxxx0
ld1h. */
- return 2440;
+ return 2449;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx101xxxxxxxxxxxx0
ld1h. */
- return 2441;
+ return 2450;
}
}
else
10987654321098765432109876543210
x0100000000xxxxx011xxxxxxxxxxxx0
ld1d. */
- return 2432;
+ return 2441;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx111xxxxxxxxxxxx0
ld1d. */
- return 2433;
+ return 2442;
}
}
}
10987654321098765432109876543210
x0100000000xxxxx000xxxxxxxxxxxx1
ldnt1b. */
- return 2456;
+ return 2465;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx100xxxxxxxxxxxx1
ldnt1b. */
- return 2457;
+ return 2466;
}
}
else
10987654321098765432109876543210
x0100000000xxxxx010xxxxxxxxxxxx1
ldnt1w. */
- return 2480;
+ return 2489;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx110xxxxxxxxxxxx1
ldnt1w. */
- return 2481;
+ return 2490;
}
}
}
10987654321098765432109876543210
x0100000000xxxxx001xxxxxxxxxxxx1
ldnt1h. */
- return 2472;
+ return 2481;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx101xxxxxxxxxxxx1
ldnt1h. */
- return 2473;
+ return 2482;
}
}
else
10987654321098765432109876543210
x0100000000xxxxx011xxxxxxxxxxxx1
ldnt1d. */
- return 2464;
+ return 2473;
}
else
{
10987654321098765432109876543210
x0100000000xxxxx111xxxxxxxxxxxx1
ldnt1d. */
- return 2465;
+ return 2474;
}
}
}
10987654321098765432109876543210
x0100000010xxxxx000xxxxxxxxxxxx0
ld1b. */
- return 2420;
+ return 2429;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx100xxxxxxxxxxxx0
ld1b. */
- return 2421;
+ return 2430;
}
}
else
10987654321098765432109876543210
x0100000010xxxxx010xxxxxxxxxxxx0
ld1w. */
- return 2444;
+ return 2453;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx110xxxxxxxxxxxx0
ld1w. */
- return 2445;
+ return 2454;
}
}
}
10987654321098765432109876543210
x0100000010xxxxx001xxxxxxxxxxxx0
ld1h. */
- return 2436;
+ return 2445;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx101xxxxxxxxxxxx0
ld1h. */
- return 2437;
+ return 2446;
}
}
else
10987654321098765432109876543210
x0100000010xxxxx011xxxxxxxxxxxx0
ld1d. */
- return 2428;
+ return 2437;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx111xxxxxxxxxxxx0
ld1d. */
- return 2429;
+ return 2438;
}
}
}
10987654321098765432109876543210
x0100000010xxxxx000xxxxxxxxxxxx1
ldnt1b. */
- return 2452;
+ return 2461;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx100xxxxxxxxxxxx1
ldnt1b. */
- return 2453;
+ return 2462;
}
}
else
10987654321098765432109876543210
x0100000010xxxxx010xxxxxxxxxxxx1
ldnt1w. */
- return 2476;
+ return 2485;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx110xxxxxxxxxxxx1
ldnt1w. */
- return 2477;
+ return 2486;
}
}
}
10987654321098765432109876543210
x0100000010xxxxx001xxxxxxxxxxxx1
ldnt1h. */
- return 2468;
+ return 2477;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx101xxxxxxxxxxxx1
ldnt1h. */
- return 2469;
+ return 2478;
}
}
else
10987654321098765432109876543210
x0100000010xxxxx011xxxxxxxxxxxx1
ldnt1d. */
- return 2460;
+ return 2469;
}
else
{
10987654321098765432109876543210
x0100000010xxxxx111xxxxxxxxxxxx1
ldnt1d. */
- return 2461;
+ return 2470;
}
}
}
10987654321098765432109876543210
x0x00000001xxxxx000xxxxxxxxxxxx0
st1b. */
- return 2504;
+ return 2518;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx100xxxxxxxxxxxx0
st1b. */
- return 2505;
+ return 2519;
}
}
else
10987654321098765432109876543210
x0x00000001xxxxx010xxxxxxxxxxxx0
st1w. */
- return 2528;
+ return 2542;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx110xxxxxxxxxxxx0
st1w. */
- return 2529;
+ return 2543;
}
}
}
10987654321098765432109876543210
x0x00000001xxxxx001xxxxxxxxxxxx0
st1h. */
- return 2520;
+ return 2534;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx101xxxxxxxxxxxx0
st1h. */
- return 2521;
+ return 2535;
}
}
else
10987654321098765432109876543210
x0x00000001xxxxx011xxxxxxxxxxxx0
st1d. */
- return 2512;
+ return 2526;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx111xxxxxxxxxxxx0
st1d. */
- return 2513;
+ return 2527;
}
}
}
10987654321098765432109876543210
x0x00000001xxxxx000xxxxxxxxxxxx1
stnt1b. */
- return 2536;
+ return 2550;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx100xxxxxxxxxxxx1
stnt1b. */
- return 2537;
+ return 2551;
}
}
else
10987654321098765432109876543210
x0x00000001xxxxx010xxxxxxxxxxxx1
stnt1w. */
- return 2560;
+ return 2574;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx110xxxxxxxxxxxx1
stnt1w. */
- return 2561;
+ return 2575;
}
}
}
10987654321098765432109876543210
x0x00000001xxxxx001xxxxxxxxxxxx1
stnt1h. */
- return 2552;
+ return 2566;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx101xxxxxxxxxxxx1
stnt1h. */
- return 2553;
+ return 2567;
}
}
else
10987654321098765432109876543210
x0x00000001xxxxx011xxxxxxxxxxxx1
stnt1d. */
- return 2544;
+ return 2558;
}
else
{
10987654321098765432109876543210
x0x00000001xxxxx111xxxxxxxxxxxx1
stnt1d. */
- return 2545;
+ return 2559;
}
}
}
10987654321098765432109876543210
x0x00000011xxxxx000xxxxxxxxxxxx0
st1b. */
- return 2500;
+ return 2514;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx100xxxxxxxxxxxx0
st1b. */
- return 2501;
+ return 2515;
}
}
else
10987654321098765432109876543210
x0x00000011xxxxx010xxxxxxxxxxxx0
st1w. */
- return 2524;
+ return 2538;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx110xxxxxxxxxxxx0
st1w. */
- return 2525;
+ return 2539;
}
}
}
10987654321098765432109876543210
x0x00000011xxxxx001xxxxxxxxxxxx0
st1h. */
- return 2516;
+ return 2530;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx101xxxxxxxxxxxx0
st1h. */
- return 2517;
+ return 2531;
}
}
else
10987654321098765432109876543210
x0x00000011xxxxx011xxxxxxxxxxxx0
st1d. */
- return 2508;
+ return 2522;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx111xxxxxxxxxxxx0
st1d. */
- return 2509;
+ return 2523;
}
}
}
10987654321098765432109876543210
x0x00000011xxxxx000xxxxxxxxxxxx1
stnt1b. */
- return 2532;
+ return 2546;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx100xxxxxxxxxxxx1
stnt1b. */
- return 2533;
+ return 2547;
}
}
else
10987654321098765432109876543210
x0x00000011xxxxx010xxxxxxxxxxxx1
stnt1w. */
- return 2556;
+ return 2570;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx110xxxxxxxxxxxx1
stnt1w. */
- return 2557;
+ return 2571;
}
}
}
10987654321098765432109876543210
x0x00000011xxxxx001xxxxxxxxxxxx1
stnt1h. */
- return 2548;
+ return 2562;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx101xxxxxxxxxxxx1
stnt1h. */
- return 2549;
+ return 2563;
}
}
else
10987654321098765432109876543210
x0x00000011xxxxx011xxxxxxxxxxxx1
stnt1d. */
- return 2540;
+ return 2554;
}
else
{
10987654321098765432109876543210
x0x00000011xxxxx111xxxxxxxxxxxx1
stnt1d. */
- return 2541;
+ return 2555;
}
}
}
10987654321098765432109876543210
x0x00001000xxxxx000xxxxxxxxx0xxx
ld1b. */
- return 2426;
+ return 2435;
}
else
{
10987654321098765432109876543210
x0x00001000xxxxx010xxxxxxxxx0xxx
ld1w. */
- return 2450;
+ return 2459;
}
}
else
10987654321098765432109876543210
x0x00001000xxxxx001xxxxxxxxx0xxx
ld1h. */
- return 2442;
+ return 2451;
}
else
{
10987654321098765432109876543210
x0x00001000xxxxx011xxxxxxxxx0xxx
ld1d. */
- return 2434;
+ return 2443;
}
}
}
10987654321098765432109876543210
x0x00001000xxxxx000xxxxxxxxx1xxx
ldnt1b. */
- return 2458;
+ return 2467;
}
else
{
10987654321098765432109876543210
x0x00001000xxxxx010xxxxxxxxx1xxx
ldnt1w. */
- return 2482;
+ return 2491;
}
}
else
10987654321098765432109876543210
x0x00001000xxxxx001xxxxxxxxx1xxx
ldnt1h. */
- return 2474;
+ return 2483;
}
else
{
10987654321098765432109876543210
x0x00001000xxxxx011xxxxxxxxx1xxx
ldnt1d. */
- return 2466;
+ return 2475;
}
}
}
10987654321098765432109876543210
xxx00001000xxxxx100xxxxxxxxx0xxx
ld1b. */
- return 2427;
+ return 2436;
}
else
{
10987654321098765432109876543210
xxx00001000xxxxx110xxxxxxxxx0xxx
ld1w. */
- return 2451;
+ return 2460;
}
}
else
10987654321098765432109876543210
xxx00001000xxxxx101xxxxxxxxx0xxx
ld1h. */
- return 2443;
+ return 2452;
}
else
{
10987654321098765432109876543210
xxx00001000xxxxx111xxxxxxxxx0xxx
ld1d. */
- return 2435;
+ return 2444;
}
}
}
10987654321098765432109876543210
xxx00001000xxxxx100xxxxxxxxx1xxx
ldnt1b. */
- return 2459;
+ return 2468;
}
else
{
10987654321098765432109876543210
xxx00001000xxxxx110xxxxxxxxx1xxx
ldnt1w. */
- return 2483;
+ return 2492;
}
}
else
10987654321098765432109876543210
xxx00001000xxxxx101xxxxxxxxx1xxx
ldnt1h. */
- return 2475;
+ return 2484;
}
else
{
10987654321098765432109876543210
xxx00001000xxxxx111xxxxxxxxx1xxx
ldnt1d. */
- return 2467;
+ return 2476;
}
}
}
10987654321098765432109876543210
xxx00001010xxxxx000xxxxxxxxx0xxx
ld1b. */
- return 2422;
+ return 2431;
}
else
{
10987654321098765432109876543210
xxx00001010xxxxx100xxxxxxxxx0xxx
ld1b. */
- return 2423;
+ return 2432;
}
}
else
10987654321098765432109876543210
xxx00001010xxxxx010xxxxxxxxx0xxx
ld1w. */
- return 2446;
+ return 2455;
}
else
{
10987654321098765432109876543210
xxx00001010xxxxx110xxxxxxxxx0xxx
ld1w. */
- return 2447;
+ return 2456;
}
}
}
10987654321098765432109876543210
xxx00001010xxxxx001xxxxxxxxx0xxx
ld1h. */
- return 2438;
+ return 2447;
}
else
{
10987654321098765432109876543210
xxx00001010xxxxx101xxxxxxxxx0xxx
ld1h. */
- return 2439;
+ return 2448;
}
}
else
10987654321098765432109876543210
xxx00001010xxxxx011xxxxxxxxx0xxx
ld1d. */
- return 2430;
+ return 2439;
}
else
{
10987654321098765432109876543210
xxx00001010xxxxx111xxxxxxxxx0xxx
ld1d. */
- return 2431;
+ return 2440;
}
}
}
10987654321098765432109876543210
xxx00001010xxxxx000xxxxxxxxx1xxx
ldnt1b. */
- return 2454;
+ return 2463;
}
else
{
10987654321098765432109876543210
xxx00001010xxxxx100xxxxxxxxx1xxx
ldnt1b. */
- return 2455;
+ return 2464;
}
}
else
10987654321098765432109876543210
xxx00001010xxxxx010xxxxxxxxx1xxx
ldnt1w. */
- return 2478;
+ return 2487;
}
else
{
10987654321098765432109876543210
xxx00001010xxxxx110xxxxxxxxx1xxx
ldnt1w. */
- return 2479;
+ return 2488;
}
}
}
10987654321098765432109876543210
xxx00001010xxxxx001xxxxxxxxx1xxx
ldnt1h. */
- return 2470;
+ return 2479;
}
else
{
10987654321098765432109876543210
xxx00001010xxxxx101xxxxxxxxx1xxx
ldnt1h. */
- return 2471;
+ return 2480;
}
}
else
10987654321098765432109876543210
xxx00001010xxxxx011xxxxxxxxx1xxx
ldnt1d. */
- return 2462;
+ return 2471;
}
else
{
10987654321098765432109876543210
xxx00001010xxxxx111xxxxxxxxx1xxx
ldnt1d. */
- return 2463;
+ return 2472;
}
}
}
}
else
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 29) & 0x1) == 0)
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 30) & 0x1) == 0)
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 4) & 0x1) == 0)
{
- if (((word >> 30) & 0x1) == 0)
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001xx1xxxxxxxxxxxxxxxx0xxxx
+ fmopa. */
+ return 2367;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0000001xx1xxxxxxxxxxxxxxxx1xxxx
+ fmops. */
+ return 2370;
+ }
+ }
+ else
+ {
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxx0xxxxxxxxxxxxxxxx
+ sel. */
+ return 2512;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxx1xxxxxxxxxxxxxxxx
+ sel. */
+ return 2513;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ if (((word >> 23) & 0x1) == 0)
+ {
+ if (((word >> 15) & 0x1) == 0)
+ {
+ if (((word >> 30) & 0x1) == 0)
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100001001xxxxx000xxxxxxxxx0xxx
+ st1b. */
+ return 2520;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100001001xxxxx010xxxxxxxxx0xxx
+ st1w. */
+ return 2544;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100001001xxxxx001xxxxxxxxx0xxx
+ st1h. */
+ return 2536;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100001001xxxxx011xxxxxxxxx0xxx
+ st1d. */
+ return 2528;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100001001xxxxx000xxxxxxxxx1xxx
+ stnt1b. */
+ return 2552;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100001001xxxxx010xxxxxxxxx1xxx
+ stnt1w. */
+ return 2576;
+ }
+ }
+ else
+ {
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100001001xxxxx001xxxxxxxxx1xxx
+ stnt1h. */
+ return 2568;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100001001xxxxx011xxxxxxxxx1xxx
+ stnt1d. */
+ return 2560;
+ }
+ }
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1100001001xxxxx0xxxxxxxxxxxxxxx
+ str. */
+ return 2414;
+ }
+ }
+ else
{
if (((word >> 3) & 0x1) == 0)
{
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x0x00001001xxxxx000xxxxxxxxx0xxx
+ xx100001001xxxxx100xxxxxxxxx0xxx
st1b. */
- return 2506;
+ return 2521;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x0x00001001xxxxx010xxxxxxxxx0xxx
+ xx100001001xxxxx110xxxxxxxxx0xxx
st1w. */
- return 2530;
+ return 2545;
}
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x0x00001001xxxxx001xxxxxxxxx0xxx
+ xx100001001xxxxx101xxxxxxxxx0xxx
st1h. */
- return 2522;
+ return 2537;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x0x00001001xxxxx011xxxxxxxxx0xxx
+ xx100001001xxxxx111xxxxxxxxx0xxx
st1d. */
- return 2514;
+ return 2529;
}
}
}
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x0x00001001xxxxx000xxxxxxxxx1xxx
+ xx100001001xxxxx100xxxxxxxxx1xxx
stnt1b. */
- return 2538;
+ return 2553;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x0x00001001xxxxx010xxxxxxxxx1xxx
+ xx100001001xxxxx110xxxxxxxxx1xxx
stnt1w. */
- return 2562;
+ return 2577;
}
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x0x00001001xxxxx001xxxxxxxxx1xxx
+ xx100001001xxxxx101xxxxxxxxx1xxx
stnt1h. */
- return 2554;
+ return 2569;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x0x00001001xxxxx011xxxxxxxxx1xxx
+ xx100001001xxxxx111xxxxxxxxx1xxx
stnt1d. */
- return 2546;
+ return 2561;
}
}
}
}
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1x00001001xxxxx0xxxxxxxxxxxxxxx
- str. */
- return 2414;
- }
}
else
{
- if (((word >> 3) & 0x1) == 0)
- {
- if (((word >> 13) & 0x1) == 0)
- {
- if (((word >> 14) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001001xxxxx100xxxxxxxxx0xxx
- st1b. */
- return 2507;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001001xxxxx110xxxxxxxxx0xxx
- st1w. */
- return 2531;
- }
- }
- else
- {
- if (((word >> 14) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001001xxxxx101xxxxxxxxx0xxx
- st1h. */
- return 2523;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001001xxxxx111xxxxxxxxx0xxx
- st1d. */
- return 2515;
- }
- }
- }
- else
- {
- if (((word >> 13) & 0x1) == 0)
- {
- if (((word >> 14) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001001xxxxx100xxxxxxxxx1xxx
- stnt1b. */
- return 2539;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001001xxxxx110xxxxxxxxx1xxx
- stnt1w. */
- return 2563;
- }
- }
- else
- {
- if (((word >> 14) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001001xxxxx101xxxxxxxxx1xxx
- stnt1h. */
- return 2555;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001001xxxxx111xxxxxxxxx1xxx
- stnt1d. */
- return 2547;
- }
- }
- }
- }
- }
- else
- {
- if (((word >> 4) & 0x1) == 0)
- {
- if (((word >> 29) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx000001101xxxxxxxxxxxxxxxx0xxxx
- fmopa. */
- return 2367;
- }
- else
+ if (((word >> 4) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
umopa. */
return 2380;
}
- }
- else
- {
- if (((word >> 29) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xx000001101xxxxxxxxxxxxxxxx1xxxx
- fmops. */
- return 2370;
- }
else
{
/* 33222222222211111111110000000000
}
}
}
- }
- else
- {
- if (((word >> 23) & 0x1) == 0)
+ else
{
- if (((word >> 3) & 0x1) == 0)
- {
- if (((word >> 13) & 0x1) == 0)
- {
- if (((word >> 14) & 0x1) == 0)
- {
- if (((word >> 15) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx000xxxxxxxxx0xxx
- st1b. */
- return 2502;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx100xxxxxxxxx0xxx
- st1b. */
- return 2503;
- }
- }
- else
- {
- if (((word >> 15) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx010xxxxxxxxx0xxx
- st1w. */
- return 2526;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx110xxxxxxxxx0xxx
- st1w. */
- return 2527;
- }
- }
- }
- else
- {
- if (((word >> 14) & 0x1) == 0)
- {
- if (((word >> 15) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx001xxxxxxxxx0xxx
- st1h. */
- return 2518;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx101xxxxxxxxx0xxx
- st1h. */
- return 2519;
- }
- }
- else
- {
- if (((word >> 15) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx011xxxxxxxxx0xxx
- st1d. */
- return 2510;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx111xxxxxxxxx0xxx
- st1d. */
- return 2511;
- }
- }
- }
- }
- else
+ if (((word >> 23) & 0x1) == 0)
{
- if (((word >> 13) & 0x1) == 0)
+ if (((word >> 3) & 0x1) == 0)
{
- if (((word >> 14) & 0x1) == 0)
+ if (((word >> 13) & 0x1) == 0)
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx000xxxxxxxxx1xxx
- stnt1b. */
- return 2534;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx000xxxxxxxxx0xxx
+ st1b. */
+ return 2516;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx100xxxxxxxxx0xxx
+ st1b. */
+ return 2517;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx100xxxxxxxxx1xxx
- stnt1b. */
- return 2535;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx010xxxxxxxxx0xxx
+ st1w. */
+ return 2540;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx110xxxxxxxxx0xxx
+ st1w. */
+ return 2541;
+ }
}
}
else
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx010xxxxxxxxx1xxx
- stnt1w. */
- return 2558;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx001xxxxxxxxx0xxx
+ st1h. */
+ return 2532;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx101xxxxxxxxx0xxx
+ st1h. */
+ return 2533;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx110xxxxxxxxx1xxx
- stnt1w. */
- return 2559;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx011xxxxxxxxx0xxx
+ st1d. */
+ return 2524;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx111xxxxxxxxx0xxx
+ st1d. */
+ return 2525;
+ }
}
}
}
else
{
- if (((word >> 14) & 0x1) == 0)
+ if (((word >> 13) & 0x1) == 0)
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx001xxxxxxxxx1xxx
- stnt1h. */
- return 2550;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx000xxxxxxxxx1xxx
+ stnt1b. */
+ return 2548;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx100xxxxxxxxx1xxx
+ stnt1b. */
+ return 2549;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx101xxxxxxxxx1xxx
- stnt1h. */
- return 2551;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx010xxxxxxxxx1xxx
+ stnt1w. */
+ return 2572;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx110xxxxxxxxx1xxx
+ stnt1w. */
+ return 2573;
+ }
}
}
else
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx011xxxxxxxxx1xxx
- stnt1d. */
- return 2542;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx001xxxxxxxxx1xxx
+ stnt1h. */
+ return 2564;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx101xxxxxxxxx1xxx
+ stnt1h. */
+ return 2565;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001011xxxxx111xxxxxxxxx1xxx
- stnt1d. */
- return 2543;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx011xxxxxxxxx1xxx
+ stnt1d. */
+ return 2556;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xx100001011xxxxx111xxxxxxxxx1xxx
+ stnt1d. */
+ return 2557;
+ }
}
}
}
}
- }
- else
- {
- if (((word >> 4) & 0x1) == 0)
+ else
{
- if (((word >> 30) & 0x1) == 0)
+ if (((word >> 4) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0x00001111xxxxxxxxxxxxxxxx0xxxx
- umopa. */
- return 2381;
+ if (((word >> 30) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x0100001111xxxxxxxxxxxxxxxx0xxxx
+ umopa. */
+ return 2381;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1100001111xxxxxxxxxxxxxxxx0xxxx
+ st1q. */
+ return 2407;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1x00001111xxxxxxxxxxxxxxxx0xxxx
- st1q. */
- return 2407;
+ xx100001111xxxxxxxxxxxxxxxx1xxxx
+ umops. */
+ return 2383;
}
}
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxx00001111xxxxxxxxxxxxxxxx1xxxx
- umops. */
- return 2383;
- }
}
}
}
10987654321098765432109876543210
00011001000xxxxxxxxx00xxxxxxxxxx
stlurb. */
- return 2604;
+ return 2626;
}
else
{
10987654321098765432109876543210
10011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2612;
+ return 2634;
}
}
else
10987654321098765432109876543210
01011001000xxxxxxxxx00xxxxxxxxxx
stlurh. */
- return 2608;
+ return 2630;
}
else
{
10987654321098765432109876543210
11011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2615;
+ return 2637;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0000x1xxxxxxxxxx
cpyfp. */
- return 2664;
+ return 2686;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1000x1xxxxxxxxxx
cpyfprn. */
- return 2670;
+ return 2692;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0100x1xxxxxxxxxx
cpyfpwn. */
- return 2667;
+ return 2689;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1100x1xxxxxxxxxx
cpyfpn. */
- return 2673;
+ return 2695;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0010x1xxxxxxxxxx
cpyfprt. */
- return 2688;
+ return 2710;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1010x1xxxxxxxxxx
cpyfprtrn. */
- return 2694;
+ return 2716;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0110x1xxxxxxxxxx
cpyfprtwn. */
- return 2691;
+ return 2713;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1110x1xxxxxxxxxx
cpyfprtn. */
- return 2697;
+ return 2719;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0001x1xxxxxxxxxx
cpyfpwt. */
- return 2676;
+ return 2698;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1001x1xxxxxxxxxx
cpyfpwtrn. */
- return 2682;
+ return 2704;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0101x1xxxxxxxxxx
cpyfpwtwn. */
- return 2679;
+ return 2701;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1101x1xxxxxxxxxx
cpyfpwtn. */
- return 2685;
+ return 2707;
}
}
}
10987654321098765432109876543210
xx011001000xxxxx0011x1xxxxxxxxxx
cpyfpt. */
- return 2700;
+ return 2722;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1011x1xxxxxxxxxx
cpyfptrn. */
- return 2706;
+ return 2728;
}
}
else
10987654321098765432109876543210
xx011001000xxxxx0111x1xxxxxxxxxx
cpyfptwn. */
- return 2703;
+ return 2725;
}
else
{
10987654321098765432109876543210
xx011001000xxxxx1111x1xxxxxxxxxx
cpyfptn. */
- return 2709;
+ return 2731;
}
}
}
10987654321098765432109876543210
00011001010xxxxxxxxx00xxxxxxxxxx
ldapurb. */
- return 2605;
+ return 2627;
}
else
{
10987654321098765432109876543210
10011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2613;
+ return 2635;
}
}
else
10987654321098765432109876543210
01011001010xxxxxxxxx00xxxxxxxxxx
ldapurh. */
- return 2609;
+ return 2631;
}
else
{
10987654321098765432109876543210
11011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2616;
+ return 2638;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0000x1xxxxxxxxxx
cpyfm. */
- return 2665;
+ return 2687;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1000x1xxxxxxxxxx
cpyfmrn. */
- return 2671;
+ return 2693;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0100x1xxxxxxxxxx
cpyfmwn. */
- return 2668;
+ return 2690;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1100x1xxxxxxxxxx
cpyfmn. */
- return 2674;
+ return 2696;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0010x1xxxxxxxxxx
cpyfmrt. */
- return 2689;
+ return 2711;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1010x1xxxxxxxxxx
cpyfmrtrn. */
- return 2695;
+ return 2717;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0110x1xxxxxxxxxx
cpyfmrtwn. */
- return 2692;
+ return 2714;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1110x1xxxxxxxxxx
cpyfmrtn. */
- return 2698;
+ return 2720;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0001x1xxxxxxxxxx
cpyfmwt. */
- return 2677;
+ return 2699;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1001x1xxxxxxxxxx
cpyfmwtrn. */
- return 2683;
+ return 2705;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0101x1xxxxxxxxxx
cpyfmwtwn. */
- return 2680;
+ return 2702;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1101x1xxxxxxxxxx
cpyfmwtn. */
- return 2686;
+ return 2708;
}
}
}
10987654321098765432109876543210
xx011001010xxxxx0011x1xxxxxxxxxx
cpyfmt. */
- return 2701;
+ return 2723;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1011x1xxxxxxxxxx
cpyfmtrn. */
- return 2707;
+ return 2729;
}
}
else
10987654321098765432109876543210
xx011001010xxxxx0111x1xxxxxxxxxx
cpyfmtwn. */
- return 2704;
+ return 2726;
}
else
{
10987654321098765432109876543210
xx011001010xxxxx1111x1xxxxxxxxxx
cpyfmtn. */
- return 2710;
+ return 2732;
}
}
}
10987654321098765432109876543210
00011001100xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2607;
+ return 2629;
}
else
{
10987654321098765432109876543210
10011001100xxxxxxxxx00xxxxxxxxxx
ldapursw. */
- return 2614;
+ return 2636;
}
}
else
10987654321098765432109876543210
x1011001100xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2611;
+ return 2633;
}
}
else
10987654321098765432109876543210
x0011001110xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2606;
+ return 2628;
}
else
{
10987654321098765432109876543210
x1011001110xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2610;
+ return 2632;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0000x1xxxxxxxxxx
cpyfe. */
- return 2666;
+ return 2688;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0000x1xxxxxxxxxx
setp. */
- return 2760;
+ return 2782;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1000x1xxxxxxxxxx
cpyfern. */
- return 2672;
+ return 2694;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1000x1xxxxxxxxxx
sete. */
- return 2762;
+ return 2784;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0100x1xxxxxxxxxx
cpyfewn. */
- return 2669;
+ return 2691;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0100x1xxxxxxxxxx
setm. */
- return 2761;
+ return 2783;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1100x1xxxxxxxxxx
cpyfen. */
- return 2675;
+ return 2697;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0010x1xxxxxxxxxx
cpyfert. */
- return 2690;
+ return 2712;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0010x1xxxxxxxxxx
setpn. */
- return 2766;
+ return 2788;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1010x1xxxxxxxxxx
cpyfertrn. */
- return 2696;
+ return 2718;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1010x1xxxxxxxxxx
seten. */
- return 2768;
+ return 2790;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0110x1xxxxxxxxxx
cpyfertwn. */
- return 2693;
+ return 2715;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0110x1xxxxxxxxxx
setmn. */
- return 2767;
+ return 2789;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1110x1xxxxxxxxxx
cpyfertn. */
- return 2699;
+ return 2721;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0001x1xxxxxxxxxx
cpyfewt. */
- return 2678;
+ return 2700;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0001x1xxxxxxxxxx
setpt. */
- return 2763;
+ return 2785;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1001x1xxxxxxxxxx
cpyfewtrn. */
- return 2684;
+ return 2706;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1001x1xxxxxxxxxx
setet. */
- return 2765;
+ return 2787;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0101x1xxxxxxxxxx
cpyfewtwn. */
- return 2681;
+ return 2703;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0101x1xxxxxxxxxx
setmt. */
- return 2764;
+ return 2786;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1101x1xxxxxxxxxx
cpyfewtn. */
- return 2687;
+ return 2709;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0011x1xxxxxxxxxx
cpyfet. */
- return 2702;
+ return 2724;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0011x1xxxxxxxxxx
setptn. */
- return 2769;
+ return 2791;
}
}
else
10987654321098765432109876543210
xx011001100xxxxx1011x1xxxxxxxxxx
cpyfetrn. */
- return 2708;
+ return 2730;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx1011x1xxxxxxxxxx
setetn. */
- return 2771;
+ return 2793;
}
}
}
10987654321098765432109876543210
xx011001100xxxxx0111x1xxxxxxxxxx
cpyfetwn. */
- return 2705;
+ return 2727;
}
else
{
10987654321098765432109876543210
xx011001110xxxxx0111x1xxxxxxxxxx
setmtn. */
- return 2770;
+ return 2792;
}
}
else
10987654321098765432109876543210
xx0110011x0xxxxx1111x1xxxxxxxxxx
cpyfetn. */
- return 2711;
+ return 2733;
}
}
}
10987654321098765432109876543210
x1x11010110xxxx0x01000xxxxxxxxxx
abs. */
- return 2789;
+ return 2811;
}
else
{
10987654321098765432109876543210
xxx11010110xxxxxx11000xxxxxxxxxx
smax. */
- return 2792;
+ return 2814;
}
}
}
10987654321098765432109876543210
xxx11010x00xxxxxx0xx10xxxxxxxxxx
setf8. */
- return 2602;
+ return 2624;
}
else
{
10987654321098765432109876543210
xxx11010x00xxxxxx1xx10xxxxxxxxxx
setf16. */
- return 2603;
+ return 2625;
}
}
else
10987654321098765432109876543210
xxx11010110xxxxxx11010xxxxxxxxxx
smin. */
- return 2794;
+ return 2816;
}
}
}
10987654321098765432109876543210
xxx11010110xxxx0x00110xxxxxxxxxx
ctz. */
- return 2791;
+ return 2813;
}
else
{
10987654321098765432109876543210
xxx11010000xxxxxxxxx01xxxxxxxxxx
rmif. */
- return 2601;
+ return 2623;
}
else
{
10987654321098765432109876543210
xxx11010x10xxxxxx11001xxxxxxxxxx
umax. */
- return 2793;
+ return 2815;
}
}
}
10987654321098765432109876543210
xxx11010xx0xxxxxx11011xxxxxxxxxx
umin. */
- return 2795;
+ return 2817;
}
}
}
10987654321098765432109876543210
xxx11010xx0xxxx0x00111xxxxxxxxxx
cnt. */
- return 2790;
+ return 2812;
}
else
{
10987654321098765432109876543210
010001x01x1xxxxx000110xxxxxxxxxx
usdot. */
- return 2621;
+ return 2643;
}
}
}
10987654321098765432109876543210
010001x01x1xxxxx000111xxxxxxxxxx
sudot. */
- return 2622;
+ return 2644;
}
}
}
10987654321098765432109876543210
010001x0xx0xxxxx011110xxxxxxxxxx
usdot. */
- return 2620;
+ return 2642;
}
}
}
10987654321098765432109876543210
011001x0100xxx10101xxxxxxxxxxxxx
bfcvtnt. */
- return 2649;
+ return 2671;
}
}
else
10987654321098765432109876543210
101001x00x1xxxxxx00xxxxxxxxxxxxx
ld1rob. */
- return 2625;
+ return 2647;
}
else
{
10987654321098765432109876543210
101001x01x1xxxxxx00xxxxxxxxxxxxx
ld1roh. */
- return 2626;
+ return 2648;
}
}
else
10987654321098765432109876543210
011001x0011xxxxx010xxxxxxxxxxxxx
bfdot. */
- return 2646;
+ return 2668;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx010xx0xxxxxxxxxx
bfmlalb. */
- return 2653;
+ return 2675;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx010xx1xxxxxxxxxx
bfmlalt. */
- return 2652;
+ return 2674;
}
}
else
10987654321098765432109876543210
x11001x0011xxxxx1x0xxxxxxxxxxxxx
bfdot. */
- return 2645;
+ return 2667;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx1x0xx0xxxxxxxxxx
bfmlalb. */
- return 2651;
+ return 2673;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx1x0xx1xxxxxxxxxx
bfmlalt. */
- return 2650;
+ return 2672;
}
}
else
10987654321098765432109876543210
101001x00x1xxxxx001xxxxxxxxxxxxx
ld1rob. */
- return 2629;
+ return 2651;
}
else
{
10987654321098765432109876543210
101001x01x1xxxxx001xxxxxxxxxxxxx
ld1roh. */
- return 2630;
+ return 2652;
}
}
else
10987654321098765432109876543210
011001x0101xxxxx111xxxxxxxxxxxxx
fmmla. */
- return 2623;
+ return 2645;
}
else
{
10987654321098765432109876543210
011001x0011xxxxx111xxxxxxxxxxxxx
bfmmla. */
- return 2647;
+ return 2669;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx111xxxxxxxxxxxxx
fmmla. */
- return 2624;
+ return 2646;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000x00xxxxxxxxxx
zip1. */
- return 2633;
+ return 2655;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000010xxxxxxxxxx
uzp1. */
- return 2635;
+ return 2657;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000110xxxxxxxxxx
trn1. */
- return 2637;
+ return 2659;
}
}
}
10987654321098765432109876543210
000001x1101xxxxx000x01xxxxxxxxxx
zip2. */
- return 2634;
+ return 2656;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000011xxxxxxxxxx
uzp2. */
- return 2636;
+ return 2658;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000111xxxxxxxxxx
trn2. */
- return 2638;
+ return 2660;
}
}
}
10987654321098765432109876543210
010001x1000xxxxx100110xxxxxxxxxx
smmla. */
- return 2617;
+ return 2639;
}
else
{
10987654321098765432109876543210
010001x1100xxxxx100110xxxxxxxxxx
usmmla. */
- return 2619;
+ return 2641;
}
}
else
10987654321098765432109876543210
010001x1x10xxxxx100110xxxxxxxxxx
ummla. */
- return 2618;
+ return 2640;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx000xxxxxxxxxxxxx
ld1row. */
- return 2627;
+ return 2649;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx000xxxxxxxxxxxxx
ld1rod. */
- return 2628;
+ return 2650;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx001xxxxxxxxxxxxx
ld1row. */
- return 2631;
+ return 2653;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx001xxxxxxxxxxxxx
ld1rod. */
- return 2632;
+ return 2654;
}
}
}
{
if (((word >> 31) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 001001x1xx1xxxxx01xxxxxxxxxxxxxx
- psel. */
- return 2418;
+ if (((word >> 4) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx01xxxxxxxxx0xxxx
+ psel. */
+ return 2418;
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx01x000xxxxx10xxx
+ whilege. */
+ return 2578;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx01x000xxxxx11xxx
+ whilegt. */
+ return 2579;
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 0) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx010100xxxxx1xxx0
+ whilege. */
+ return 2420;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx010100xxxxx1xxx1
+ whilegt. */
+ return 2421;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx011100xxxxx1xxxx
+ pext. */
+ return 2509;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx01x010xxxxx10xxx
+ whilehs. */
+ return 2581;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx01x010xxxxx11xxx
+ whilehi. */
+ return 2580;
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 0) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx010110xxxxx1xxx0
+ whilehs. */
+ return 2423;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx010110xxxxx1xxx1
+ whilehi. */
+ return 2422;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx011110xxxxx1xxxx
+ ptrue. */
+ return 2511;
+ }
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx01x001xxxxx10xxx
+ whilelt. */
+ return 2585;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx01x001xxxxx11xxx
+ whilele. */
+ return 2582;
+ }
+ }
+ else
+ {
+ if (((word >> 13) & 0x1) == 0)
+ {
+ if (((word >> 0) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx010101xxxxx1xxx0
+ whilelt. */
+ return 2427;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx010101xxxxx1xxx1
+ whilele. */
+ return 2424;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx011101xxxxx1xxxx
+ pext. */
+ return 2510;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 3) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx01x011xxxxx10xxx
+ whilelo. */
+ return 2583;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx01x011xxxxx11xxx
+ whilels. */
+ return 2584;
+ }
+ }
+ else
+ {
+ if (((word >> 0) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx01x111xxxxx1xxx0
+ whilelo. */
+ return 2425;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx1xxxxx01x111xxxxx1xxx1
+ whilels. */
+ return 2426;
+ }
+ }
+ }
+ }
+ }
}
else
{
10987654321098765432109876543210
011001x110001x10101xxxxxxxxxxxxx
bfcvt. */
- return 2648;
+ return 2670;
}
}
else
{
if (((word >> 31) & 0x1) == 0)
{
- if (((word >> 16) & 0x1) == 0)
+ if (((word >> 9) & 0x1) == 0)
{
- if (((word >> 17) & 0x1) == 0)
+ if (((word >> 16) & 0x1) == 0)
{
- if (((word >> 18) & 0x1) == 0)
+ if (((word >> 17) & 0x1) == 0)
{
- if (((word >> 19) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 001001x1xx10000010xxxxxxxxxxxxxx
- cntp. */
- return 1365;
- }
- else
+ if (((word >> 18) & 0x1) == 0)
{
- if (((word >> 10) & 0x1) == 0)
+ if (((word >> 19) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx10000010xxxx0xxxxxxxxx
+ cntp. */
+ return 1365;
+ }
+ else
{
- if (((word >> 11) & 0x1) == 0)
+ if (((word >> 10) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 11) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 001001x1xx10100010x000xxxxxxxxxx
- sqincp. */
- return 1874;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx10100010x0000xxxxxxxxx
+ sqincp. */
+ return 1874;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx10100010x1000xxxxxxxxx
+ wrffr. */
+ return 2048;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 001001x1xx10100010x100xxxxxxxxxx
- wrffr. */
- return 2048;
+ 001001x1xx10100010xx100xxxxxxxxx
+ sqincp. */
+ return 1876;
}
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 001001x1xx10100010xx10xxxxxxxxxx
+ 001001x1xx10100010xxx10xxxxxxxxx
sqincp. */
- return 1876;
+ return 1875;
+ }
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx10x10010x00x0xxxxxxxxx
+ incp. */
+ return 1503;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx10x10010x10x0xxxxxxxxx
+ setffr. */
+ return 1841;
}
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 001001x1xx10100010xxx1xxxxxxxxxx
- sqincp. */
- return 1875;
+ 001001x1xx10x10010xx1x0xxxxxxxxx
+ incp. */
+ return 1504;
}
}
}
else
{
- if (((word >> 11) & 0x1) == 0)
+ if (((word >> 10) & 0x1) == 0)
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 11) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 001001x1xx10x10010x00xxxxxxxxxxx
- incp. */
- return 1503;
+ 001001x1xx10xx1010xx000xxxxxxxxx
+ sqdecp. */
+ return 1860;
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 001001x1xx10x10010x10xxxxxxxxxxx
- setffr. */
- return 1841;
+ 001001x1xx10xx1010xx100xxxxxxxxx
+ sqdecp. */
+ return 1862;
}
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 001001x1xx10x10010xx1xxxxxxxxxxx
- incp. */
- return 1504;
+ 001001x1xx10xx1010xxx10xxxxxxxxx
+ sqdecp. */
+ return 1861;
}
}
}
{
if (((word >> 11) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 001001x1xx10xx1010xx00xxxxxxxxxx
- sqdecp. */
- return 1860;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 001001x1xx10xx1010xx10xxxxxxxxxx
- sqdecp. */
- return 1862;
- }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 001001x1xx10xx1010xxx1xxxxxxxxxx
- sqdecp. */
- return 1861;
- }
- }
- }
- else
- {
- if (((word >> 10) & 0x1) == 0)
- {
- if (((word >> 11) & 0x1) == 0)
- {
- if (((word >> 17) & 0x1) == 0)
- {
- if (((word >> 18) & 0x1) == 0)
+ if (((word >> 17) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 001001x1xx10x00110xx00xxxxxxxxxx
- uqincp. */
- return 2023;
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx10x00110xx000xxxxxxxxx
+ uqincp. */
+ return 2023;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx10x10110xx000xxxxxxxxx
+ decp. */
+ return 1378;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 001001x1xx10x10110xx00xxxxxxxxxx
- decp. */
- return 1378;
+ 001001x1xx10xx1110xx000xxxxxxxxx
+ uqdecp. */
+ return 2009;
}
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 001001x1xx10xx1110xx00xxxxxxxxxx
- uqdecp. */
- return 2009;
- }
- }
- else
- {
- if (((word >> 17) & 0x1) == 0)
- {
- if (((word >> 18) & 0x1) == 0)
+ if (((word >> 17) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 001001x1xx10x00110xx10xxxxxxxxxx
- uqincp. */
- return 2024;
+ if (((word >> 18) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx10x00110xx100xxxxxxxxx
+ uqincp. */
+ return 2024;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx10x10110xx100xxxxxxxxx
+ decp. */
+ return 1379;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 001001x1xx10x10110xx10xxxxxxxxxx
- decp. */
- return 1379;
+ 001001x1xx10xx1110xx100xxxxxxxxx
+ uqdecp. */
+ return 2010;
}
}
+ }
+ else
+ {
+ if (((word >> 17) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx10xx0110xxx10xxxxxxxxx
+ uqincp. */
+ return 2025;
+ }
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 001001x1xx10xx1110xx10xxxxxxxxxx
+ 001001x1xx10xx1110xxx10xxxxxxxxx
uqdecp. */
- return 2010;
+ return 2011;
}
}
}
- else
- {
- if (((word >> 17) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 001001x1xx10xx0110xxx1xxxxxxxxxx
- uqincp. */
- return 2025;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 001001x1xx10xx1110xxx1xxxxxxxxxx
- uqdecp. */
- return 2011;
- }
- }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 001001x1xx10xxxx10xxxx1xxxxxxxxx
+ cntp. */
+ return 2428;
}
}
else
10987654321098765432109876543210
x1010100xxxxxxxxxxxxxxxxxxx1xxxx
bc.c. */
- return 2784;
+ return 2806;
}
else
{
10987654321098765432109876543210
xx01110100xxxxxx0000xxxxxxxxxxxx
cpyp. */
- return 2712;
+ return 2734;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0000xxxxxxxxxxxx
cpye. */
- return 2714;
+ return 2736;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1000xxxxxxxxxxxx
cpyprn. */
- return 2718;
+ return 2740;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1000xxxxxxxxxxxx
cpyern. */
- return 2720;
+ return 2742;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0100xxxxxxxxxxxx
cpypwn. */
- return 2715;
+ return 2737;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0100xxxxxxxxxxxx
cpyewn. */
- return 2717;
+ return 2739;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1100xxxxxxxxxxxx
cpypn. */
- return 2721;
+ return 2743;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1100xxxxxxxxxxxx
cpyen. */
- return 2723;
+ return 2745;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0010xxxxxxxxxxxx
cpyprt. */
- return 2736;
+ return 2758;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0010xxxxxxxxxxxx
cpyert. */
- return 2738;
+ return 2760;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1010xxxxxxxxxxxx
cpyprtrn. */
- return 2742;
+ return 2764;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1010xxxxxxxxxxxx
cpyertrn. */
- return 2744;
+ return 2766;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0110xxxxxxxxxxxx
cpyprtwn. */
- return 2739;
+ return 2761;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0110xxxxxxxxxxxx
cpyertwn. */
- return 2741;
+ return 2763;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1110xxxxxxxxxxxx
cpyprtn. */
- return 2745;
+ return 2767;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1110xxxxxxxxxxxx
cpyertn. */
- return 2747;
+ return 2769;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0001xxxxxxxxxxxx
cpypwt. */
- return 2724;
+ return 2746;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0001xxxxxxxxxxxx
cpyewt. */
- return 2726;
+ return 2748;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1001xxxxxxxxxxxx
cpypwtrn. */
- return 2730;
+ return 2752;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1001xxxxxxxxxxxx
cpyewtrn. */
- return 2732;
+ return 2754;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0101xxxxxxxxxxxx
cpypwtwn. */
- return 2727;
+ return 2749;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0101xxxxxxxxxxxx
cpyewtwn. */
- return 2729;
+ return 2751;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1101xxxxxxxxxxxx
cpypwtn. */
- return 2733;
+ return 2755;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1101xxxxxxxxxxxx
cpyewtn. */
- return 2735;
+ return 2757;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0011xxxxxxxxxxxx
cpypt. */
- return 2748;
+ return 2770;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0011xxxxxxxxxxxx
cpyet. */
- return 2750;
+ return 2772;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1011xxxxxxxxxxxx
cpyptrn. */
- return 2754;
+ return 2776;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1011xxxxxxxxxxxx
cpyetrn. */
- return 2756;
+ return 2778;
}
}
}
10987654321098765432109876543210
xx01110100xxxxxx0111xxxxxxxxxxxx
cpyptwn. */
- return 2751;
+ return 2773;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx0111xxxxxxxxxxxx
cpyetwn. */
- return 2753;
+ return 2775;
}
}
else
10987654321098765432109876543210
xx01110100xxxxxx1111xxxxxxxxxxxx
cpyptn. */
- return 2757;
+ return 2779;
}
else
{
10987654321098765432109876543210
xx01110110xxxxxx1111xxxxxxxxxxxx
cpyetn. */
- return 2759;
+ return 2781;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0000xxxxxxxxxxxx
cpym. */
- return 2713;
+ return 2735;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0000xxxxxxxxxxxx
setgp. */
- return 2772;
+ return 2794;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1000xxxxxxxxxxxx
cpymrn. */
- return 2719;
+ return 2741;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1000xxxxxxxxxxxx
setge. */
- return 2774;
+ return 2796;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0100xxxxxxxxxxxx
cpymwn. */
- return 2716;
+ return 2738;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0100xxxxxxxxxxxx
setgm. */
- return 2773;
+ return 2795;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1100xxxxxxxxxxxx
cpymn. */
- return 2722;
+ return 2744;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0010xxxxxxxxxxxx
cpymrt. */
- return 2737;
+ return 2759;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0010xxxxxxxxxxxx
setgpn. */
- return 2778;
+ return 2800;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1010xxxxxxxxxxxx
cpymrtrn. */
- return 2743;
+ return 2765;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1010xxxxxxxxxxxx
setgen. */
- return 2780;
+ return 2802;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0110xxxxxxxxxxxx
cpymrtwn. */
- return 2740;
+ return 2762;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0110xxxxxxxxxxxx
setgmn. */
- return 2779;
+ return 2801;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1110xxxxxxxxxxxx
cpymrtn. */
- return 2746;
+ return 2768;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0001xxxxxxxxxxxx
cpymwt. */
- return 2725;
+ return 2747;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0001xxxxxxxxxxxx
setgpt. */
- return 2775;
+ return 2797;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1001xxxxxxxxxxxx
cpymwtrn. */
- return 2731;
+ return 2753;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1001xxxxxxxxxxxx
setget. */
- return 2777;
+ return 2799;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0101xxxxxxxxxxxx
cpymwtwn. */
- return 2728;
+ return 2750;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0101xxxxxxxxxxxx
setgmt. */
- return 2776;
+ return 2798;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1101xxxxxxxxxxxx
cpymwtn. */
- return 2734;
+ return 2756;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0011xxxxxxxxxxxx
cpymt. */
- return 2749;
+ return 2771;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0011xxxxxxxxxxxx
setgptn. */
- return 2781;
+ return 2803;
}
}
else
10987654321098765432109876543210
xx01110101xxxxxx1011xxxxxxxxxxxx
cpymtrn. */
- return 2755;
+ return 2777;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx1011xxxxxxxxxxxx
setgetn. */
- return 2783;
+ return 2805;
}
}
}
10987654321098765432109876543210
xx01110101xxxxxx0111xxxxxxxxxxxx
cpymtwn. */
- return 2752;
+ return 2774;
}
else
{
10987654321098765432109876543210
xx01110111xxxxxx0111xxxxxxxxxxxx
setgmtn. */
- return 2782;
+ return 2804;
}
}
else
10987654321098765432109876543210
xx011101x1xxxxxx1111xxxxxxxxxxxx
cpymtn. */
- return 2758;
+ return 2780;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x1001xxxxxxxxxx
smmla. */
- return 2639;
+ return 2661;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x0101xxxxxxxxxx
sdot. */
- return 2565;
+ return 2587;
}
}
else
10987654321098765432109876543210
0x001110xx0xxxxx1x1011xxxxxxxxxx
usmmla. */
- return 2641;
+ return 2663;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x0111xxxxxxxxxx
usdot. */
- return 2642;
+ return 2664;
}
}
else
10987654321098765432109876543210
1x001110000xxxxxxxxxxxxxxxxxxxxx
eor3. */
- return 2572;
+ return 2594;
}
else
{
10987654321098765432109876543210
1x001110100xxxxxxxxxxxxxxxxxxxxx
xar. */
- return 2574;
+ return 2596;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx0xxxxxxxxxxxxxxx
sm3ss1. */
- return 2576;
+ return 2598;
}
else
{
10987654321098765432109876543210
1x001110010xxxxx1xxx00xxxxxxxxxx
sm3tt1a. */
- return 2577;
+ return 2599;
}
else
{
10987654321098765432109876543210
1x001110110xxxxx1xxx00xxxxxxxxxx
sha512su0. */
- return 2570;
+ return 2592;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx1xxx10xxxxxxxxxx
sm3tt2a. */
- return 2579;
+ return 2601;
}
}
else
10987654321098765432109876543210
1x001110010xxxxx1xxx01xxxxxxxxxx
sm3tt1b. */
- return 2578;
+ return 2600;
}
else
{
10987654321098765432109876543210
1x001110110xxxxx1xxx01xxxxxxxxxx
sm4e. */
- return 2583;
+ return 2605;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx1xxx11xxxxxxxxxx
sm3tt2b. */
- return 2580;
+ return 2602;
}
}
}
10987654321098765432109876543210
xx101110xx0xxxxx100101xxxxxxxxxx
udot. */
- return 2564;
+ return 2586;
}
}
else
10987654321098765432109876543210
xx101110xx0xxxxx101x01xxxxxxxxxx
ummla. */
- return 2640;
+ return 2662;
}
else
{
10987654321098765432109876543210
xx101110xx0xxxxx1x1011xxxxxxxxxx
bfmmla. */
- return 2656;
+ return 2678;
}
else
{
10987654321098765432109876543210
xx1011100x0xxxxx1x1111xxxxxxxxxx
bfdot. */
- return 2654;
+ return 2676;
}
else
{
10987654321098765432109876543210
x01011101x0xxxxx1x1111xxxxxxxxxx
bfmlalb. */
- return 2661;
+ return 2683;
}
else
{
10987654321098765432109876543210
x11011101x0xxxxx1x1111xxxxxxxxxx
bfmlalt. */
- return 2660;
+ return 2682;
}
}
}
10987654321098765432109876543210
000011101x1xxxx1011010xxxxxxxxxx
bfcvtn. */
- return 2657;
+ return 2679;
}
else
{
10987654321098765432109876543210
010011101x1xxxx1011010xxxxxxxxxx
bfcvtn2. */
- return 2658;
+ return 2680;
}
}
}
10987654321098765432109876543210
1x001110xx1xxxxx0xxxxxxxxxxxxxxx
bcax. */
- return 2575;
+ return 2597;
}
}
else
10987654321098765432109876543210
11001110xx1xxxxx100000xxxxxxxxxx
sha512h. */
- return 2568;
+ return 2590;
}
}
}
10987654321098765432109876543210
11001110xx1xxxxx110000xxxxxxxxxx
sm3partw1. */
- return 2581;
+ return 2603;
}
}
}
10987654321098765432109876543210
1x001110xx1xxxxx100010xxxxxxxxxx
sha512su1. */
- return 2571;
+ return 2593;
}
}
else
10987654321098765432109876543210
1x0011100x1xxxxx110010xxxxxxxxxx
sm4ekey. */
- return 2584;
+ return 2606;
}
}
else
10987654321098765432109876543210
1x001110xx1xxxxx100001xxxxxxxxxx
sha512h2. */
- return 2569;
+ return 2591;
}
}
else
10987654321098765432109876543210
1x0011100x1xxxxx110001xxxxxxxxxx
sm3partw2. */
- return 2582;
+ return 2604;
}
}
else
10987654321098765432109876543210
1x001110xx1xxxxx100011xxxxxxxxxx
rax1. */
- return 2573;
+ return 2595;
}
}
else
10987654321098765432109876543210
x01011100x1xxxxx110011xxxxxxxxxx
fmlal2. */
- return 2587;
+ return 2609;
}
else
{
10987654321098765432109876543210
x11011100x1xxxxx110011xxxxxxxxxx
fmlal2. */
- return 2591;
+ return 2613;
}
}
}
10987654321098765432109876543210
x01011101x1xxxxx110011xxxxxxxxxx
fmlsl2. */
- return 2588;
+ return 2610;
}
else
{
10987654321098765432109876543210
x11011101x1xxxxx110011xxxxxxxxxx
fmlsl2. */
- return 2592;
+ return 2614;
}
}
}
10987654321098765432109876543210
x00011100x1xxxxx111011xxxxxxxxxx
fmlal. */
- return 2585;
+ return 2607;
}
else
{
10987654321098765432109876543210
x10011100x1xxxxx111011xxxxxxxxxx
fmlal. */
- return 2589;
+ return 2611;
}
}
else
10987654321098765432109876543210
x00011101x1xxxxx111011xxxxxxxxxx
fmlsl. */
- return 2586;
+ return 2608;
}
else
{
10987654321098765432109876543210
x10011101x1xxxxx111011xxxxxxxxxx
fmlsl. */
- return 2590;
+ return 2612;
}
}
else
10987654321098765432109876543210
x0001111xxxxxxxx0000x0xxxxxxxxxx
fmlal. */
- return 2593;
+ return 2615;
}
else
{
10987654321098765432109876543210
x1001111xxxxxxxx0000x0xxxxxxxxxx
fmlal. */
- return 2597;
+ return 2619;
}
}
else
10987654321098765432109876543210
x0001111xxxxxxxx0100x0xxxxxxxxxx
fmlsl. */
- return 2594;
+ return 2616;
}
else
{
10987654321098765432109876543210
x1001111xxxxxxxx0100x0xxxxxxxxxx
fmlsl. */
- return 2598;
+ return 2620;
}
}
else
10987654321098765432109876543210
x0101111xxxxxxxx1000x0xxxxxxxxxx
fmlal2. */
- return 2595;
+ return 2617;
}
else
{
10987654321098765432109876543210
x1101111xxxxxxxx1000x0xxxxxxxxxx
fmlal2. */
- return 2599;
+ return 2621;
}
}
}
10987654321098765432109876543210
x0101111xxxxxxxx1100x0xxxxxxxxxx
fmlsl2. */
- return 2596;
+ return 2618;
}
else
{
10987654321098765432109876543210
x1101111xxxxxxxx1100x0xxxxxxxxxx
fmlsl2. */
- return 2600;
+ return 2622;
}
}
}
10987654321098765432109876543210
xx001111xxxxxxxx1110x0xxxxxxxxxx
sdot. */
- return 2567;
+ return 2589;
}
else
{
10987654321098765432109876543210
xx101111xxxxxxxx1110x0xxxxxxxxxx
udot. */
- return 2566;
+ return 2588;
}
}
}
10987654321098765432109876543210
xx00111100xxxxxx1111x0xxxxxxxxxx
sudot. */
- return 2644;
+ return 2666;
}
else
{
10987654321098765432109876543210
xx00111110xxxxxx1111x0xxxxxxxxxx
usdot. */
- return 2643;
+ return 2665;
}
}
else
10987654321098765432109876543210
xx00111101xxxxxx1111x0xxxxxxxxxx
bfdot. */
- return 2655;
+ return 2677;
}
else
{
10987654321098765432109876543210
x000111111xxxxxx1111x0xxxxxxxxxx
bfmlalb. */
- return 2663;
+ return 2685;
}
else
{
10987654321098765432109876543210
x100111111xxxxxx1111x0xxxxxxxxxx
bfmlalt. */
- return 2662;
+ return 2684;
}
}
}
{
case 2389: value = 2391; break; /* mov --> mova. */
case 2391: return NULL; /* mova --> NULL. */
- case 2490: value = 2498; break; /* mov --> mova. */
- case 2498: return NULL; /* mova --> NULL. */
- case 2488: value = 2496; break; /* mov --> mova. */
- case 2496: return NULL; /* mova --> NULL. */
- case 2491: value = 2499; break; /* mov --> mova. */
- case 2499: return NULL; /* mova --> NULL. */
- case 2489: value = 2497; break; /* mov --> mova. */
- case 2497: return NULL; /* mova --> NULL. */
+ case 2499: value = 2507; break; /* mov --> mova. */
+ case 2507: return NULL; /* mova --> NULL. */
+ case 2497: value = 2505; break; /* mov --> mova. */
+ case 2505: return NULL; /* mova --> NULL. */
+ case 2500: value = 2508; break; /* mov --> mova. */
+ case 2508: return NULL; /* mova --> NULL. */
+ case 2498: value = 2506; break; /* mov --> mova. */
+ case 2506: return NULL; /* mova --> NULL. */
case 2388: value = 2390; break; /* mov --> mova. */
case 2390: return NULL; /* mova --> NULL. */
- case 2486: value = 2494; break; /* mov --> mova. */
- case 2494: return NULL; /* mova --> NULL. */
- case 2484: value = 2492; break; /* mov --> mova. */
- case 2492: return NULL; /* mova --> NULL. */
- case 2487: value = 2495; break; /* mov --> mova. */
- case 2495: return NULL; /* mova --> NULL. */
- case 2485: value = 2493; break; /* mov --> mova. */
- case 2493: return NULL; /* mova --> NULL. */
+ case 2495: value = 2503; break; /* mov --> mova. */
+ case 2503: return NULL; /* mova --> NULL. */
+ case 2493: value = 2501; break; /* mov --> mova. */
+ case 2501: return NULL; /* mova --> NULL. */
+ case 2496: value = 2504; break; /* mov --> mova. */
+ case 2504: return NULL; /* mova --> NULL. */
+ case 2494: value = 2502; break; /* mov --> mova. */
+ case 2502: return NULL; /* mova --> NULL. */
case 2393: value = 2398; break; /* ld1b --> ld1b. */
case 2398: return NULL; /* ld1b --> NULL. */
case 2395: value = 2400; break; /* ld1w --> ld1w. */
case 2407: value = 2412; break; /* st1q --> st1q. */
case 2412: return NULL; /* st1q --> NULL. */
case 12: value = 19; break; /* add --> addg. */
- case 19: value = 2785; break; /* addg --> smax. */
- case 2785: value = 2786; break; /* smax --> umax. */
- case 2786: value = 2787; break; /* umax --> smin. */
- case 2787: value = 2788; break; /* smin --> umin. */
- case 2788: return NULL; /* umin --> NULL. */
+ case 19: value = 2807; break; /* addg --> smax. */
+ case 2807: value = 2808; break; /* smax --> umax. */
+ case 2808: value = 2809; break; /* umax --> smin. */
+ case 2809: value = 2810; break; /* smin --> umin. */
+ case 2810: return NULL; /* umin --> NULL. */
case 16: value = 20; break; /* sub --> subg. */
case 20: return NULL; /* subg --> NULL. */
case 971: value = 975; break; /* stnp --> stp. */
case 824: return NULL; /* fsqrt --> NULL. */
case 832: value = 833; break; /* frintz --> frintz. */
case 833: return NULL; /* frintz --> NULL. */
- case 825: value = 2659; break; /* fcvt --> bfcvt. */
- case 2659: return NULL; /* bfcvt --> NULL. */
+ case 825: value = 2681; break; /* fcvt --> bfcvt. */
+ case 2681: return NULL; /* bfcvt --> NULL. */
case 834: value = 835; break; /* frinta --> frinta. */
case 835: return NULL; /* frinta --> NULL. */
case 836: value = 837; break; /* frintx --> frintx. */
case 203:
case 209:
case 212:
- case 220:
- case 221:
- case 226:
- case 227:
+ case 222:
+ case 223:
+ case 230:
+ case 231:
+ case 232:
+ case 233:
return aarch64_ext_regno (self, info, code, inst, errors);
case 10:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
case 33:
case 34:
case 35:
- case 237:
+ case 247:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ext_reglist (self, info, code, inst, errors);
case 192:
case 193:
case 194:
- case 228:
case 236:
- case 241:
- case 242:
+ case 244:
+ case 245:
+ case 246:
+ case 251:
+ case 252:
return aarch64_ext_imm (self, info, code, inst, errors);
case 44:
case 45:
return aarch64_ext_sve_index (self, info, code, inst, errors);
case 211:
case 213:
+ case 229:
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
case 214:
case 215:
case 216:
case 217:
- return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
case 218:
case 219:
+ case 228:
+ return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
+ case 220:
+ case 221:
return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors);
- case 222:
case 224:
- case 229:
+ case 226:
+ case 237:
return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
- case 223:
case 225:
+ case 227:
return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
- case 230:
- case 231:
- case 232:
- return aarch64_ext_sme_za_array (self, info, code, inst, errors);
- case 233:
- return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 234:
- return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
case 235:
- return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ return aarch64_ext_simple_index (self, info, code, inst, errors);
case 238:
case 239:
case 240:
+ return aarch64_ext_sme_za_array (self, info, code, inst, errors);
+ case 241:
+ return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
+ case 242:
+ return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
+ case 243:
+ return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case 248:
+ case 249:
+ case 250:
return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}
return value;
}
-/* Extract the value of all fields in SELF->fields from instruction CODE.
- The least significant bit comes from the final field. */
+/* Extract the value of all fields in SELF->fields after START from
+ instruction CODE. The least significant bit comes from the final field. */
static aarch64_insn
-extract_all_fields (const aarch64_operand *self, aarch64_insn code)
+extract_all_fields_after (const aarch64_operand *self, unsigned int start,
+ aarch64_insn code)
{
aarch64_insn value;
unsigned int i;
enum aarch64_field_kind kind;
value = 0;
- for (i = 0; i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i)
+ for (i = start;
+ i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i)
{
kind = self->fields[i];
value <<= fields[kind].width;
return value;
}
+/* Extract the value of all fields in SELF->fields from instruction CODE.
+ The least significant bit comes from the final field. */
+
+static aarch64_insn
+extract_all_fields (const aarch64_operand *self, aarch64_insn code)
+{
+ return extract_all_fields_after (self, 0, code);
+}
+
/* Sign-extend bit I of VALUE. */
static inline uint64_t
sign_extend (aarch64_insn value, unsigned i)
info->reg.regno = extract_field (self->fields[0], code, 0);
return info->reg.regno <= 30;
}
+
+/* Decode an indexed register, with the first field being the register
+ number and the remaining fields being the index. */
+bool
+aarch64_ext_simple_index (const aarch64_operand *self, aarch64_opnd_info *info,
+ const aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ int bias = get_operand_specific_data (self);
+ info->reglane.regno = extract_field (self->fields[0], code, 0) + bias;
+ info->reglane.index = extract_all_fields_after (self, 1, code);
+ return true;
+}
\f
/* Bitfields that are commonly used to encode certain operands' information
may be partially used as part of the base opcode in some instructions.
AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1);
AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2);
AARCH64_DECL_OPD_EXTRACTOR (ext_x0_to_x30);
+AARCH64_DECL_OPD_EXTRACTOR (ext_simple_index);
#undef AARCH64_DECL_OPD_EXTRACTOR
{AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm4}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt3}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_srcxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_5}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_destxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_0}, "an SME horizontal or vertical vector access register"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Pdx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pdx2}, "a list of SVE predicate registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_PdxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pd}, "a list of SVE predicate registers"},
{AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SME_PNd3", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_PNd3}, "an SVE predicate-as-counter register"},
{AARCH64_OPND_CLASS_PRED_REG, "SME_PNg3", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg3}, "an SVE predicate-as-counter register"},
+ {AARCH64_OPND_CLASS_PRED_REG, "SME_PNn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate-as-counter register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX1", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_PNn3, FLD_imm1_8}, "an indexed SVE predicate-as-counter register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX2", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_PNn3, FLD_imm2_8}, "an indexed SVE predicate-as-counter register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_0}, "ZA array"},
{AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_10}, "VLx2 or VLx4"},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_13}, "VLx2 or VLx4"},
{AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"},
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
{AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"},
0
};
+/* Vector length multiples for a predicate-as-counter operand. Used in things
+ like AARCH64_OPND_SME_VLxN_10. */
+const char *const aarch64_sme_vlxn_array[2] = {
+ "vlx2",
+ "vlx4"
+};
+
/* Helper functions to determine which operand to be used to encode/decode
the size:Q fields for AdvSIMD instructions. */
{ 10, 5 }, /* Rt2: in load/store pair instructions. */
{ 12, 1 }, /* S: in load/store reg offset instructions. */
{ 12, 2 }, /* SM3_imm2: Indexed element SM3 2 bits index immediate. */
+ { 1, 3 }, /* SME_Pdx2: predicate register, multiple of 2, [3:1]. */
{ 13, 3 }, /* SME_Pm: second source scalable predicate register P0-P7. */
+ { 0, 3 }, /* SME_PNd3: PN0-PN7, bits [2:0]. */
+ { 5, 3 }, /* SME_PNn3: PN0-PN7, bits [7:5]. */
{ 16, 1 }, /* SME_Q: Q class bit, bit 16. */
{ 16, 2 }, /* SME_Rm: index base register W12-W15 [17:16]. */
{ 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */
{ 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
+ { 10, 1 }, /* SME_VL_10: VLx2 or VLx4, bit [10]. */
+ { 13, 1 }, /* SME_VL_13: VLx2 or VLx4, bit [13]. */
{ 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */
{ 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */
{ 1, 4 }, /* SME_Zdn2: Z0-Z31, multiple of 2, bits [4:1]. */
{ 2, 3 }, /* SME_Zdn4: Z0-Z31, multiple of 4, bits [4:2]. */
+ { 17, 4 }, /* SME_Zm2: Z0-Z31, multiple of 2, bits [20:17]. */
+ { 18, 3 }, /* SME_Zm4: Z0-Z31, multiple of 4, bits [20:18]. */
{ 6, 4 }, /* SME_Zn2: Z0-Z31, multiple of 2, bits [9:6]. */
{ 7, 3 }, /* SME_Zn4: Z0-Z31, multiple of 4, bits [9:7]. */
{ 4, 1 }, /* SME_ZtT: upper bit of Zt, bit [4]. */
{ 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
{ 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
{ 21, 2 }, /* hw: in move wide constant instructions. */
+ { 8, 1 }, /* imm1_8: general immediate in bits [8]. */
+ { 8, 2 }, /* imm2_8: general immediate in bits [9:8]. */
{ 0, 3 }, /* imm3_0: general immediate in bits [2:0]. */
{ 5, 3 }, /* imm3_5: general immediate in bits [7:5]. */
{ 10, 3 }, /* imm3_10: in add/sub extended reg instructions. */
return 0;
break;
+ case AARCH64_OPND_SME_PNn3_INDEX1:
+ case AARCH64_OPND_SME_PNn3_INDEX2:
+ size = get_operand_field_width (get_operand_from_code (type), 1);
+ if (!check_reglane (opnd, mismatch_detail, idx, "pn", 8, 15,
+ 0, (1 << size) - 1))
+ return 0;
+ break;
+
case AARCH64_OPND_SME_PnT_Wm_imm:
size = aarch64_get_qualifier_esize (opnd->qualifier);
max_value = 16 / size - 1;
case AARCH64_OPND_CLASS_SVE_REGLIST:
switch (type)
{
+ case AARCH64_OPND_SME_Pdx2:
case AARCH64_OPND_SME_Zdnx2:
case AARCH64_OPND_SME_Zdnx4:
+ case AARCH64_OPND_SME_Zmx2:
+ case AARCH64_OPND_SME_Zmx4:
case AARCH64_OPND_SME_Znx2:
case AARCH64_OPND_SME_Znx4:
num = get_operand_specific_data (&aarch64_operands[type]);
}
break;
+ case AARCH64_OPND_SME_PdxN:
case AARCH64_OPND_SVE_ZnxN:
case AARCH64_OPND_SVE_ZtxN:
num = get_opcode_dependent_value (opcode);
case AARCH64_OPND_CLASS_PRED_REG:
switch (type)
{
+ case AARCH64_OPND_SME_PNd3:
case AARCH64_OPND_SME_PNg3:
if (opnd->reg.regno < 8)
{
print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
const char *prefix, struct aarch64_styler *styler)
{
+ const int mask = (prefix[0] == 'p' ? 15 : 31);
const int num_regs = opnd->reglist.num_regs;
const int stride = opnd->reglist.stride;
const int first_reg = opnd->reglist.first_regno;
- const int last_reg = (first_reg + (num_regs - 1) * stride) & 0x1f;
+ const int last_reg = (first_reg + (num_regs - 1) * stride) & mask;
const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
char tb[16]; /* Temporary buffer. */
else
{
const int reg0 = first_reg;
- const int reg1 = (first_reg + stride) & 0x1f;
- const int reg2 = (first_reg + stride * 2) & 0x1f;
- const int reg3 = (first_reg + stride * 3) & 0x1f;
+ const int reg1 = (first_reg + stride) & mask;
+ const int reg2 = (first_reg + stride * 2) & mask;
+ const int reg3 = (first_reg + stride * 3) & mask;
switch (num_regs)
{
case AARCH64_OPND_SVE_PNg4_10:
case AARCH64_OPND_SVE_PNn:
case AARCH64_OPND_SVE_PNt:
+ case AARCH64_OPND_SME_PNd3:
case AARCH64_OPND_SME_PNg3:
+ case AARCH64_OPND_SME_PNn:
if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
snprintf (buf, size, "%s",
style_reg (styler, "pn%d", opnd->reg.regno));
aarch64_get_qualifier_name (opnd->qualifier)));
break;
+ case AARCH64_OPND_SME_Pdx2:
+ case AARCH64_OPND_SME_PdxN:
+ print_register_list (buf, size, opnd, "p", styler);
+ break;
+
+ case AARCH64_OPND_SME_PNn3_INDEX1:
+ case AARCH64_OPND_SME_PNn3_INDEX2:
+ snprintf (buf, size, "%s[%s]",
+ style_reg (styler, "pn%d", opnd->reglane.regno),
+ style_imm (styler, "%" PRIi64, opnd->reglane.index));
+ break;
+
case AARCH64_OPND_SVE_Za_5:
case AARCH64_OPND_SVE_Za_16:
case AARCH64_OPND_SVE_Zd:
case AARCH64_OPND_SVE_ZtxN:
case AARCH64_OPND_SME_Zdnx2:
case AARCH64_OPND_SME_Zdnx4:
+ case AARCH64_OPND_SME_Zmx2:
+ case AARCH64_OPND_SME_Zmx4:
case AARCH64_OPND_SME_Znx2:
case AARCH64_OPND_SME_Znx4:
case AARCH64_OPND_SME_Ztx2_STRIDED:
style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm));
break;
+ case AARCH64_OPND_SME_VLxN_10:
+ case AARCH64_OPND_SME_VLxN_13:
+ enum_value = opnd->imm.value;
+ assert (enum_value < ARRAY_SIZE (aarch64_sme_vlxn_array));
+ snprintf (buf, size, "%s",
+ style_sub_mnem (styler, aarch64_sme_vlxn_array[enum_value]));
+ break;
+
case AARCH64_OPND_CRn:
case AARCH64_OPND_CRm:
snprintf (buf, size, "%s",
FLD_Rt2,
FLD_S,
FLD_SM3_imm2,
+ FLD_SME_Pdx2,
FLD_SME_Pm,
+ FLD_SME_PNd3,
+ FLD_SME_PNn3,
FLD_SME_Q,
FLD_SME_Rm,
FLD_SME_Rv,
FLD_SME_V,
+ FLD_SME_VL_10,
+ FLD_SME_VL_13,
FLD_SME_ZAda_2b,
FLD_SME_ZAda_3b,
FLD_SME_Zdn2,
FLD_SME_Zdn4,
+ FLD_SME_Zm2,
+ FLD_SME_Zm4,
FLD_SME_Zn2,
FLD_SME_Zn4,
FLD_SME_ZtT,
FLD_cond2,
FLD_defgh,
FLD_hw,
+ FLD_imm1_8,
+ FLD_imm2_8,
FLD_imm3_0,
FLD_imm3_5,
FLD_imm3_10,
QLF3(S_S,X,X), \
QLF3(S_D,X,X), \
}
+#define OP_SVE_VXXU_BHSD \
+{ \
+ QLF4(S_B,X,X,NIL), \
+ QLF4(S_H,X,X,NIL), \
+ QLF4(S_S,X,X,NIL), \
+ QLF4(S_D,X,X,NIL), \
+}
#define OP_SVE_VZVD_BHS \
{ \
QLF4(S_B,P_Z,S_B,S_D), \
QLF3(S_S,P_Z,S_S), \
QLF3(S_D,P_Z,S_D), \
}
+#define OP_SVE_V_BHSD \
+{ \
+ QLF1(S_B), \
+ QLF1(S_H), \
+ QLF1(S_S), \
+ QLF1(S_D), \
+}
#define OP_SVE_V_HSD \
{ \
QLF1(S_H), \
SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
+ /* SME2 extensions to SVE2. */
+ SME2_INSN ("whilege", 0x25205010, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+ SME2_INSN ("whilegt", 0x25205011, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+ SME2_INSN ("whilehi", 0x25205811, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+ SME2_INSN ("whilehs", 0x25205810, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+ SME2_INSN ("whilele", 0x25205411, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+ SME2_INSN ("whilelo", 0x25205c10, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+ SME2_INSN ("whilels", 0x25205c11, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+ SME2_INSN ("whilelt", 0x25205410, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
+
/* SME2 extensions to SME. */
+ SME2_INSN ("cntp", 0x25208200, 0xff3ffa00, sme_size_22, 0, OP3 (Rd, SME_PNn, SME_VLxN_10), OP_SVE_XV_BHSD, 0, 0),
SME2_INSN ("ld1b", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
SME2_INSN ("ld1b", 0xa0408000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
SME2_INSN ("ld1b", 0xa1400000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
SME2_INSN ("mova", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0),
SME2_INSN ("mova", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0),
SME2_INSN ("mova", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0),
+ SME2_INSN ("pext", 0x25207010, 0xff3ffc10, sme_size_22, 0, OP2 (SVE_Pd, SME_PNn3_INDEX2), OP_SVE_VU_BHSD, 0, 0),
+ SME2_INSN ("pext", 0x25207410, 0xff3ffe10, sme_size_22, 0, OP2 (SME_PdxN, SME_PNn3_INDEX1), OP_SVE_VU_BHSD, F_OD (2), 0),
+ SME2_INSN ("ptrue", 0x25207810, 0xff3ffff8, sme_size_22, 0, OP1 (SME_PNd3), OP_SVE_V_BHSD, 0, 0),
+ SME2_INSN ("sel", 0xc1208000, 0xff21e021, sme_size_22, 0, OP4 (SME_Zdnx2, SME_PNg3, SME_Znx2, SME_Zmx2), OP_SVE_VUVV_BHSD, 0, 0),
+ SME2_INSN ("sel", 0xc1218000, 0xff23e063, sme_size_22, 0, OP4 (SME_Zdnx4, SME_PNg3, SME_Znx4, SME_Zmx4), OP_SVE_VUVV_BHSD, 0, 0),
SME2_INSN ("st1b", 0xa0600000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
SME2_INSN ("st1b", 0xa0608000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
SME2_INSN ("st1b", 0xa1600000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
SME2_INSN ("stnt1w", 0xa020c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
SME2_INSN ("stnt1w", 0xa1204008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
SME2_INSN ("stnt1w", 0xa120c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
+ SME2_INSN ("whilege", 0x25204010, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
+ SME2_INSN ("whilegt", 0x25204018, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
+ SME2_INSN ("whilehi", 0x25204818, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
+ SME2_INSN ("whilehs", 0x25204810, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
+ SME2_INSN ("whilele", 0x25204418, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
+ SME2_INSN ("whilelo", 0x25204c10, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
+ SME2_INSN ("whilels", 0x25204c18, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
+ SME2_INSN ("whilelt", 0x25204410, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
/* SIMD Dot Product (optional in v8.2-A). */
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
F(FLD_SME_Zdn2), "a list of SVE vector registers") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx4", 4 << OPD_F_OD_LSB, \
F(FLD_SME_Zdn4), "a list of SVE vector registers") \
+ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2", 2 << OPD_F_OD_LSB, \
+ F(FLD_SME_Zm2), "a list of SVE vector registers") \
+ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx4", 4 << OPD_F_OD_LSB, \
+ F(FLD_SME_Zm4), "a list of SVE vector registers") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx2", 2 << OPD_F_OD_LSB, \
F(FLD_SME_Zn2), "a list of SVE vector registers") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx4", 4 << OPD_F_OD_LSB, \
Y(ZA_ACCESS, sme_za_hv_tiles_range, "SME_ZA_HV_idx_destxN", 0, \
F(FLD_SME_V,FLD_SME_Rv,FLD_imm3_0), \
"an SME horizontal or vertical vector access register") \
+ Y(SVE_REGLIST, sve_aligned_reglist, "SME_Pdx2", 2 << OPD_F_OD_LSB, \
+ F(FLD_SME_Pdx2), "a list of SVE predicate registers") \
+ Y(SVE_REGLIST, sve_reglist, "SME_PdxN", 0, F(FLD_SVE_Pd), \
+ "a list of SVE predicate registers") \
Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \
"an SVE predicate register") \
+ Y(PRED_REG, regno, "SME_PNd3", 8 << OPD_F_OD_LSB, F(FLD_SME_PNd3), \
+ "an SVE predicate-as-counter register") \
Y(PRED_REG, regno, "SME_PNg3", 8 << OPD_F_OD_LSB, F(FLD_SVE_Pg3), \
"an SVE predicate-as-counter register") \
+ Y(PRED_REG, regno, "SME_PNn", 0, F(FLD_SVE_Pn), \
+ "an SVE predicate-as-counter register") \
+ Y(SVE_REG, simple_index, "SME_PNn3_INDEX1", 8 << OPD_F_OD_LSB, \
+ F(FLD_SME_PNn3, FLD_imm1_8), \
+ "an indexed SVE predicate-as-counter register") \
+ Y(SVE_REG, simple_index, "SME_PNn3_INDEX2", 8 << OPD_F_OD_LSB, \
+ F(FLD_SME_PNn3, FLD_imm2_8), \
+ "an indexed SVE predicate-as-counter register") \
Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \
F(FLD_SME_zero_mask), "a list of 64-bit ZA element tiles") \
Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \
Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \
F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \
"Source scalable predicate register with index ") \
+ Y(IMMEDIATE, imm, "SME_VLxN_10", 0, F(FLD_SME_VL_10), \
+ "VLx2 or VLx4") \
+ Y(IMMEDIATE, imm, "SME_VLxN_13", 0, F(FLD_SME_VL_13), \
+ "VLx2 or VLx4") \
Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5), \
"a 16-bit unsigned immediate for TME tcancel") \
Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \
projects / binutils-gdb.git / commitdiff