paragraph explaining regs not always accessible for all ops in svp64.mdwn

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index dec1ff76396cb6f2bf8f9e09c2df0c408cb1a7e3..dae7e7b290cd57365b621e00aabe3ce35bfa6fd9 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -524,6 +524,10 @@ The register files are therefore extended:
 * FP is extended from fp0-32 to fp0-fp127
 * CR Fields are extended from CR0-7 to CR0-127
 
+However due to pressure in `RM.EXTRA` not all these registers
+are accessible by all instructions, particularly those with
+a large number of operands (`madd`, `isel`).
+
 In the following tables register numbers are constructed from the
 standard v3.0B / v3.1B 32 bit register field (RA, FRA) and the EXTRA2
 or EXTRA3 field from the SV Prefix, determined by the specific