[GCC, ARM] armv8 linux toolchain asan testcase fail due to stl missing conditional...

On behalf of Shiva Chen

2015-06-09  Shiva Chen  <shiva0217@gmail.com>

	* sync.md (atomic_load<mode>): Add conditional code for lda/ldr
	(atomic_store<mode>): Likewise.

2015-06-09  Shiva Chen  <shiva0217@gmail.com>

	* gcc.target/arm/stl-cond.c: New test.

From-SVN: r224269

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4af34951803ff427198c550aeaa069459c7feade..95a6df4e3fa01877c92c4bc39b231ce60e160cee 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2015-06-09  Shiva Chen  <shiva0217@gmail.com>
+
+       * sync.md (atomic_load<mode>): Add conditional code for lda/ldr
+       (atomic_store<mode>): Likewise.
+
 2015-06-09  Richard Biener  <rguenther@suse.de>
 
        * cfgloop.c (get_loop_body_in_bfs_order): Fix assert.

diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md
index 44cda61d2738c4be61ee12dd5055e5ecfd471a93..75dd52ea3aa94a227c62b6f77ee78ebf0eee61d5 100644 (file)
--- a/gcc/config/arm/sync.md
+++ b/gcc/config/arm/sync.md
@@ -75,11 +75,12 @@
   {
     enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
     if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_release (model))
-      return \"ldr<sync_sfx>\\t%0, %1\";
+      return \"ldr%(<sync_sfx>%)\\t%0, %1\";
     else
-      return \"lda<sync_sfx>\\t%0, %1\";
+      return \"lda<sync_sfx>%?\\t%0, %1\";
   }
-)
+  [(set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")])
 
 (define_insn "atomic_store<mode>"
   [(set (match_operand:QHSI 0 "memory_operand" "=Q")
@@ -91,11 +92,12 @@
   {
     enum memmodel model = memmodel_from_int (INTVAL (operands[2]));
     if (is_mm_relaxed (model) || is_mm_consume (model) || is_mm_acquire (model))
-      return \"str<sync_sfx>\t%1, %0\";
+      return \"str%(<sync_sfx>%)\t%1, %0\";
     else
-      return \"stl<sync_sfx>\t%1, %0\";
+      return \"stl<sync_sfx>%?\t%1, %0\";
   }
-)
+  [(set_attr "predicable" "yes")
+   (set_attr "predicable_short_it" "no")])
 
 ;; Note that ldrd and vldr are *not* guaranteed to be single-copy atomic,
 ;; even for a 64-bit aligned address.  Instead we use a ldrexd unparied

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 5c21d29fcd872cdcb544f1cf85d8b1d752360568..a51682a380105b00a53dc837e8d8e3de054fd9e7 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2015-06-09  Shiva Chen  <shiva0217@gmail.com>
+
+       * gcc.target/arm/stl-cond.c: New test.
+
 2015-06-09  Richard Biener  <rguenther@suse.de>
 
        PR middle-end/66413

diff --git a/gcc/testsuite/gcc.target/arm/stl-cond.c b/gcc/testsuite/gcc.target/arm/stl-cond.c
new file mode 100644 (file)
index 0000000..de14bb5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/stl-cond.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arm_ok } */ 
+/* { dg-require-effective-target arm_arch_v8a_ok } */
+/* { dg-options "-O2 -marm" } */
+/* { dg-add-options arm_arch_v8a } */
+
+struct backtrace_state
+{
+  int threaded;
+  int lock_alloc;
+};
+
+void foo (struct backtrace_state *state)
+{
+  if (state->threaded)
+    __sync_lock_release (&state->lock_alloc);
+}
+
+/* { dg-final { scan-assembler "stlne" } } */