xcalloc, free);
fprintf (table, "\n/* i386 opcode table. */\n\n");
- fprintf (table, "const insn_template i386_optab[] =\n{\n");
+ fprintf (table, "static const insn_template i386_optab[] =\n{\n");
/* Put everything on opcode array. */
while (!feof (fp))
xstrerror (errno));
fprintf (table, "\n/* i386 register table. */\n\n");
- fprintf (table, "const reg_entry i386_regtab[] =\n{\n");
+ fprintf (table, "static const reg_entry i386_regtab[] =\n{\n");
while (!feof (fp))
{
fprintf (table, "};\n");
- fprintf (table, "\nconst unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab);\n");
+ fprintf (table, "\nstatic const unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab);\n");
}
static void
typedef struct insn_template
{
/* instruction name sans width suffix ("mov" for movl insns) */
- char *name;
+ const char *name;
/* Bitfield arrangement is such that individual fields can be easily
extracted (in native builds at least) - either by at most a masking
}
insn_template;
-extern const insn_template i386_optab[];
-
/* these are for register name --> number & type hash lookup */
typedef struct
{
#define Dw2Inval (-1)
}
reg_entry;
-
-extern const reg_entry i386_regtab[];
-extern const unsigned int i386_regtab_size;
/* i386 opcode table. */
-const insn_template i386_optab[] =
+static const insn_template i386_optab[] =
{
{ "mov", 0xa0, 2, None,
{ 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0,
/* i386 register table. */
-const reg_entry i386_regtab[] =
+static const reg_entry i386_regtab[] =
{
{ "al",
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0,
0, 0, { 39, 64 } },
};
-const unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab);
+static const unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab);