nv50/ir/nir: support gather offsets

v2: only emit offsets if those are !0

Signed-off-by: Karol Herbst <kherbst@redhat.com>

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
index 3051a7cc72e164475b7f2a357cec05d3780d2601..ed0c5d24b8514d4aa131e276f66775e944d5ad41 100644 (file)
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp
@@ -36,6 +36,7 @@
 #else
 #include <tr1/unordered_map>
 #endif
+#include <cstring>
 #include <list>
 #include <vector>
 
@@ -3205,6 +3206,20 @@ Converter::visit(nir_tex_instr *insn)
          }
       }
 
+      if (op == OP_TXG && offsetIdx == -1) {
+         if (nir_tex_instr_has_explicit_tg4_offsets(insn)) {
+            texi->tex.useOffsets = 4;
+            setPosition(texi, false);
+            for (uint8_t i = 0; i < 4; ++i) {
+               for (uint8_t j = 0; j < 2; ++j) {
+                  texi->offset[i][j].set(loadImm(NULL, insn->tg4_offsets[i][j]));
+                  texi->offset[i][j].setInsn(texi);
+               }
+            }
+            setPosition(texi, true);
+         }
+      }
+
       if (ddxIdx != -1 && ddyIdx != -1) {
          for (uint8_t c = 0u; c < target.getDim() + target.isCube(); ++c) {
             texi->dPdx[c].set(getSrc(&insn->src[ddxIdx].src, c));

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 9d10e169d80a20b6457d7c511c4972c0592ecda4..afad48b59204918a7a6ba4a726e5468b3eb67970 100644 (file)
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -235,6 +235,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_USER_VERTEX_BUFFERS:
    case PIPE_CAP_TEXTURE_QUERY_LOD:
    case PIPE_CAP_SAMPLE_SHADING:
+   case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
    case PIPE_CAP_TEXTURE_GATHER_SM5:
    case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
    case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
@@ -299,9 +300,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
       return class_3d >= GP100_3D_CLASS;
 
-   case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
-      /* TODO: nir doesn't support tg4 with multiple offsets */
-      return screen->prefer_nir ? 0 : 1;
    /* caps has to be turned on with nir */
    case PIPE_CAP_INT64_DIVMOD:
       return screen->prefer_nir ? 1 : 0;