[RS6000] Tests that use int128_t and -m32

All these tests fail with -m32 due to lack of int128 support, in some
cases with what I thought was not the best error message.  For example
vsx_mask-move-runnable.c:34:3: error: unknown type name 'vector'
is misleading.  The problem isn't "vector" but "vector __uint128_t".

	* gcc.target/powerpc/vsx-load-element-extend-char.c: Require int128.
	* gcc.target/powerpc/vsx-load-element-extend-int.c: Likewise.
	* gcc.target/powerpc/vsx-load-element-extend-longlong.c: Likewise.
	* gcc.target/powerpc/vsx-load-element-extend-short.c: Likewise.
	* gcc.target/powerpc/vsx-store-element-truncate-char.c: Likewise.
	* gcc.target/powerpc/vsx-store-element-truncate-int.c: Likewise.
	* gcc.target/powerpc/vsx-store-element-truncate-longlong.c: Likewise.
	* gcc.target/powerpc/vsx-store-element-truncate-short.c: Likewise.
	* gcc.target/powerpc/vsx_mask-count-runnable.c: Likewise.
	* gcc.target/powerpc/vsx_mask-expand-runnable.c: Likewise.
	* gcc.target/powerpc/vsx_mask-extract-runnable.c: Likewise.
	* gcc.target/powerpc/vsx_mask-move-runnable.c: Likewise.

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
index 0b8cfd610f88603a432de8ee94f02096c6f4ffa8..58986d636e4ce907a47565aad9f10e5ebb920c91 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-char.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 /* { dg-options "-mdejagnu-cpu=power10 -O3" } */
 
 /* At the time of writing, the number of lxvrbx instructions is

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
index b10d3cb43d2f6d2560712960968bafc430018d35..366a01370044990b034d83c323dc0bbf5658d87b 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-int.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 
 /* Deliberately set optization to zero for this test to confirm
    the lxvr*x instruction is generated. At higher optimization levels

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
index 52fcf2e572f1697a2b842775fbfdb6b72e121390..8dfbc79a33d7fc2f1c879635584ceda2ac48282f 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-longlong.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 /* { dg-options "-mdejagnu-cpu=power10 -O3" } */
 
 /* At time of writing, we also geenerate a .constrprop copy

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
index 8fc0cc66eb72bdb1ef1c649a39f62a938faf8b25..87e263c864de7a3dc619f86bbdf60ca0d4beb365 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-load-element-extend-short.c
@@ -4,6 +4,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 
 /* Deliberately set optization to zero for this test to confirm
    the lxvr*x instruction is generated. At higher optimization levels

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
index 99f3904983be022f91894ab34fe8799a95c406dc..b69a1f3e291a2038e12c712eff7b54f0c94f2bd4 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-char.c
@@ -3,6 +3,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 /* Deliberately set optization to zero for this test to confirm
    the stxvr*x instruction is generated. At higher optimization levels
    the instruction we are looking for is sometimes replaced by other

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
index 6e2acf83c38367086f0ba1d43ab83db574593bee..76e09fde0683bb692985d1b462077bb4379cb8dd 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-int.c
@@ -3,6 +3,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 /* Deliberately set optization to zero for this test to confirm
    the stxvr*x instruction is generated. At higher optimization levels
    the instruction we are looking for is sometimes replaced by other

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c
index 7fce6a44d4f5487660b84a0f85b0c1cfb57b7ec8..c137ce2d19f680da18aea184c31c45de94df40bf 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-longlong.c
@@ -3,6 +3,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 
 /* Deliberately set optization to zero for this test to confirm
    the stxvr*x instruction is generated. At higher optimization levels

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c
index 17925c87732ef643b3cfa6eac0bb647496475497..7d856e7c3eb278e2c99ef0bb09e50a6a516c5df6 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx-store-element-truncate-short.c
@@ -3,6 +3,7 @@
 
 /* { dg-do compile {target power10_ok} } */
 /* { dg-do run {target power10_hw} } */
+/* { dg-require-effective-target int128 } */
 
 /* Deliberately set optization to zero for this test to confirm
    the stxvr*x instruction is generated. At higher optimization levels

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
index 5862517eae930afb5eb892c6951d53f564288556..6ac4ed2173f411a9999ec38092d0e292ed3736a3 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-count-runnable.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
 /* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor
    supports the 128-bit integer instructions. */

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
index 13b4c8afd4f22b7144113e8a88f201e0c44b569a..05fedf77eb9022f9cade496b4983bd24d27fe1b0 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-expand-runnable.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
 /* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor
    supports the 128-bit integer instructions. */

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
index d58a6b0b6822513e4ab7981db40afc9b93e41914..6e952695905d5a6955d160c591c7aeacec103dea 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-extract-runnable.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
 /* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor
    supports the 128-bit integer instructions. */

diff --git a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
index 9147d67c9d1958b5098ec71638c5b778d5da2c61..c2eb53d3bb2331ae522e1fa455c348e083d143b8 100644 (file)
--- a/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsx_mask-move-runnable.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { power10_hw } } } */
 /* { dg-do link { target { ! power10_hw } } } */
 /* { dg-options "-mcpu=power10 -O2" } */
-/* { dg-require-effective-target power10_ok } */
+/* { dg-require-effective-target { int128 && power10_ok } } */
 
 /* Check that the expected 128-bit instructions are generated if the processor
    supports the 128-bit integer instructions. */