system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 51332073 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1893392 # number cycles where commit BW limit reached
-system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 165216916 # The number of ROB reads
system.cpu0.rob.rob_writes 117798939 # The number of ROB writes
system.cpu0.timesIdled 506110 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 8615735 # Class of committed instruction
system.cpu1.commit.bw_lim_events 304379 # number cycles where commit BW limit reached
-system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 23176968 # The number of ROB reads
system.cpu1.rob.rob_writes 20704388 # The number of ROB writes
system.cpu1.timesIdled 112605 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction
system.cpu.commit.bw_lim_events 2085445 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 177593269 # The number of ROB reads
system.cpu.rob.rob_writes 130137832 # The number of ROB writes
system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 32325567 # Class of committed instruction
system.cpu2.commit.bw_lim_events 870316 # number cycles where commit BW limit reached
-system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 62726939 # The number of ROB reads
system.cpu2.rob.rob_writes 70507401 # The number of ROB writes
system.cpu2.timesIdled 178497 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction
system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 375672050 # The number of ROB reads
system.cpu.rob.rob_writes 292972268 # The number of ROB writes
system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 120715819 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1448193 # number cycles where commit BW limit reached
-system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 292184577 # The number of ROB reads
system.cpu0.rob.rob_writes 263546817 # The number of ROB writes
system.cpu0.timesIdled 122559 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 25443224 # Class of committed instruction
system.cpu1.commit.bw_lim_events 442982 # number cycles where commit BW limit reached
-system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 68115809 # The number of ROB reads
system.cpu1.rob.rob_writes 56808236 # The number of ROB writes
system.cpu1.timesIdled 67589 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction
system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 375672050 # The number of ROB reads
system.cpu.rob.rob_writes 292972268 # The number of ROB writes
system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 47174544 # Class of committed instruction
system.cpu2.commit.bw_lim_events 1230130 # number cycles where commit BW limit reached
-system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 112818862 # The number of ROB reads
system.cpu2.rob.rob_writes 112362949 # The number of ROB writes
system.cpu2.timesIdled 279332 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 68988407 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1718944 # number cycles where commit BW limit reached
-system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 167372763 # The number of ROB reads
system.cpu0.rob.rob_writes 163072923 # The number of ROB writes
system.cpu0.timesIdled 393865 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 73162446 # Class of committed instruction
system.cpu1.commit.bw_lim_events 1807529 # number cycles where commit BW limit reached
-system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 173729023 # The number of ROB reads
system.cpu1.rob.rob_writes 171875858 # The number of ROB writes
system.cpu1.timesIdled 390006 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1005211605 # Class of committed instruction
system.cpu.commit.bw_lim_events 11866014 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2555711925 # The number of ROB reads
system.cpu.rob.rob_writes 2125474325 # The number of ROB writes
system.cpu.timesIdled 8142220 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 545285068 # Class of committed instruction
system.cpu0.commit.bw_lim_events 13335148 # number cycles where commit BW limit reached
-system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 1272468420 # The number of ROB reads
system.cpu0.rob.rob_writes 1194722923 # The number of ROB writes
system.cpu0.timesIdled 998377 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 500362777 # Class of committed instruction
system.cpu1.commit.bw_lim_events 12356672 # number cycles where commit BW limit reached
-system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 1162834468 # The number of ROB reads
system.cpu1.rob.rob_writes 1096743807 # The number of ROB writes
system.cpu1.timesIdled 924876 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1005211605 # Class of committed instruction
system.cpu.commit.bw_lim_events 11866014 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2555711925 # The number of ROB reads
system.cpu.rob.rob_writes 2125474325 # The number of ROB writes
system.cpu.timesIdled 8142220 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 387615464 # Class of committed instruction
system.cpu2.commit.bw_lim_events 16778864 # number cycles where commit BW limit reached
-system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 862595097 # The number of ROB reads
system.cpu2.rob.rob_writes 905518660 # The number of ROB writes
system.cpu2.timesIdled 2960768 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 532162399 # Class of committed instruction
system.cpu0.commit.bw_lim_events 22726868 # number cycles where commit BW limit reached
-system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 1220262369 # The number of ROB reads
system.cpu0.rob.rob_writes 1241914021 # The number of ROB writes
system.cpu0.timesIdled 4040058 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 535141123 # Class of committed instruction
system.cpu1.commit.bw_lim_events 22907771 # number cycles where commit BW limit reached
-system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 1220174232 # The number of ROB reads
system.cpu1.rob.rob_writes 1248183780 # The number of ROB writes
system.cpu1.timesIdled 4134360 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 806389826 # Class of committed instruction
system.cpu.commit.bw_lim_events 5444825 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1270729806 # The number of ROB reads
system.cpu.rob.rob_writes 1664729387 # The number of ROB writes
system.cpu.timesIdled 294275 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 270578300 # Class of committed instruction
system.cpu2.commit.bw_lim_events 2129956 # number cycles where commit BW limit reached
-system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 431186663 # The number of ROB reads
system.cpu2.rob.rob_writes 561693850 # The number of ROB writes
system.cpu2.timesIdled 124283 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction
system.cpu.commit.bw_lim_events 4111371 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 217986125 # The number of ROB reads
system.cpu.rob.rob_writes 219581178 # The number of ROB writes
system.cpu.timesIdled 584 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction
system.cpu.commit.bw_lim_events 23473761 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 419820689 # The number of ROB reads
system.cpu.rob.rob_writes 657620446 # The number of ROB writes
system.cpu.timesIdled 598 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction
system.cpu.commit.bw_lim_events 13831485 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1093653497 # The number of ROB reads
system.cpu.rob.rob_writes 1334601058 # The number of ROB writes
system.cpu.timesIdled 13925 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
system.cpu.commit.bw_lim_events 76872227 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2867051516 # The number of ROB reads
system.cpu.rob.rob_writes 4304473794 # The number of ROB writes
system.cpu.timesIdled 2567 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction
system.cpu.commit.bw_lim_events 29857166 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 543683043 # The number of ROB reads
system.cpu.rob.rob_writes 885930772 # The number of ROB writes
system.cpu.timesIdled 3165 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction
system.cpu.commit.bw_lim_events 10346735 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 561599370 # The number of ROB reads
system.cpu.rob.rob_writes 705507733 # The number of ROB writes
system.cpu.timesIdled 50679 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction
system.cpu.commit.bw_lim_events 50554341 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1905392712 # The number of ROB reads
system.cpu.rob.rob_writes 3017093514 # The number of ROB writes
system.cpu.timesIdled 3164 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction
system.cpu.commit.bw_lim_events 22360483 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 1891410858 # The number of ROB reads
system.cpu.rob.rob_writes 2343104087 # The number of ROB writes
system.cpu.timesIdled 647398 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction
system.cpu.commit.bw_lim_events 5716148 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 133590014 # The number of ROB reads
system.cpu.rob.rob_writes 196617452 # The number of ROB writes
system.cpu.timesIdled 47547 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction
system.cpu.commit.bw_lim_events 3769965 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 158240550 # The number of ROB reads
system.cpu.rob.rob_writes 195514428 # The number of ROB writes
system.cpu.timesIdled 23835 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction
system.cpu.commit.bw_lim_events 106281090 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3840325519 # The number of ROB reads
system.cpu.rob.rob_writes 5790523687 # The number of ROB writes
system.cpu.timesIdled 690 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction
system.cpu.commit.bw_lim_events 58069727 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3367926925 # The number of ROB reads
system.cpu.rob.rob_writes 3883468057 # The number of ROB writes
system.cpu.timesIdled 846 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction
system.cpu.commit.bw_lim_events 6204717 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 157112780 # The number of ROB reads
system.cpu.rob.rob_writes 252206838 # The number of ROB writes
system.cpu.timesIdled 4633 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction
system.cpu.commit.bw_lim_events 3352927 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 406304779 # The number of ROB reads
system.cpu.rob.rob_writes 513839131 # The number of ROB writes
system.cpu.timesIdled 3408 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction
system.cpu.commit.bw_lim_events 6920063 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 615300578 # The number of ROB reads
system.cpu.rob.rob_writes 699132843 # The number of ROB writes
system.cpu.timesIdled 3156 # Number of times that the entire CPU went into an idle state and unscheduled itself
mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
mem_mode=atomic
mem_ranges=2147483648:2415919103
memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu0.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu0.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
[system.cpu0.tracer]
type=ExeTracer
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu1.toL2Bus.slave[5]
[system.cpu1.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu1.toL2Bus.slave[4]
[system.cpu1.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
[system.cpu1.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
mem_mode=atomic
mem_ranges=2147483648:2415919103
memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
mem_mode=timing
mem_ranges=2147483648:2415919103
memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu0.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu0.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
[system.cpu0.tracer]
type=ExeTracer
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu1.toL2Bus.slave[5]
[system.cpu1.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu1.toL2Bus.slave[4]
[system.cpu1.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
[system.cpu1.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
mem_mode=timing
mem_ranges=2147483648:2415919103
memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
mem_mode=atomic
mem_ranges=2147483648:2415919103
memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
[system.vncserver]
type=VncServer
mem_mode=atomic
mem_ranges=2147483648:2415919103
memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu0.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu0.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
[system.cpu0.tracer]
type=ExeTracer
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu1.toL2Bus.slave[5]
[system.cpu1.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu1.toL2Bus.slave[4]
[system.cpu1.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
[system.cpu1.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
mem_mode=atomic
mem_ranges=2147483648:2415919103
memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
mem_mode=timing
mem_ranges=2147483648:2415919103
memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu0.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu0.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu0.l2cache.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
[system.cpu0.tracer]
type=ExeTracer
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu1.toL2Bus.slave[5]
[system.cpu1.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu1.toL2Bus.slave[4]
[system.cpu1.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu1.l2cache.cpu_side
-slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
[system.cpu1.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
mem_mode=timing
mem_ranges=2147483648:2415919103
memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/projects/pd/randd/dist/binaries/boot_emm.arm64
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
boot_release_addr=65528
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/projects/pd/randd/dist/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.aarch64.20140821
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
machine_type=VExpress_EMM64
mem_mode=atomic
mem_ranges=2147483648:2415919103
-memories=system.realview.nvmem system.physmem system.realview.vram
+memories=system.physmem system.realview.nvmem system.realview.vram
+mmap_using_noreserve=false
multi_proc=true
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/work/gem5.latest/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/projects/pd/randd/dist/disks/linaro-minimal-aarch64.img
+image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.dtb
[system.cpu0.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[5]
[system.cpu0.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu0.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu0.itb
[system.cpu0.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[4]
[system.cpu0.itb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.dtb
[system.cpu1.dstage2_mmu.stage2_tlb]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu1.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu1.itb
[system.cpu1.istage2_mmu.stage2_tlb]
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=system.realview.pciconfig.pio
master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma
addr_ranges=2147483648:2415919103
assoc=8
clk_domain=system.clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=false
hit_latency=50
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.local_cpu_timer.pio system.realview.vgic.pio system.physmem.port
slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.iocache.mem_side
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
-slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
[system.vncserver]
type=VncServer
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
kernel_addr_check=true
load_addr_mask=18446744073709551615
load_offset=0
mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
-readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=false
-width=8
+width=16
default=system.pc.pciconfig.pio
master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port
slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
kernel_addr_check=true
load_addr_mask=18446744073709551615
load_offset=0
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
-readfile=/usr/local/google/home/gabeblack/gem5/hg/gem5/tests/halt.sh
+readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=false
-width=8
+width=16
default=system.pc.pciconfig.pio
master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist1.pio system.pc.i_dont_exist2.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
children=badaddr_responder
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port
slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
mem_mode=atomic
mem_ranges=0:134217727
memories=drivesys.physmem
+mmap_using_noreserve=false
num_work_ids=16
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=/scratch/nilay/GEM5/gem5/configs/boot/netperf-server.rcS
type=NoncoherentXBar
clk_domain=drivesys.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=drivesys.tsunami.pciconfig.pio
master=drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ide.config drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.iobridge.slave
slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.dma
children=badaddr_responder
clk_domain=drivesys.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=drivesys
use_default_range=false
-width=8
+width=16
default=drivesys.membus.badaddr_responder.pio
master=drivesys.bridge.slave drivesys.physmem.port
slave=drivesys.system_port drivesys.cpu.icache_port drivesys.cpu.dcache_port drivesys.iobridge.master
dma_write_delay=0
dma_write_factor=0
eventq_index=0
-hardware_address=00:90:00:00:00:02
+hardware_address=00:90:00:00:00:01
intr_delay=10000000
pci_bus=0
pci_dev=1
mem_mode=atomic
mem_ranges=0:134217727
memories=testsys.physmem
+mmap_using_noreserve=false
num_work_ids=16
pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=/scratch/nilay/GEM5/gem5/configs/boot/netperf-stream-client.rcS
type=NoncoherentXBar
clk_domain=testsys.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=true
-width=8
+width=16
default=testsys.tsunami.pciconfig.pio
master=testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ide.config testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.iobridge.slave
slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma
children=badaddr_responder
clk_domain=testsys.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=testsys
use_default_range=false
-width=8
+width=16
default=testsys.membus.badaddr_responder.pio
master=testsys.bridge.slave testsys.physmem.port
slave=testsys.system_port testsys.cpu.icache_port testsys.cpu.dcache_port testsys.iobridge.master
dma_write_delay=0
dma_write_factor=0
eventq_index=0
-hardware_address=00:90:00:00:00:01
+hardware_address=00:90:00:00:00:02
intr_delay=10000000
pci_bus=0
pci_dev=1
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 6389 # Class of committed instruction
system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 25491 # The number of ROB reads
system.cpu.rob.rob_writes 27316 # The number of ROB writes
system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself
mem_mode=atomic
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu.clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu.clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu.clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu.clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu.clk_domain
dcache=system.ruby.l1_cntrl0.cacheMemory
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 2576 # Class of committed instruction
system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 11659 # The number of ROB reads
system.cpu.rob.rob_writes 10686 # The number of ROB writes
system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself
mem_mode=atomic
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu.clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu.clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu.clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu.clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu.clk_domain
dcache=system.ruby.l1_cntrl0.cacheMemory
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.checker.dtb
[system.cpu.checker.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[9]
[system.cpu.checker.dtb]
type=ArmTLB
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[7]
+port=system.cpu.toL2Bus.slave[5]
[system.cpu.checker.isa]
type=ArmISA
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.checker.istage2_mmu]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.checker.itb
[system.cpu.checker.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[8]
[system.cpu.checker.itb]
type=ArmTLB
is_stage2=false
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[6]
+port=system.cpu.toL2Bus.slave[4]
[system.cpu.checker.tracer]
type=ExeTracer
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port system.cpu.checker.istage2_mmu.stage2_tlb.walker.port system.cpu.checker.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5377 # Class of committed instruction
system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 22770 # The number of ROB reads
system.cpu.rob.rob_writes 21679 # The number of ROB writes
system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=1
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=16
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=12
[system.cpu.l2cache.prefetcher]
type=StridePrefetcher
+cache_snoop=false
clk_domain=system.cpu_clk_domain
-cross_pages=false
-data_accesses_only=false
degree=8
eventq_index=0
-inst_tagged=true
latency=1
-on_miss_only=false
-on_prefetch=true
-on_read_only=false
-serial_squash=false
-size=100
+max_conf=7
+min_conf=0
+on_data=true
+on_inst=true
+on_miss=false
+on_read=true
+on_write=true
+queue_filter=true
+queue_size=32
+queue_squash=true
+start_conf=4
sys=system
+table_assoc=4
+table_sets=16
+tag_prefetch=true
+thresh_conf=4
use_master_id=true
[system.cpu.l2cache.tags]
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5377 # Class of committed instruction
system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 22696 # The number of ROB reads
system.cpu.rob.rob_writes 16433 # The number of ROB writes
system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
mem_mode=atomic
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.checker.dtb
[system.cpu.checker.dstage2_mmu.stage2_tlb]
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.checker.istage2_mmu]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.checker.itb
[system.cpu.checker.istage2_mmu.stage2_tlb]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.membus.slave[6]
[system.cpu.dtb]
type=ArmTLB
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.membus.slave[5]
[system.cpu.itb]
type=ArmTLB
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=SimpleMemory
mem_mode=atomic
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.membus.slave[6]
[system.cpu.dtb]
type=ArmTLB
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.membus.slave[5]
[system.cpu.itb]
type=ArmTLB
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
-slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=SimpleMemory
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.dtb
[system.cpu.dstage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[5]
[system.cpu.dtb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
id_pfr0=49
id_pfr1=4113
midr=1091551472
+pmu=Null
system=system
[system.cpu.istage2_mmu]
children=stage2_tlb
eventq_index=0
stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
+sys=system
tlb=system.cpu.itb
[system.cpu.istage2_mmu.stage2_tlb]
is_stage2=true
num_squash_per_cycle=2
sys=system
-port=system.cpu.toL2Bus.slave[4]
[system.cpu.itb]
type=ArmTLB
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5623 # Class of committed instruction
system.cpu.commit.bw_lim_events 103 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 23990 # The number of ROB reads
system.cpu.rob.rob_writes 21831 # The number of ROB writes
system.cpu.timesIdled 267 # Number of times that the entire CPU went into an idle state and unscheduled itself
mem_mode=atomic
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu.clk_domain
dcache=system.ruby.l1_cntrl0.cacheMemory
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 5792 # Class of committed instruction
system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 22278 # The number of ROB reads
system.cpu.rob.rob_writes 21482 # The number of ROB writes
system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
mem_mode=atomic
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
mem_mode=atomic
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu.clk_domain
dcache=system.ruby.l1_cntrl0.cacheMemory
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 9747 # Class of committed instruction
system.cpu.commit.bw_lim_events 259 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 43058 # The number of ROB reads
system.cpu.rob.rob_writes 44876 # The number of ROB writes
system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself
mem_mode=atomic
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu.clk_domain
dcache=system.ruby.l1_cntrl0.cacheMemory
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=LiveProcess
cmd=hello
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
system.cpu.commit.op_class_1::total 6389 # Class of committed instruction
system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction
system.cpu.commit.bw_lim_events 325 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits
-system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits
-system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 130940 # The number of ROB reads
system.cpu.rob.rob_writes 58397 # The number of ROB writes
system.cpu.timesIdled 389 # Number of times that the entire CPU went into an idle state and unscheduled itself
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=LiveProcess
cmd=insttest
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 15162 # Class of committed instruction
system.cpu.commit.bw_lim_events 272 # number cycles where commit BW limit reached
-system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 54715 # The number of ROB reads
system.cpu.rob.rob_writes 52974 # The number of ROB writes
system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself
mem_mode=atomic
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=LiveProcess
cmd=insttest
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
width=32
type=LiveProcess
cmd=insttest
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.l2c.mem_side
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 450384 # Class of committed instruction
system.cpu0.commit.bw_lim_events 494 # number cycles where commit BW limit reached
-system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu0.rob.rob_reads 649458 # The number of ROB reads
system.cpu0.rob.rob_writes 931043 # The number of ROB writes
system.cpu0.timesIdled 314 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 251602 # Class of committed instruction
system.cpu1.commit.bw_lim_events 1312 # number cycles where commit BW limit reached
-system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu1.rob.rob_reads 417798 # The number of ROB reads
system.cpu1.rob.rob_writes 534614 # The number of ROB writes
system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 246921 # Class of committed instruction
system.cpu2.commit.bw_lim_events 1310 # number cycles where commit BW limit reached
-system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 416888 # The number of ROB reads
system.cpu2.rob.rob_writes 525783 # The number of ROB writes
system.cpu2.timesIdled 205 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::total 238347 # Class of committed instruction
system.cpu3.commit.bw_lim_events 1300 # number cycles where commit BW limit reached
-system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu3.rob.rob_reads 408052 # The number of ROB reads
system.cpu3.rob.rob_writes 507784 # The number of ROB writes
system.cpu3.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself
mem_mode=atomic
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
type=LiveProcess
cmd=test_atomic 4
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.l2c.mem_side
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
type=LiveProcess
cmd=test_atomic 4
cwd=
+drivers=
egid=100
env=
errout=cerr
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
+kvmInSE=false
max_stack_size=67108864
output=cout
pid=100
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
-width=8
+width=16
master=system.physmem.port
slave=system.system_port system.l2c.mem_side
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=8
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
[system]
type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem mem_ctrls ruby sys_port_proxy voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
-memories=system.funcmem system.mem_ctrls
+memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
[system.cpu0]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.ruby.l1_cntrl0.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.cpu1]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.ruby.l1_cntrl1.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl1.sequencer.slave[0]
[system.cpu2]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.ruby.l1_cntrl2.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl2.sequencer.slave[0]
[system.cpu3]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.ruby.l1_cntrl3.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl3.sequencer.slave[0]
[system.cpu4]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.ruby.l1_cntrl4.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl4.sequencer.slave[0]
[system.cpu5]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.ruby.l1_cntrl5.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl5.sequencer.slave[0]
[system.cpu6]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.ruby.l1_cntrl6.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl6.sequencer.slave[0]
[system.cpu7]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.ruby.l1_cntrl7.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl7.sequencer.slave[0]
[system.cpu_clk_domain]
type=SrcClockDomain
sys_clk_domain=system.clk_domain
transition_latency=100000
-[system.funcbus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-port=system.funcbus.master[0]
-
[system.mem_ctrls]
type=DRAMCtrl
IDD0=0.075000
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=0
-slave=system.cpu0.test
+slave=system.cpu0.port
[system.ruby.l1_cntrl1]
type=L1Cache_Controller
[system.ruby.l1_cntrl1.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl1.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=1
-slave=system.cpu1.test
+slave=system.cpu1.port
[system.ruby.l1_cntrl2]
type=L1Cache_Controller
[system.ruby.l1_cntrl2.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl2.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=2
-slave=system.cpu2.test
+slave=system.cpu2.port
[system.ruby.l1_cntrl3]
type=L1Cache_Controller
[system.ruby.l1_cntrl3.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl3.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=3
-slave=system.cpu3.test
+slave=system.cpu3.port
[system.ruby.l1_cntrl4]
type=L1Cache_Controller
[system.ruby.l1_cntrl4.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl4.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=4
-slave=system.cpu4.test
+slave=system.cpu4.port
[system.ruby.l1_cntrl5]
type=L1Cache_Controller
[system.ruby.l1_cntrl5.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl5.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=5
-slave=system.cpu5.test
+slave=system.cpu5.port
[system.ruby.l1_cntrl6]
type=L1Cache_Controller
[system.ruby.l1_cntrl6.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl6.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=6
-slave=system.cpu6.test
+slave=system.cpu6.port
[system.ruby.l1_cntrl7]
type=L1Cache_Controller
[system.ruby.l1_cntrl7.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl7.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=7
-slave=system.cpu7.test
+slave=system.cpu7.port
[system.ruby.l2_cntrl0]
type=L2Cache_Controller
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
[system]
type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem mem_ctrls ruby sys_port_proxy voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
-memories=system.funcmem system.mem_ctrls
+memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
[system.cpu0]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.ruby.l1_cntrl0.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.cpu1]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.ruby.l1_cntrl1.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl1.sequencer.slave[0]
[system.cpu2]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.ruby.l1_cntrl2.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl2.sequencer.slave[0]
[system.cpu3]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.ruby.l1_cntrl3.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl3.sequencer.slave[0]
[system.cpu4]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.ruby.l1_cntrl4.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl4.sequencer.slave[0]
[system.cpu5]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.ruby.l1_cntrl5.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl5.sequencer.slave[0]
[system.cpu6]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.ruby.l1_cntrl6.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl6.sequencer.slave[0]
[system.cpu7]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.ruby.l1_cntrl7.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl7.sequencer.slave[0]
[system.cpu_clk_domain]
type=SrcClockDomain
sys_clk_domain=system.clk_domain
transition_latency=100000
-[system.funcbus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-port=system.funcbus.master[0]
-
[system.mem_ctrls]
type=DRAMCtrl
IDD0=0.075000
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=0
-slave=system.cpu0.test
+slave=system.cpu0.port
[system.ruby.l1_cntrl1]
type=L1Cache_Controller
[system.ruby.l1_cntrl1.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl1.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=1
-slave=system.cpu1.test
+slave=system.cpu1.port
[system.ruby.l1_cntrl2]
type=L1Cache_Controller
[system.ruby.l1_cntrl2.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl2.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=2
-slave=system.cpu2.test
+slave=system.cpu2.port
[system.ruby.l1_cntrl3]
type=L1Cache_Controller
[system.ruby.l1_cntrl3.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl3.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=3
-slave=system.cpu3.test
+slave=system.cpu3.port
[system.ruby.l1_cntrl4]
type=L1Cache_Controller
[system.ruby.l1_cntrl4.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl4.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=4
-slave=system.cpu4.test
+slave=system.cpu4.port
[system.ruby.l1_cntrl5]
type=L1Cache_Controller
[system.ruby.l1_cntrl5.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl5.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=5
-slave=system.cpu5.test
+slave=system.cpu5.port
[system.ruby.l1_cntrl6]
type=L1Cache_Controller
[system.ruby.l1_cntrl6.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl6.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=6
-slave=system.cpu6.test
+slave=system.cpu6.port
[system.ruby.l1_cntrl7]
type=L1Cache_Controller
[system.ruby.l1_cntrl7.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl7.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=7
-slave=system.cpu7.test
+slave=system.cpu7.port
[system.ruby.l2_cntrl0]
type=L2Cache_Controller
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
[system]
type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem mem_ctrls ruby sys_port_proxy voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
-memories=system.funcmem system.mem_ctrls
+memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
[system.cpu0]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.ruby.l1_cntrl0.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.cpu1]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.ruby.l1_cntrl1.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl1.sequencer.slave[0]
[system.cpu2]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.ruby.l1_cntrl2.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl2.sequencer.slave[0]
[system.cpu3]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.ruby.l1_cntrl3.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl3.sequencer.slave[0]
[system.cpu4]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.ruby.l1_cntrl4.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl4.sequencer.slave[0]
[system.cpu5]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.ruby.l1_cntrl5.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl5.sequencer.slave[0]
[system.cpu6]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.ruby.l1_cntrl6.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl6.sequencer.slave[0]
[system.cpu7]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.ruby.l1_cntrl7.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl7.sequencer.slave[0]
[system.cpu_clk_domain]
type=SrcClockDomain
sys_clk_domain=system.clk_domain
transition_latency=100000
-[system.funcbus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-port=system.funcbus.master[0]
-
[system.mem_ctrls]
type=DRAMCtrl
IDD0=0.075000
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=0
-slave=system.cpu0.test
+slave=system.cpu0.port
[system.ruby.l1_cntrl1]
type=L1Cache_Controller
[system.ruby.l1_cntrl1.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl1.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=1
-slave=system.cpu1.test
+slave=system.cpu1.port
[system.ruby.l1_cntrl2]
type=L1Cache_Controller
[system.ruby.l1_cntrl2.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl2.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=2
-slave=system.cpu2.test
+slave=system.cpu2.port
[system.ruby.l1_cntrl3]
type=L1Cache_Controller
[system.ruby.l1_cntrl3.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl3.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=3
-slave=system.cpu3.test
+slave=system.cpu3.port
[system.ruby.l1_cntrl4]
type=L1Cache_Controller
[system.ruby.l1_cntrl4.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl4.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=4
-slave=system.cpu4.test
+slave=system.cpu4.port
[system.ruby.l1_cntrl5]
type=L1Cache_Controller
[system.ruby.l1_cntrl5.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl5.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=5
-slave=system.cpu5.test
+slave=system.cpu5.port
[system.ruby.l1_cntrl6]
type=L1Cache_Controller
[system.ruby.l1_cntrl6.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl6.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=6
-slave=system.cpu6.test
+slave=system.cpu6.port
[system.ruby.l1_cntrl7]
type=L1Cache_Controller
[system.ruby.l1_cntrl7.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl7.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=7
-slave=system.cpu7.test
+slave=system.cpu7.port
[system.ruby.l2_cntrl0]
type=L2Cache_Controller
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
[system]
type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem mem_ctrls ruby sys_port_proxy voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
-memories=system.mem_ctrls system.funcmem
+memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
[system.cpu0]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.ruby.l1_cntrl0.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.cpu1]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.ruby.l1_cntrl1.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl1.sequencer.slave[0]
[system.cpu2]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.ruby.l1_cntrl2.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl2.sequencer.slave[0]
[system.cpu3]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.ruby.l1_cntrl3.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl3.sequencer.slave[0]
[system.cpu4]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.ruby.l1_cntrl4.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl4.sequencer.slave[0]
[system.cpu5]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.ruby.l1_cntrl5.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl5.sequencer.slave[0]
[system.cpu6]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.ruby.l1_cntrl6.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl6.sequencer.slave[0]
[system.cpu7]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.ruby.l1_cntrl7.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl7.sequencer.slave[0]
[system.cpu_clk_domain]
type=SrcClockDomain
sys_clk_domain=system.clk_domain
transition_latency=100000
-[system.funcbus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-port=system.funcbus.master[0]
-
[system.mem_ctrls]
type=DRAMCtrl
IDD0=0.075000
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=0
-slave=system.cpu0.test
+slave=system.cpu0.port
[system.ruby.l1_cntrl1]
type=L1Cache_Controller
[system.ruby.l1_cntrl1.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl1.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=1
-slave=system.cpu1.test
+slave=system.cpu1.port
[system.ruby.l1_cntrl2]
type=L1Cache_Controller
[system.ruby.l1_cntrl2.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl2.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=2
-slave=system.cpu2.test
+slave=system.cpu2.port
[system.ruby.l1_cntrl3]
type=L1Cache_Controller
[system.ruby.l1_cntrl3.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl3.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=3
-slave=system.cpu3.test
+slave=system.cpu3.port
[system.ruby.l1_cntrl4]
type=L1Cache_Controller
[system.ruby.l1_cntrl4.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl4.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=4
-slave=system.cpu4.test
+slave=system.cpu4.port
[system.ruby.l1_cntrl5]
type=L1Cache_Controller
[system.ruby.l1_cntrl5.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl5.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=5
-slave=system.cpu5.test
+slave=system.cpu5.port
[system.ruby.l1_cntrl6]
type=L1Cache_Controller
[system.ruby.l1_cntrl6.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl6.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=6
-slave=system.cpu6.test
+slave=system.cpu6.port
[system.ruby.l1_cntrl7]
type=L1Cache_Controller
[system.ruby.l1_cntrl7.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl7.L1Dcache
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=7
-slave=system.cpu7.test
+slave=system.cpu7.port
[system.ruby.memctrl_clk_domain]
type=DerivedClockDomain
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
[system]
type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem mem_ctrls ruby sys_port_proxy voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler mem_ctrls ruby sys_port_proxy voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
load_offset=0
mem_mode=timing
mem_ranges=0:268435455
-memories=system.mem_ctrls system.funcmem
+memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
[system.cpu0]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.ruby.l1_cntrl0.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl0.sequencer.slave[0]
[system.cpu1]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.ruby.l1_cntrl1.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl1.sequencer.slave[0]
[system.cpu2]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.ruby.l1_cntrl2.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl2.sequencer.slave[0]
[system.cpu3]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.ruby.l1_cntrl3.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl3.sequencer.slave[0]
[system.cpu4]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.ruby.l1_cntrl4.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl4.sequencer.slave[0]
[system.cpu5]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.ruby.l1_cntrl5.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl5.sequencer.slave[0]
[system.cpu6]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.ruby.l1_cntrl6.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl6.sequencer.slave[0]
[system.cpu7]
type=MemTest
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=0
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=true
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.ruby.l1_cntrl7.sequencer.slave[0]
+system=system
+port=system.ruby.l1_cntrl7.sequencer.slave[0]
[system.cpu_clk_domain]
type=SrcClockDomain
sys_clk_domain=system.clk_domain
transition_latency=100000
-[system.funcbus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=0.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30
-latency_var=0
-null=false
-range=0:134217727
-port=system.funcbus.master[0]
-
[system.mem_ctrls]
type=DRAMCtrl
IDD0=0.075000
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl0.cacheMemory
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=0
-slave=system.cpu0.test
+slave=system.cpu0.port
[system.ruby.l1_cntrl1]
type=L1Cache_Controller
[system.ruby.l1_cntrl1.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl1.cacheMemory
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=1
-slave=system.cpu1.test
+slave=system.cpu1.port
[system.ruby.l1_cntrl2]
type=L1Cache_Controller
[system.ruby.l1_cntrl2.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl2.cacheMemory
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=2
-slave=system.cpu2.test
+slave=system.cpu2.port
[system.ruby.l1_cntrl3]
type=L1Cache_Controller
[system.ruby.l1_cntrl3.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl3.cacheMemory
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=3
-slave=system.cpu3.test
+slave=system.cpu3.port
[system.ruby.l1_cntrl4]
type=L1Cache_Controller
[system.ruby.l1_cntrl4.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl4.cacheMemory
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=4
-slave=system.cpu4.test
+slave=system.cpu4.port
[system.ruby.l1_cntrl5]
type=L1Cache_Controller
[system.ruby.l1_cntrl5.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl5.cacheMemory
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=5
-slave=system.cpu5.test
+slave=system.cpu5.port
[system.ruby.l1_cntrl6]
type=L1Cache_Controller
[system.ruby.l1_cntrl6.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl6.cacheMemory
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=6
-slave=system.cpu6.test
+slave=system.cpu6.port
[system.ruby.l1_cntrl7]
type=L1Cache_Controller
[system.ruby.l1_cntrl7.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.cpu_clk_domain
dcache=system.ruby.l1_cntrl7.cacheMemory
deadlock_threshold=1000000
using_network_tester=false
using_ruby_tester=false
version=7
-slave=system.cpu7.test
+slave=system.cpu7.port
[system.ruby.memctrl_clk_domain]
type=DerivedClockDomain
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
[system]
type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem l2c membus physmem toL2Bus voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
load_offset=0
mem_mode=timing
mem_ranges=
-memories=system.physmem system.funcmem
+memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
[system.cpu0]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.cpu0.l1c.cpu_side
+system=system
+port=system.cpu0.l1c.cpu_side
[system.cpu0.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu0.test
+cpu_side=system.cpu0.port
mem_side=system.toL2Bus.slave[0]
[system.cpu0.l1c.tags]
[system.cpu1]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.cpu1.l1c.cpu_side
+system=system
+port=system.cpu1.l1c.cpu_side
[system.cpu1.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu1.test
+cpu_side=system.cpu1.port
mem_side=system.toL2Bus.slave[1]
[system.cpu1.l1c.tags]
[system.cpu2]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.cpu2.l1c.cpu_side
+system=system
+port=system.cpu2.l1c.cpu_side
[system.cpu2.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu2.test
+cpu_side=system.cpu2.port
mem_side=system.toL2Bus.slave[2]
[system.cpu2.l1c.tags]
[system.cpu3]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.cpu3.l1c.cpu_side
+system=system
+port=system.cpu3.l1c.cpu_side
[system.cpu3.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu3.test
+cpu_side=system.cpu3.port
mem_side=system.toL2Bus.slave[3]
[system.cpu3.l1c.tags]
[system.cpu4]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.cpu4.l1c.cpu_side
+system=system
+port=system.cpu4.l1c.cpu_side
[system.cpu4.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu4.test
+cpu_side=system.cpu4.port
mem_side=system.toL2Bus.slave[4]
[system.cpu4.l1c.tags]
[system.cpu5]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.cpu5.l1c.cpu_side
+system=system
+port=system.cpu5.l1c.cpu_side
[system.cpu5.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu5.test
+cpu_side=system.cpu5.port
mem_side=system.toL2Bus.slave[5]
[system.cpu5.l1c.tags]
[system.cpu6]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.cpu6.l1c.cpu_side
+system=system
+port=system.cpu6.l1c.cpu_side
[system.cpu6.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu6.test
+cpu_side=system.cpu6.port
mem_side=system.toL2Bus.slave[6]
[system.cpu6.l1c.tags]
[system.cpu7]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.cpu7.l1c.cpu_side
+system=system
+port=system.cpu7.l1c.cpu_side
[system.cpu7.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu7.test
+cpu_side=system.cpu7.port
mem_side=system.toL2Bus.slave[7]
[system.cpu7.l1c.tags]
sys_clk_domain=system.clk_domain
transition_latency=100000000
-[system.funcbus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.funcbus.master[0]
-
[system.l2c]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
children=snoop_filter
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=system.membus.snoop_filter
+snoop_response_latency=4
system=system
use_default_range=false
width=16
[system.membus.snoop_filter]
type=SnoopFilter
eventq_index=0
-lookup_latency=3
+lookup_latency=1
system=system
[system.physmem]
children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=system.toL2Bus.snoop_filter
+snoop_response_latency=1
system=system
use_default_range=false
-width=16
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
[system.toL2Bus.snoop_filter]
type=SnoopFilter
eventq_index=0
-lookup_latency=3
+lookup_latency=1
system=system
[system.voltage_domain]
[system]
type=System
-children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler funcbus funcmem l2c membus physmem toL2Bus voltage_domain
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
load_offset=0
mem_mode=timing
mem_ranges=
-memories=system.physmem system.funcmem
+memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
[system.cpu0]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[0]
-test=system.cpu0.l1c.cpu_side
+system=system
+port=system.cpu0.l1c.cpu_side
[system.cpu0.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu0.test
+cpu_side=system.cpu0.port
mem_side=system.toL2Bus.slave[0]
[system.cpu0.l1c.tags]
[system.cpu1]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[1]
-test=system.cpu1.l1c.cpu_side
+system=system
+port=system.cpu1.l1c.cpu_side
[system.cpu1.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu1.test
+cpu_side=system.cpu1.port
mem_side=system.toL2Bus.slave[1]
[system.cpu1.l1c.tags]
[system.cpu2]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[2]
-test=system.cpu2.l1c.cpu_side
+system=system
+port=system.cpu2.l1c.cpu_side
[system.cpu2.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu2.test
+cpu_side=system.cpu2.port
mem_side=system.toL2Bus.slave[2]
[system.cpu2.l1c.tags]
[system.cpu3]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[3]
-test=system.cpu3.l1c.cpu_side
+system=system
+port=system.cpu3.l1c.cpu_side
[system.cpu3.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu3.test
+cpu_side=system.cpu3.port
mem_side=system.toL2Bus.slave[3]
[system.cpu3.l1c.tags]
[system.cpu4]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[4]
-test=system.cpu4.l1c.cpu_side
+system=system
+port=system.cpu4.l1c.cpu_side
[system.cpu4.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu4.test
+cpu_side=system.cpu4.port
mem_side=system.toL2Bus.slave[4]
[system.cpu4.l1c.tags]
[system.cpu5]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[5]
-test=system.cpu5.l1c.cpu_side
+system=system
+port=system.cpu5.l1c.cpu_side
[system.cpu5.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu5.test
+cpu_side=system.cpu5.port
mem_side=system.toL2Bus.slave[5]
[system.cpu5.l1c.tags]
[system.cpu6]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[6]
-test=system.cpu6.l1c.cpu_side
+system=system
+port=system.cpu6.l1c.cpu_side
[system.cpu6.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu6.test
+cpu_side=system.cpu6.port
mem_side=system.toL2Bus.slave[6]
[system.cpu6.l1c.tags]
[system.cpu7]
type=MemTest
children=l1c
-atomic=false
clk_domain=system.cpu_clk_domain
eventq_index=0
-issue_dmas=false
+interval=1
max_loads=100000
-memory_size=65536
-percent_dest_unaligned=50
percent_functional=50
percent_reads=65
-percent_source_unaligned=50
percent_uncacheable=10
+progress_check=5000000
progress_interval=10000
+size=65536
suppress_func_warnings=false
-sys=system
-trace_addr=0
-functional=system.funcbus.slave[7]
-test=system.cpu7.l1c.cpu_side
+system=system
+port=system.cpu7.l1c.cpu_side
[system.cpu7.l1c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=2
tgts_per_mshr=20
two_queue=false
write_buffers=8
-cpu_side=system.cpu7.test
+cpu_side=system.cpu7.port
mem_side=system.toL2Bus.slave[7]
[system.cpu7.l1c.tags]
sys_clk_domain=system.clk_domain
transition_latency=100000000
-[system.funcbus]
-type=NoncoherentXBar
-clk_domain=system.clk_domain
-eventq_index=0
-header_cycles=1
-use_default_range=false
-width=8
-master=system.funcmem.port
-slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
-
-[system.funcmem]
-type=SimpleMemory
-bandwidth=73.000000
-clk_domain=system.clk_domain
-conf_table_reported=true
-eventq_index=0
-in_addr_map=false
-latency=30000
-latency_var=0
-null=false
-range=0:134217727
-port=system.funcbus.master[0]
-
[system.l2c]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
+demand_mshr_reserve=1
eventq_index=0
forward_snoops=true
hit_latency=20
type=CoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=4
+frontend_latency=3
+response_latency=2
snoop_filter=Null
+snoop_response_latency=4
system=system
use_default_range=false
width=16
type=CoherentXBar
clk_domain=system.cpu_clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=0
+frontend_latency=1
+response_latency=1
snoop_filter=Null
+snoop_response_latency=1
system=system
use_default_range=false
-width=16
+width=32
master=system.l2c.cpu_side
slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.ruby.clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.ruby.clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 l2_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.ruby.clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.ruby.clk_domain
dcache=system.ruby.l1_cntrl0.L1Dcache
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=0:268435455
memories=system.mem_ctrls
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
[system.ruby]
type=RubySystem
children=clk_domain dir_cntrl0 l1_cntrl0 memctrl_clk_domain network
+access_backing_store=false
all_instructions=false
block_size_bytes=64
clk_domain=system.ruby.clk_domain
[system.ruby.l1_cntrl0.sequencer]
type=RubySequencer
-access_backing_store=false
clk_domain=system.ruby.clk_domain
dcache=system.ruby.l1_cntrl0.cacheMemory
deadlock_threshold=500000
[system.sys_port_proxy]
type=RubyPortProxy
-access_backing_store=false
clk_domain=system.clk_domain
eventq_index=0
ruby_system=system.ruby
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=false
width=16
master=system.physmem.port
outstanding_bins=20
read_addr_mask=18446744073709551615
sample_period=1000000000
+stack_dist_calc=Null
system=system
trace_compress=true
trace_enable=false
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=false
width=16
master=system.physmem.port
[system.monitor]
type=CommMonitor
+children=stack_dist_calc
bandwidth_bins=20
burst_length_bins=20
clk_domain=system.clk_domain
outstanding_bins=20
read_addr_mask=18446744073709551615
sample_period=1000000000
+stack_dist_calc=system.monitor.stack_dist_calc
system=system
trace_compress=true
trace_enable=true
master=system.membus.slave[0]
slave=system.cpu.port
+[system.monitor.stack_dist_calc]
+type=StackDistCalc
+disable_linear_hists=false
+disable_log_hists=false
+eventq_index=0
+linear_hist_bins=16
+log_hist_bins=32
+verify=true
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
projects / gem5.git / commitdiff