Merge remote-tracking branch 'origin/eddie/fix1115' into xc7mux

diff --cc CHANGELOG
index b9582fd63140fac8a6b4da6dbe8d93ab0290ec12,496a521be6cf6221d454a5e22f45918b0b7ec882..1ab1bc4f20ac69b806fbfd0153f53055be92b741
--- 1/CHANGELOG
--- 2/CHANGELOG
+++ b/CHANGELOG
@@@ -17,14 -17,9 +17,15 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "rename -src"
      - Added "equiv_opt" pass
      - Added "read_aiger" frontend
 +    - Added "shregmap -tech xilinx"
 +    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 +    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 +    - Added "synth_xilinx -abc9" (experimental)
 +    - Added "synth_ice40 -abc9" (experimental)
      - Extended "muxcover -mux{4,8,16}=<cost>"
 -    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
+     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
 +    - Added "synth -abc9" (experimental)
 +    - "synth_xilinx" to now infer wide multiplexers (-nomux to disable)
  
  
  Yosys 0.7 .. Yosys 0.8

diff --cc kernel/rtlil.cc
Simple merge