Tick
CommMonitor::recvAtomic(PacketPtr pkt)
{
- ppPktReq->notify(pkt);
+ ProbePoints::PacketInfo req_pkt_info(pkt);
+ ppPktReq->notify(req_pkt_info);
const Tick delay(masterPort.sendAtomic(pkt));
assert(pkt->isResponse());
- ppPktResp->notify(pkt);
+ ProbePoints::PacketInfo resp_pkt_info(pkt);
+ ppPktResp->notify(resp_pkt_info);
return delay;
}
// Store relevant fields of packet, because packet may be modified
// or even deleted when sendTiming() is called.
+ const ProbePoints::PacketInfo pkt_info(pkt);
+
const bool is_read = pkt->isRead();
const bool is_write = pkt->isWrite();
- const MemCmd cmd = pkt->cmd;
- const unsigned size = pkt->getSize();
- const Addr addr = pkt->getAddr();
const bool expects_response(
pkt->needsResponse() && !pkt->memInhibitAsserted());
}
if (successful) {
- // The receiver might already have modified the packet. We
- // want to give the probe access to the original packet, which
- // means we need to fake the original packet by temporarily
- // restoring the command.
- const MemCmd response_cmd(pkt->cmd);
- pkt->cmd = cmd;
- ppPktReq->notify(pkt);
- pkt->cmd = response_cmd;
+ ppPktReq->notify(pkt_info);
}
if (successful && is_read) {
// Get sample of burst length
if (!stats.disableBurstLengthHists) {
- stats.readBurstLengthHist.sample(size);
+ stats.readBurstLengthHist.sample(pkt_info.size);
}
// Sample the masked address
if (!stats.disableAddrDists) {
- stats.readAddrDist.sample(addr & readAddrMask);
+ stats.readAddrDist.sample(pkt_info.addr & readAddrMask);
}
// If it needs a response increment number of outstanding read
}
if (!stats.disableBurstLengthHists) {
- stats.writeBurstLengthHist.sample(size);
+ stats.writeBurstLengthHist.sample(pkt_info.size);
}
// Update the bandwidth stats on the request
if (!stats.disableBandwidthHists) {
- stats.writtenBytes += size;
- stats.totalWrittenBytes += size;
+ stats.writtenBytes += pkt_info.size;
+ stats.totalWrittenBytes += pkt_info.size;
}
// Sample the masked write address
if (!stats.disableAddrDists) {
- stats.writeAddrDist.sample(addr & writeAddrMask);
+ stats.writeAddrDist.sample(pkt_info.addr & writeAddrMask);
}
if (!stats.disableOutstandingHists && expects_response) {
// Store relevant fields of packet, because packet may be modified
// or even deleted when sendTiming() is called.
+ const ProbePoints::PacketInfo pkt_info(pkt);
+
bool is_read = pkt->isRead();
bool is_write = pkt->isWrite();
- unsigned size = pkt->getSize();
Tick latency = 0;
CommMonitorSenderState* received_state =
dynamic_cast<CommMonitorSenderState*>(pkt->senderState);
}
if (successful) {
- assert(pkt->isResponse());
- ppPktResp->notify(pkt);
+ ppPktResp->notify(pkt_info);
}
if (successful && is_read) {
// Update the bandwidth stats based on responses for reads
if (!stats.disableBandwidthHists) {
- stats.readBytes += size;
- stats.totalReadBytes += size;
+ stats.readBytes += pkt_info.size;
+ stats.totalReadBytes += pkt_info.size;
}
} else if (successful && is_write) {
#include <memory>
#include <vector>
-#include "mem/packet.hh"
-#include "sim/probe/probe.hh"
+#include "sim/probe/mem.hh"
#include "sim/sim_object.hh"
struct BaseMemProbeParams;
/**
* Callback to analyse intercepted Packets.
*/
- virtual void handleRequest(const PacketPtr &pkt) = 0;
+ virtual void handleRequest(const ProbePoints::PacketInfo &pkt_info) = 0;
private:
- class PacketListener : public ProbeListenerArgBase<PacketPtr>
+ class PacketListener : public ProbeListenerArgBase<ProbePoints::PacketInfo>
{
public:
PacketListener(BaseMemProbe &_parent,
: ProbeListenerArgBase(pm, name),
parent(_parent) {}
- void notify(const PacketPtr &pkt) M5_ATTR_OVERRIDE {
- parent.handleRequest(pkt);
+ void notify(const ProbePoints::PacketInfo &pkt_info) M5_ATTR_OVERRIDE {
+ parent.handleRequest(pkt_info);
}
protected:
}
void
-StackDistProbe::handleRequest(const PacketPtr &pkt)
+StackDistProbe::handleRequest(const ProbePoints::PacketInfo &pkt_info)
{
// only capturing read and write requests (which allocate in the
// cache)
- if (!pkt->isRead() && !pkt->isWrite())
+ if (!pkt_info.cmd.isRead() && !pkt_info.cmd.isWrite())
return;
// Align the address to a cache line size
- const Addr aligned_addr(roundDown(pkt->getAddr(), lineSize));
+ const Addr aligned_addr(roundDown(pkt_info.addr, lineSize));
// Calculate the stack distance
const uint64_t sd(calc.calcStackDistAndUpdate(aligned_addr).first);
// Sample the stack distance of the address in linear bins
if (!disableLinearHists) {
- if (pkt->isRead())
+ if (pkt_info.cmd.isRead())
readLinearHist.sample(sd);
else
writeLinearHist.sample(sd);
int sd_lg2 = sd == 0 ? 1 : floorLog2(sd);
// Sample the stack distance of the address in log bins
- if (pkt->isRead())
+ if (pkt_info.cmd.isRead())
readLogHist.sample(sd_lg2);
else
writeLogHist.sample(sd_lg2);