Clean up pseudo-private member usage in `passes/sat/freduce.cc`.

diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index f29631639baece20f765c2dd2e68d9d1fca53462..7dfc1765fc76fd3bdc6fc43179b9d8ea291a5793 100644 (file)
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -614,29 +614,29 @@ struct FreduceWorker
 
                int bits_full_total = 0;
                std::vector<std::set<RTLIL::SigBit>> batches;
-               for (auto &it : module->wires_)
-                       if (it.second->port_input) {
-                               batches.push_back(sigmap(it.second).to_sigbit_set());
-                               bits_full_total += it.second->width;
+               for (auto w : module->wires())
+                       if (w->port_input) {
+                               batches.push_back(sigmap(w).to_sigbit_set());
+                               bits_full_total += w->width;
                        }
-               for (auto &it : module->cells_) {
-                       if (ct.cell_known(it.second->type)) {
+               for (auto cell : module->cells()) {
+                       if (ct.cell_known(cell->type)) {
                                std::set<RTLIL::SigBit> inputs, outputs;
-                               for (auto &port : it.second->connections()) {
+                               for (auto &port : cell->connections()) {
                                        std::vector<RTLIL::SigBit> bits = sigmap(port.second).to_sigbit_vector();
-                                       if (ct.cell_output(it.second->type, port.first))
+                                       if (ct.cell_output(cell->type, port.first))
                                                outputs.insert(bits.begin(), bits.end());
                                        else
                                                inputs.insert(bits.begin(), bits.end());
                                }
-                               std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(it.second, inputs);
+                               std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>> drv(cell, inputs);
                                for (auto &bit : outputs)
                                        drivers[bit] = drv;
                                batches.push_back(outputs);
                                bits_full_total += outputs.size();
                        }
-                       if (inv_mode && it.second->type == "$_NOT_")
-                               inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(it.second->getPort("\\A")), sigmap(it.second->getPort("\\Y"))));
+                       if (inv_mode && cell->type == "$_NOT_")
+                               inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort("\\A")), sigmap(cell->getPort("\\Y"))));
                }
 
                int bits_count = 0;
@@ -828,8 +828,7 @@ struct FreducePass : public Pass {
                extra_args(args, argidx, design);
 
                int bitcount = 0;
-               for (auto &mod_it : design->modules_) {
-                       RTLIL::Module *module = mod_it.second;
+               for (auto module : design->modules()) {
                        if (design->selected(module))
                                bitcount += FreduceWorker(design, module).run();
                }