fhdl: list signals in execution order

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 307bf65726d87391972b1e0acfb5adc5e315dfdf..6b77840b30d1fe96461aa925ac2df0dda4f7e756 100644 (file)
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -154,6 +154,7 @@ def _cst(x):
                return x
 
 class Signal(Value):
+       _counter = 0
        def __init__(self, bv=BV(), name=None, variable=False, reset=0, name_override=None):
                assert(isinstance(bv, BV))
                self.bv = bv
@@ -161,7 +162,9 @@ class Signal(Value):
                self.reset = Constant(reset, bv)
                self.name_override = name_override
                self.backtrace = tracer.trace_back(name)
-       
+               self.order = Signal._counter
+               Signal._counter += 1
+
        def __len__(self):
                return self.bv.width
 

diff --git a/migen/fhdl/tools.py b/migen/fhdl/tools.py
index 90ec62e525ba04435fce4b0c5c638289507b8c8a..ebecf2bbf5ddc3c6b2fdb7daa28ddb1eaa061d8b 100644 (file)
--- a/migen/fhdl/tools.py
+++ b/migen/fhdl/tools.py
@@ -130,7 +130,7 @@ def is_variable(node):
 
 def insert_reset(rst, sl):
        targets = list_targets(sl)
-       resetcode = [t.eq(t.reset) for t in targets]
+       resetcode = [t.eq(t.reset) for t in sorted(targets, key=lambda x: x.order)]
        return If(rst, *resetcode).Else(*sl)
 
 def value_bv(v):

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 034ac2c6e9a8235815f9b7216903f9b688a0d870..8993300e8be00c597b76a895b55b5b06b8217e80 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -110,7 +110,7 @@ def _printheader(f, ios, name, ns):
        wires = _list_comb_wires(f) | inst_mem_outs
        r = "module " + name + "(\n"
        firstp = True
-       for sig in ios:
+       for sig in sorted(ios, key=lambda x: x.order):
                if not firstp:
                        r += ",\n"
                firstp = False
@@ -124,7 +124,7 @@ def _printheader(f, ios, name, ns):
                else:
                        r += "\tinput " + _printsig(ns, sig)
        r += "\n);\n\n"
-       for sig in sigs - ios:
+       for sig in sorted(sigs - ios, key=lambda x: x.order):
                if sig in wires:
                        r += "wire " + _printsig(ns, sig) + ";\n"
                else:
@@ -238,7 +238,7 @@ def _printinit(f, ios, ns):
                - list_mem_ios(f, False, True)
        if signals:
                r += "initial begin\n"
-               for s in signals:
+               for s in sorted(signals, key=lambda x: x.order):
                        r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset) + ";\n"
                r += "end\n\n"
        return r