add spike_sv page

diff --git a/3d_gpu/spike_sv.mdwn b/3d_gpu/spike_sv.mdwn
new file mode 100644 (file)
index 0000000..bc74cd9
--- /dev/null
+++ b/3d_gpu/spike_sv.mdwn
@@ -0,0 +1,11 @@
+# Simple-V Spike emulator
+
+Needs riscv-tools, first
+
+* git clone https://git.libre-riscv.org/git/riscv-isa-sim.git
+* cd risc-v-isa-sim
+* git checkout -b sv
+* cd ..
+* git clone https://git.libre-riscv.org/git/riscv-tests.git
+* cd risc-tests
+* git checkout -b sv

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index c70a86acc7cadc0b4c1788f76aadc08cbc7e9b1b..f14039d298a76184a70832d29d3b231ea7b7dc49 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -731,6 +731,12 @@ scalar RV LOAD operation:
         srcbase = ireg[rs+i];
         return mem[srcbase + imm];
 
+Whilst LOAD and STORE remain as-is when compared to their scalar
+counterparts, the incrementing on the source register (for LOAD)
+means that pointers-to-structures can be easily implemented, and
+if contiguous offsets are required, those pointers (the contents
+of the contiguous source registers) may simply be set up to point
+to contiguous locations.  
 
 ## Compressed Stack LOAD / STORE Instructions
 
@@ -759,8 +765,8 @@ that must be incremented.  Pseudo-code follows:
         if (int_csr[rd].isvec) j++;
 
 For C.LDSP, the offset (and loop) multiplier would be 8, and for
-C.LQSP it would be 16.  Effectively this is a Vector "Unit Stride"
-Load instruction.
+C.LQSP it would be 16.  Effectively this makes C.LWSP etc. a Vector
+"Unit Stride" Load instruction.
 
 **Note**: It is critical for implementors and compiler writers to note that
 the **real** target register, x2, is predicated.  Ordinarily (with all