+2002-01-22 Graydon Hoare <graydon@redhat.com>
+
+ * cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure.
+ (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field.
+
2002-01-21 Thomas Klausner <wiz@danbala.ifoer.tuwien.ac.at>
* h8300.h: Comment typo fix.
/* "nil" indicator for the operand instance table */
#define CGEN_OPERAND_NIL CGEN_OPERAND_MAX
+/* A tree of these structs represents the multi-ifield
+ structure of an operand's hw-index value, if it exists. */
+
+struct cgen_ifld;
+
+typedef struct cgen_maybe_multi_ifield
+{
+ int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry);
+ n: indexed by array of more cgen_maybe_multi_ifields. */
+ union
+ {
+ struct cgen_maybe_multi_ifield * multi;
+ struct cgen_ifld * leaf;
+ } val;
+}
+CGEN_MAYBE_MULTI_IFLD;
+
/* This struct defines each entry in the operand table. */
typedef struct
May be unused for a modifier. */
unsigned char length;
+ /* The (possibly-multi) ifield used as an index for this operand, if it
+ is indexed by a field at all. This substitutes / extends the start and
+ length fields above, but unsure at this time whether they are used
+ anywhere. */
+ CGEN_MAYBE_MULTI_IFLD index_fields;
#if 0 /* ??? Interesting idea but relocs tend to get too complicated,
and ABI dependent, for simple table lookups to work. */
/* Ideally this would be the internal (external?) reloc type. */
+2002-01-22 Graydon Hoare <graydon@redhat.com>
+
+ * fr30-asm.c: Regenerate.
+ * fr30-desc.c: Likewise.
+ * fr30-desc.h: Likewise.
+ * fr30-dis.c: Likewise.
+ * fr30-ibld.c: Likewise.
+ * fr30-opc.c: Likewise.
+ * fr30-opc.h: Likewise.
+ * m32r-asm.c: Likewise.
+ * m32r-desc.c: Likewise.
+ * m32r-desc.h: Likewise.
+ * m32r-dis.c: Likewise.
+ * m32r-ibld.c: Likewise.
+ * m32r-opc.c: Likewise.
+ * m32r-opc.h: Likewise.
+ * m32r-opinst.c: Likewise.
+ * openrisc-asm.c: Likewise.
+ * openrisc-desc.c: Likewise.
+ * openrisc-desc.h: Likewise.
+ * openrisc-dis.c: Likewise.
+ * openrisc-ibld.c: Likewise.
+ * openrisc-opc.c: Likewise.
+ * openrisc-opc.h: Likewise.
+ * xstormy16-desc.c: Likewise.
+
2002-01-22 Richard Henderson <rth@redhat.com>
* alpha-dis.c (print_insn_alpha): Also mask the base opcode for
This function could be moved into `parse_insn_normal', but keeping it
separate makes clear the interface between `parse_insn_normal' and each of
- the handlers.
-*/
+ the handlers. */
const char *
fr30_cgen_parse_operand (cd, opindex, strp, fields)
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
#undef A
+
+/* multi ifield declarations */
+
+const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [];
+
+
+/* multi ifield definitions */
+
+const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] =
+{
+ { 0, &(fr30_cgen_ifld_table[23]) },
+ { 0, &(fr30_cgen_ifld_table[24]) },
+ {0,0}
+};
+
/* The operand table. */
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
{
/* pc: program counter */
{ "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
+ { 0, &(fr30_cgen_ifld_table[0]) },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* Ri: destination register */
{ "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
+ { 0, &(fr30_cgen_ifld_table[10]) },
{ 0, { (1<<MACH_BASE) } } },
/* Rj: source register */
{ "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
+ { 0, &(fr30_cgen_ifld_table[9]) },
{ 0, { (1<<MACH_BASE) } } },
/* Ric: target register coproc insn */
{ "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
+ { 0, &(fr30_cgen_ifld_table[14]) },
{ 0, { (1<<MACH_BASE) } } },
/* Rjc: source register coproc insn */
{ "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
+ { 0, &(fr30_cgen_ifld_table[13]) },
{ 0, { (1<<MACH_BASE) } } },
/* CRi: coprocessor register */
{ "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
+ { 0, &(fr30_cgen_ifld_table[16]) },
{ 0, { (1<<MACH_BASE) } } },
/* CRj: coprocessor register */
{ "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
+ { 0, &(fr30_cgen_ifld_table[15]) },
{ 0, { (1<<MACH_BASE) } } },
/* Rs1: dedicated register */
{ "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
+ { 0, &(fr30_cgen_ifld_table[11]) },
{ 0, { (1<<MACH_BASE) } } },
/* Rs2: dedicated register */
{ "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
+ { 0, &(fr30_cgen_ifld_table[12]) },
{ 0, { (1<<MACH_BASE) } } },
/* R13: General Register 13 */
{ "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
+ { 0, 0 },
{ 0, { (1<<MACH_BASE) } } },
/* R14: General Register 14 */
{ "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
+ { 0, 0 },
{ 0, { (1<<MACH_BASE) } } },
/* R15: General Register 15 */
{ "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
+ { 0, 0 },
{ 0, { (1<<MACH_BASE) } } },
/* ps: Program Status register */
{ "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
+ { 0, 0 },
{ 0, { (1<<MACH_BASE) } } },
/* u4: 4 bit unsigned immediate */
{ "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
+ { 0, &(fr30_cgen_ifld_table[17]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u4c: 4 bit unsigned immediate */
{ "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
+ { 0, &(fr30_cgen_ifld_table[18]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u8: 8 bit unsigned immediate */
{ "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
+ { 0, &(fr30_cgen_ifld_table[21]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* i8: 8 bit unsigned immediate */
{ "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
+ { 0, &(fr30_cgen_ifld_table[22]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* udisp6: 6 bit unsigned immediate */
{ "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
+ { 0, &(fr30_cgen_ifld_table[26]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* disp8: 8 bit signed immediate */
{ "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
+ { 0, &(fr30_cgen_ifld_table[27]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* disp9: 9 bit signed immediate */
{ "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
+ { 0, &(fr30_cgen_ifld_table[28]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* disp10: 10 bit signed immediate */
{ "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
+ { 0, &(fr30_cgen_ifld_table[29]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* s10: 10 bit signed immediate */
{ "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
+ { 0, &(fr30_cgen_ifld_table[30]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* u10: 10 bit unsigned immediate */
{ "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
+ { 0, &(fr30_cgen_ifld_table[31]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* i32: 32 bit immediate */
{ "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
+ { 0, &(fr30_cgen_ifld_table[25]) },
{ 0|A(HASH_PREFIX)|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* m4: 4 bit negative immediate */
{ "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
+ { 0, &(fr30_cgen_ifld_table[20]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* i20: 20 bit immediate */
{ "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
+ { 2, &(FR30_F_I20_MULTI_IFIELD[0]) },
{ 0|A(HASH_PREFIX)|A(VIRTUAL), { (1<<MACH_BASE) } } },
/* dir8: 8 bit direct address */
{ "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
+ { 0, &(fr30_cgen_ifld_table[33]) },
{ 0, { (1<<MACH_BASE) } } },
/* dir9: 9 bit direct address */
{ "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
+ { 0, &(fr30_cgen_ifld_table[34]) },
{ 0, { (1<<MACH_BASE) } } },
/* dir10: 10 bit direct address */
{ "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
+ { 0, &(fr30_cgen_ifld_table[35]) },
{ 0, { (1<<MACH_BASE) } } },
/* label9: 9 bit pc relative address */
{ "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
+ { 0, &(fr30_cgen_ifld_table[32]) },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* label12: 12 bit pc relative address */
{ "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
+ { 0, &(fr30_cgen_ifld_table[36]) },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* reglist_low_ld: 8 bit low register mask for ldm */
{ "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
+ { 0, &(fr30_cgen_ifld_table[40]) },
{ 0, { (1<<MACH_BASE) } } },
/* reglist_hi_ld: 8 bit high register mask for ldm */
{ "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
+ { 0, &(fr30_cgen_ifld_table[39]) },
{ 0, { (1<<MACH_BASE) } } },
/* reglist_low_st: 8 bit low register mask for stm */
{ "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
+ { 0, &(fr30_cgen_ifld_table[38]) },
{ 0, { (1<<MACH_BASE) } } },
/* reglist_hi_st: 8 bit high register mask for stm */
{ "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
+ { 0, &(fr30_cgen_ifld_table[37]) },
{ 0, { (1<<MACH_BASE) } } },
/* cc: condition codes */
{ "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
+ { 0, &(fr30_cgen_ifld_table[7]) },
{ 0, { (1<<MACH_BASE) } } },
/* ccc: coprocessor calc */
{ "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
+ { 0, &(fr30_cgen_ifld_table[8]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* nbit: negative bit */
{ "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* vbit: overflow bit */
{ "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* zbit: zero bit */
{ "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* cbit: carry bit */
{ "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* ibit: interrupt bit */
{ "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* sbit: stack bit */
{ "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* tbit: trace trap bit */
{ "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* d0bit: division 0 bit */
{ "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* d1bit: division 1 bit */
{ "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* ccr: condition code bits */
{ "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* scr: system condition bits */
{ "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* ilm: interrupt level mask */
{ "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, {0, {0}} }
};
{
const CGEN_ISA *isa = & fr30_cgen_isa_table[i];
- /* Default insn sizes of all selected isas must be equal or we set
- the result to 0, meaning "unknown". */
+ /* Default insn sizes of all selected isas must be
+ equal or we set the result to 0, meaning "unknown". */
if (cd->default_insn_bitsize == UNSET)
cd->default_insn_bitsize = isa->default_insn_bitsize;
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
else
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
- /* Base insn sizes of all selected isas must be equal or we set
- the result to 0, meaning "unknown". */
+ /* Base insn sizes of all selected isas must be equal
+ or we set the result to 0, meaning "unknown". */
if (cd->base_insn_bitsize == UNSET)
cd->base_insn_bitsize = isa->base_insn_bitsize;
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
static void
print_hi_register_list_ld (cd, dis_info, value, attrs, pc, length)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
- unsigned int attrs;
- bfd_vma pc;
- int length;
+ unsigned int attrs ATTRIBUTE_UNUSED;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+ int length ATTRIBUTE_UNUSED;
{
print_register_list (dis_info, value, 8, 0/*load*/);
}
static void
print_low_register_list_ld (cd, dis_info, value, attrs, pc, length)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
- unsigned int attrs;
- bfd_vma pc;
- int length;
+ unsigned int attrs ATTRIBUTE_UNUSED;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+ int length ATTRIBUTE_UNUSED;
{
print_register_list (dis_info, value, 0, 0/*load*/);
}
static void
print_hi_register_list_st (cd, dis_info, value, attrs, pc, length)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
- unsigned int attrs;
- bfd_vma pc;
- int length;
+ unsigned int attrs ATTRIBUTE_UNUSED;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+ int length ATTRIBUTE_UNUSED;
{
print_register_list (dis_info, value, 8, 1/*store*/);
}
static void
print_low_register_list_st (cd, dis_info, value, attrs, pc, length)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
- unsigned int attrs;
- bfd_vma pc;
- int length;
+ unsigned int attrs ATTRIBUTE_UNUSED;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+ int length ATTRIBUTE_UNUSED;
{
print_register_list (dis_info, value, 0, 1/*store*/);
}
static void
print_m4 (cd, dis_info, value, attrs, pc, length)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
long value;
- unsigned int attrs;
- bfd_vma pc;
- int length;
+ unsigned int attrs ATTRIBUTE_UNUSED;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+ int length ATTRIBUTE_UNUSED;
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "%ld", value);
This function could be moved into `print_insn_normal', but keeping it
separate makes clear the interface between `print_insn_normal' and each of
- the handlers.
-*/
+ the handlers. */
void
fr30_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
This function could be moved into `parse_insn_normal', but keeping it
separate makes clear the interface between `parse_insn_normal' and each of
the handlers. It's also needed by GAS to insert operands that couldn't be
- resolved during parsing.
-*/
+ resolved during parsing. */
const char *
fr30_cgen_insert_operand (cd, opindex, fields, buffer, pc)
This function could be moved into `print_insn_normal', but keeping it
separate makes clear the interface between `print_insn_normal' and each of
- the handlers.
-*/
+ the handlers. */
int
fr30_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
This function could be moved into `parse_insn_normal', but keeping it
separate makes clear the interface between `parse_insn_normal' and each of
- the handlers.
-*/
+ the handlers. */
const char *
m32r_cgen_parse_operand (cd, opindex, strp, fields)
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
#undef A
+
+/* multi ifield declarations */
+
+
+
+/* multi ifield definitions */
+
+
/* The operand table. */
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
{
/* pc: program counter */
{ "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
+ { 0, &(m32r_cgen_ifld_table[0]) },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* sr: source register */
{ "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
+ { 0, &(m32r_cgen_ifld_table[6]) },
{ 0, { (1<<MACH_BASE) } } },
/* dr: destination register */
{ "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
+ { 0, &(m32r_cgen_ifld_table[5]) },
{ 0, { (1<<MACH_BASE) } } },
/* src1: source register 1 */
{ "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
+ { 0, &(m32r_cgen_ifld_table[5]) },
{ 0, { (1<<MACH_BASE) } } },
/* src2: source register 2 */
{ "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
+ { 0, &(m32r_cgen_ifld_table[6]) },
{ 0, { (1<<MACH_BASE) } } },
/* scr: source control register */
{ "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
+ { 0, &(m32r_cgen_ifld_table[6]) },
{ 0, { (1<<MACH_BASE) } } },
/* dcr: destination control register */
{ "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
+ { 0, &(m32r_cgen_ifld_table[5]) },
{ 0, { (1<<MACH_BASE) } } },
/* simm8: 8 bit signed immediate */
{ "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
+ { 0, &(m32r_cgen_ifld_table[7]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* simm16: 16 bit signed immediate */
{ "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
+ { 0, &(m32r_cgen_ifld_table[8]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm4: 4 bit trap number */
{ "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
+ { 0, &(m32r_cgen_ifld_table[10]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm5: 5 bit shift count */
{ "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
+ { 0, &(m32r_cgen_ifld_table[11]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm16: 16 bit unsigned immediate */
{ "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
+ { 0, &(m32r_cgen_ifld_table[12]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* imm1: 1 bit immediate */
{ "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
+ { 0, &(m32r_cgen_ifld_table[25]) },
{ 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } } },
/* accd: accumulator destination register */
{ "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
+ { 0, &(m32r_cgen_ifld_table[22]) },
{ 0, { (1<<MACH_M32RX) } } },
/* accs: accumulator source register */
{ "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
+ { 0, &(m32r_cgen_ifld_table[21]) },
{ 0, { (1<<MACH_M32RX) } } },
/* acc: accumulator reg (d) */
{ "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
+ { 0, &(m32r_cgen_ifld_table[20]) },
{ 0, { (1<<MACH_M32RX) } } },
/* hash: # prefix */
{ "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
+ { 0, 0 },
{ 0, { (1<<MACH_BASE) } } },
/* hi16: high 16 bit immediate, sign optional */
{ "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
+ { 0, &(m32r_cgen_ifld_table[14]) },
{ 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* slo16: 16 bit signed immediate, for low() */
{ "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
+ { 0, &(m32r_cgen_ifld_table[8]) },
{ 0, { (1<<MACH_BASE) } } },
/* ulo16: 16 bit unsigned immediate, for low() */
{ "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
+ { 0, &(m32r_cgen_ifld_table[12]) },
{ 0, { (1<<MACH_BASE) } } },
/* uimm24: 24 bit address */
{ "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
+ { 0, &(m32r_cgen_ifld_table[13]) },
{ 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
/* disp8: 8 bit displacement */
{ "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
+ { 0, &(m32r_cgen_ifld_table[15]) },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* disp16: 16 bit displacement */
{ "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
+ { 0, &(m32r_cgen_ifld_table[16]) },
{ 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* disp24: 24 bit displacement */
{ "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
+ { 0, &(m32r_cgen_ifld_table[17]) },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* condbit: condition bit */
{ "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* accum: accumulator */
{ "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, {0, {0}} }
};
{
const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
- /* Default insn sizes of all selected isas must be equal or we set
- the result to 0, meaning "unknown". */
+ /* Default insn sizes of all selected isas must be
+ equal or we set the result to 0, meaning "unknown". */
if (cd->default_insn_bitsize == UNSET)
cd->default_insn_bitsize = isa->default_insn_bitsize;
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
else
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
- /* Base insn sizes of all selected isas must be equal or we set
- the result to 0, meaning "unknown". */
+ /* Base insn sizes of all selected isas must be equal
+ or we set the result to 0, meaning "unknown". */
if (cd->base_insn_bitsize == UNSET)
cd->base_insn_bitsize = isa->base_insn_bitsize;
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
static void
print_hash (cd, dis_info, value, attrs, pc, length)
- CGEN_CPU_DESC cd;
+ CGEN_CPU_DESC cd ATTRIBUTE_UNUSED;
PTR dis_info;
- long value;
- unsigned int attrs;
- bfd_vma pc;
- int length;
+ long value ATTRIBUTE_UNUSED;
+ unsigned int attrs ATTRIBUTE_UNUSED;
+ bfd_vma pc ATTRIBUTE_UNUSED;
+ int length ATTRIBUTE_UNUSED;
{
disassemble_info *info = (disassemble_info *) dis_info;
(*info->fprintf_func) (info->stream, "#");
This function could be moved into `print_insn_normal', but keeping it
separate makes clear the interface between `print_insn_normal' and each of
- the handlers.
-*/
+ the handlers. */
void
m32r_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
This function could be moved into `parse_insn_normal', but keeping it
separate makes clear the interface between `parse_insn_normal' and each of
the handlers. It's also needed by GAS to insert operands that couldn't be
- resolved during parsing.
-*/
+ resolved during parsing. */
const char *
m32r_cgen_insert_operand (cd, opindex, fields, buffer, pc)
This function could be moved into `print_insn_normal', but keeping it
separate makes clear the interface between `print_insn_normal' and each of
- the handlers.
-*/
+ the handlers. */
int
m32r_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
/* -- opc.h */
-#undef CGEN_DIS_HASH_SIZE
+#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 256
-#undef CGEN_DIS_HASH
+#undef CGEN_DIS_HASH
#define X(b) (((unsigned char *) (b))[0] & 0xf0)
#define CGEN_DIS_HASH(buffer, value) \
(X (buffer) | \
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
This function could be moved into `parse_insn_normal', but keeping it
separate makes clear the interface between `parse_insn_normal' and each of
- the handlers.
-*/
+ the handlers. */
const char *
openrisc_cgen_parse_operand (cd, opindex, strp, fields)
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
#undef A
+
+/* multi ifield declarations */
+
+const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [];
+
+
+/* multi ifield definitions */
+
+const CGEN_MAYBE_MULTI_IFLD OPENRISC_F_I16NC_MULTI_IFIELD [] =
+{
+ { 0, &(openrisc_cgen_ifld_table[19]) },
+ { 0, &(openrisc_cgen_ifld_table[20]) },
+ {0,0}
+};
+
/* The operand table. */
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
{
/* pc: program counter */
{ "pc", OPENRISC_OPERAND_PC, HW_H_PC, 0, 0,
+ { 0, &(openrisc_cgen_ifld_table[0]) },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* sr: special register */
{ "sr", OPENRISC_OPERAND_SR, HW_H_SR, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* cbit: condition bit */
{ "cbit", OPENRISC_OPERAND_CBIT, HW_H_CBIT, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* simm-16: 16 bit signed immediate */
{ "simm-16", OPENRISC_OPERAND_SIMM_16, HW_H_SINT, 15, 16,
+ { 0, &(openrisc_cgen_ifld_table[7]) },
{ 0, { (1<<MACH_BASE) } } },
/* uimm-16: 16 bit unsigned immediate */
{ "uimm-16", OPENRISC_OPERAND_UIMM_16, HW_H_UINT, 15, 16,
+ { 0, &(openrisc_cgen_ifld_table[8]) },
{ 0, { (1<<MACH_BASE) } } },
/* disp-26: pc-rel 26 bit */
{ "disp-26", OPENRISC_OPERAND_DISP_26, HW_H_IADDR, 25, 26,
+ { 0, &(openrisc_cgen_ifld_table[21]) },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* abs-26: abs 26 bit */
{ "abs-26", OPENRISC_OPERAND_ABS_26, HW_H_IADDR, 25, 26,
+ { 0, &(openrisc_cgen_ifld_table[22]) },
{ 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
/* uimm-5: imm5 */
{ "uimm-5", OPENRISC_OPERAND_UIMM_5, HW_H_UINT, 4, 5,
+ { 0, &(openrisc_cgen_ifld_table[9]) },
{ 0, { (1<<MACH_BASE) } } },
/* rD: destination register */
{ "rD", OPENRISC_OPERAND_RD, HW_H_GR, 25, 5,
+ { 0, &(openrisc_cgen_ifld_table[4]) },
{ 0, { (1<<MACH_BASE) } } },
/* rA: source register A */
{ "rA", OPENRISC_OPERAND_RA, HW_H_GR, 20, 5,
+ { 0, &(openrisc_cgen_ifld_table[5]) },
{ 0, { (1<<MACH_BASE) } } },
/* rB: source register B */
{ "rB", OPENRISC_OPERAND_RB, HW_H_GR, 15, 5,
+ { 0, &(openrisc_cgen_ifld_table[6]) },
{ 0, { (1<<MACH_BASE) } } },
/* op-f-23: f-op23 */
{ "op-f-23", OPENRISC_OPERAND_OP_F_23, HW_H_UINT, 23, 3,
+ { 0, &(openrisc_cgen_ifld_table[15]) },
{ 0, { (1<<MACH_BASE) } } },
/* op-f-3: f-op3 */
{ "op-f-3", OPENRISC_OPERAND_OP_F_3, HW_H_UINT, 25, 5,
+ { 0, &(openrisc_cgen_ifld_table[16]) },
{ 0, { (1<<MACH_BASE) } } },
/* hi16: high 16 bit immediate, sign optional */
{ "hi16", OPENRISC_OPERAND_HI16, HW_H_HI16, 15, 16,
+ { 0, &(openrisc_cgen_ifld_table[7]) },
{ 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* lo16: low 16 bit immediate, sign optional */
{ "lo16", OPENRISC_OPERAND_LO16, HW_H_LO16, 15, 16,
+ { 0, &(openrisc_cgen_ifld_table[11]) },
{ 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* ui16nc: 16 bit immediate, sign optional */
{ "ui16nc", OPENRISC_OPERAND_UI16NC, HW_H_LO16, 10, 16,
+ { 2, &(OPENRISC_F_I16NC_MULTI_IFIELD[0]) },
{ 0|A(SIGN_OPT)|A(VIRTUAL), { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, {0, {0}} }
};
{
const CGEN_ISA *isa = & openrisc_cgen_isa_table[i];
- /* Default insn sizes of all selected isas must be equal or we set
- the result to 0, meaning "unknown". */
+ /* Default insn sizes of all selected isas must be
+ equal or we set the result to 0, meaning "unknown". */
if (cd->default_insn_bitsize == UNSET)
cd->default_insn_bitsize = isa->default_insn_bitsize;
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
else
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
- /* Base insn sizes of all selected isas must be equal or we set
- the result to 0, meaning "unknown". */
+ /* Base insn sizes of all selected isas must be equal
+ or we set the result to 0, meaning "unknown". */
if (cd->base_insn_bitsize == UNSET)
cd->base_insn_bitsize = isa->base_insn_bitsize;
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
This function could be moved into `print_insn_normal', but keeping it
separate makes clear the interface between `print_insn_normal' and each of
- the handlers.
-*/
+ the handlers. */
void
openrisc_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
This function could be moved into `parse_insn_normal', but keeping it
separate makes clear the interface between `parse_insn_normal' and each of
the handlers. It's also needed by GAS to insert operands that couldn't be
- resolved during parsing.
-*/
+ resolved during parsing. */
const char *
openrisc_cgen_insert_operand (cd, opindex, fields, buffer, pc)
This function could be moved into `print_insn_normal', but keeping it
separate makes clear the interface between `print_insn_normal' and each of
- the handlers.
-*/
+ the handlers. */
int
openrisc_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
#undef A
+
+/* multi ifield declarations */
+
+const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [];
+
+
+/* multi ifield definitions */
+
+const CGEN_MAYBE_MULTI_IFLD XSTORMY16_F_ABS24_MULTI_IFIELD [] =
+{
+ { 0, &(xstormy16_cgen_ifld_table[34]) },
+ { 0, &(xstormy16_cgen_ifld_table[35]) },
+ {0,0}
+};
+
/* The operand table. */
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
{
/* pc: program counter */
{ "pc", XSTORMY16_OPERAND_PC, HW_H_PC, 0, 0,
+ { 0, &(xstormy16_cgen_ifld_table[0]) },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psw-z8: */
{ "psw-z8", XSTORMY16_OPERAND_PSW_Z8, HW_H_Z8, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psw-z16: */
{ "psw-z16", XSTORMY16_OPERAND_PSW_Z16, HW_H_Z16, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psw-cy: */
{ "psw-cy", XSTORMY16_OPERAND_PSW_CY, HW_H_CY, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psw-hc: */
{ "psw-hc", XSTORMY16_OPERAND_PSW_HC, HW_H_HC, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psw-ov: */
{ "psw-ov", XSTORMY16_OPERAND_PSW_OV, HW_H_OV, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psw-pt: */
{ "psw-pt", XSTORMY16_OPERAND_PSW_PT, HW_H_PT, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* psw-s: */
{ "psw-s", XSTORMY16_OPERAND_PSW_S, HW_H_S, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* Rd: general register destination */
{ "Rd", XSTORMY16_OPERAND_RD, HW_H_GR, 12, 4,
+ { 0, &(xstormy16_cgen_ifld_table[2]) },
{ 0, { (1<<MACH_BASE) } } },
/* Rdm: general register destination */
{ "Rdm", XSTORMY16_OPERAND_RDM, HW_H_GR, 13, 3,
+ { 0, &(xstormy16_cgen_ifld_table[3]) },
{ 0, { (1<<MACH_BASE) } } },
/* Rm: general register for memory */
{ "Rm", XSTORMY16_OPERAND_RM, HW_H_GR, 4, 3,
+ { 0, &(xstormy16_cgen_ifld_table[4]) },
{ 0, { (1<<MACH_BASE) } } },
/* Rs: general register source */
{ "Rs", XSTORMY16_OPERAND_RS, HW_H_GR, 8, 4,
+ { 0, &(xstormy16_cgen_ifld_table[5]) },
{ 0, { (1<<MACH_BASE) } } },
/* Rb: base register */
{ "Rb", XSTORMY16_OPERAND_RB, HW_H_RB, 17, 3,
+ { 0, &(xstormy16_cgen_ifld_table[6]) },
{ 0, { (1<<MACH_BASE) } } },
/* Rbj: base register for jump */
{ "Rbj", XSTORMY16_OPERAND_RBJ, HW_H_RBJ, 11, 1,
+ { 0, &(xstormy16_cgen_ifld_table[7]) },
{ 0, { (1<<MACH_BASE) } } },
/* bcond2: branch condition opcode */
{ "bcond2", XSTORMY16_OPERAND_BCOND2, HW_H_BRANCHCOND, 4, 4,
+ { 0, &(xstormy16_cgen_ifld_table[9]) },
{ 0, { (1<<MACH_BASE) } } },
/* ws2: word size opcode */
{ "ws2", XSTORMY16_OPERAND_WS2, HW_H_WORDSIZE, 7, 1,
+ { 0, &(xstormy16_cgen_ifld_table[11]) },
{ 0, { (1<<MACH_BASE) } } },
/* bcond5: branch condition opcode */
{ "bcond5", XSTORMY16_OPERAND_BCOND5, HW_H_BRANCHCOND, 16, 4,
+ { 0, &(xstormy16_cgen_ifld_table[18]) },
{ 0, { (1<<MACH_BASE) } } },
/* imm2: 2 bit unsigned immediate */
{ "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
+ { 0, &(xstormy16_cgen_ifld_table[21]) },
{ 0, { (1<<MACH_BASE) } } },
/* imm3: 3 bit unsigned immediate */
{ "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
+ { 0, &(xstormy16_cgen_ifld_table[22]) },
{ 0, { (1<<MACH_BASE) } } },
/* imm3b: 3 bit unsigned immediate for bit tests */
{ "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
+ { 0, &(xstormy16_cgen_ifld_table[23]) },
{ 0, { (1<<MACH_BASE) } } },
/* imm4: 4 bit unsigned immediate */
{ "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
+ { 0, &(xstormy16_cgen_ifld_table[24]) },
{ 0, { (1<<MACH_BASE) } } },
/* imm8: 8 bit unsigned immediate */
{ "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
+ { 0, &(xstormy16_cgen_ifld_table[25]) },
{ 0, { (1<<MACH_BASE) } } },
/* imm8small: 8 bit unsigned immediate */
{ "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
+ { 0, &(xstormy16_cgen_ifld_table[25]) },
{ 0, { (1<<MACH_BASE) } } },
/* imm12: 12 bit signed immediate */
{ "imm12", XSTORMY16_OPERAND_IMM12, HW_H_SINT, 20, 12,
+ { 0, &(xstormy16_cgen_ifld_table[26]) },
{ 0, { (1<<MACH_BASE) } } },
/* imm16: 16 bit immediate */
{ "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
+ { 0, &(xstormy16_cgen_ifld_table[27]) },
{ 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* lmem8: 8 bit unsigned immediate low memory */
{ "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
+ { 0, &(xstormy16_cgen_ifld_table[28]) },
{ 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
/* hmem8: 8 bit unsigned immediate high memory */
{ "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
+ { 0, &(xstormy16_cgen_ifld_table[29]) },
{ 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
/* rel8-2: 8 bit relative address */
{ "rel8-2", XSTORMY16_OPERAND_REL8_2, HW_H_UINT, 8, 8,
+ { 0, &(xstormy16_cgen_ifld_table[30]) },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* rel8-4: 8 bit relative address */
{ "rel8-4", XSTORMY16_OPERAND_REL8_4, HW_H_UINT, 8, 8,
+ { 0, &(xstormy16_cgen_ifld_table[31]) },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* rel12: 12 bit relative address */
{ "rel12", XSTORMY16_OPERAND_REL12, HW_H_UINT, 20, 12,
+ { 0, &(xstormy16_cgen_ifld_table[32]) },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* rel12a: 12 bit relative address */
{ "rel12a", XSTORMY16_OPERAND_REL12A, HW_H_UINT, 4, 11,
+ { 0, &(xstormy16_cgen_ifld_table[33]) },
{ 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* abs24: 24 bit absolute address */
{ "abs24", XSTORMY16_OPERAND_ABS24, HW_H_UINT, 8, 24,
+ { 2, &(XSTORMY16_F_ABS24_MULTI_IFIELD[0]) },
{ 0|A(ABS_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
/* psw: program status word */
{ "psw", XSTORMY16_OPERAND_PSW, HW_H_GR, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* Rpsw: N0-N3 of the program status word */
{ "Rpsw", XSTORMY16_OPERAND_RPSW, HW_H_RPSW, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* sp: stack pointer */
{ "sp", XSTORMY16_OPERAND_SP, HW_H_GR, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* R0: R0 */
{ "R0", XSTORMY16_OPERAND_R0, HW_H_GR, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* R1: R1 */
{ "R1", XSTORMY16_OPERAND_R1, HW_H_GR, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* R2: R2 */
{ "R2", XSTORMY16_OPERAND_R2, HW_H_GR, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* R8: R8 */
{ "R8", XSTORMY16_OPERAND_R8, HW_H_GR, 0, 0,
+ { 0, 0 },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, {0, {0}} }
};
{
const CGEN_ISA *isa = & xstormy16_cgen_isa_table[i];
- /* Default insn sizes of all selected isas must be equal or we set
- the result to 0, meaning "unknown". */
+ /* Default insn sizes of all selected isas must be
+ equal or we set the result to 0, meaning "unknown". */
if (cd->default_insn_bitsize == UNSET)
cd->default_insn_bitsize = isa->default_insn_bitsize;
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
else
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
- /* Base insn sizes of all selected isas must be equal or we set
- the result to 0, meaning "unknown". */
+ /* Base insn sizes of all selected isas must be equal
+ or we set the result to 0, meaning "unknown". */
if (cd->base_insn_bitsize == UNSET)
cd->base_insn_bitsize = isa->base_insn_bitsize;
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
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