(no commit message)

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 9717c2080fa84539485ca5b937ffd7ed22da91d9..7eb4847673c09584314b21fe200a97d6e3c5537d 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -41,15 +41,17 @@ Pages being developed and examples
 * [[sv/register_type_tags]]
 * [[sv/mv.swizzle]]
 * [[sv/mv.x]]
-* [[sv/branches]] - SVP64 Conditional Branch behaviour: All/Some Vector CRs
-* [[sv/cr_ops]] - SVP64 Condition Register ops: Guidelines
+* SVP64 "Modes":
+  - For condition register operations see [[sv/cr_ops]] - SVP64 Condition Register ops: Guidelines
  on Vectorisation of any v3.0B base operations which return
  or modify a Condition Register bit or field.
+  - For LD/ST Modes, see [[sv/ldst]].
+  - For Branch modes, see [[sv/branches]] - SVP64 Conditional Branch behaviour: All/Some Vector CRs
+  - For arithmetic and logical, see [[sv/normal]]
 * [[sv/fcvt]] FP Conversion (due to OpenPOWER Scalar FP32)
 * [[sv/fclass]] detect class of FP numbers
 * [[sv/int_fp_mv]] Move and convert GPR <-> FPR, needed for !VSX
 * [[sv/mv.vec]] move to and from vec2/3/4
-* [[sv/ldst]] Load and Store
 * [[sv/sprs]] SPRs
 * [[sv/bitmanip]]
 * [[sv/biginteger]] Operations that help with big arithmetic
@@ -60,12 +62,12 @@ Pages being developed and examples
 * [[sv/av_opcodes]] scalar opcodes for Audio/Video
 * Twin targetted instructions (two registers out, one implicit)
   Explanation of the rules for twin register targets
-  (implicit RS, FRS) explained in SVP4 [[sv/svp64/appendix]]
+  (implicit RS, FRS) explained in SVP64 [[sv/svp64/appendix]]
   - [[isa/svfixedarith]]
   - [[isa/svfparith]]
 * TODO: OpenPOWER [[openpower/transcendentals]]
 
-Examples ideas discussion:
+Examples experiments ideas discussion:
 
 * [[sv/masked_vector_chaining]]
 * [[sv/discussion]]