soc/integration/soc_sdram: allow using axi interface with litedram

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 71789a4fe8a8ae679014489e54343130f15d8a4b..432de0b26791636f25de0fba4abed490566ee43e 100644 (file)
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -5,7 +5,8 @@ from litex.soc.interconnect import wishbone
 from litex.soc.interconnect.csr import AutoCSR
 from litex.soc.integration.soc_core import *
 
-from litedram.frontend.wishbone import LiteDRAMWishbone2Native
+from litedram.frontend.wishbone import *
+from litedram.frontend.axi import *
 from litedram import dfii, core
 
 
@@ -51,7 +52,7 @@ class SoCSDRAM(SoCCore):
             raise FinalizeError
         self._wb_sdram_ifs.append(interface)
 
-    def register_sdram(self, phy, geom_settings, timing_settings, **kwargs):
+    def register_sdram(self, phy, geom_settings, timing_settings, use_axi=False, **kwargs):
         assert not self._sdram_phy
         self._sdram_phy.append(phy)  # encapsulate in list to prevent CSR scanning
 
@@ -84,7 +85,15 @@ class SoCSDRAM(SoCCore):
                 self.submodules.l2_cache = FullMemoryWE()(l2_cache)
             else:
                 self.submodules.l2_cache = l2_cache
-            self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port)
+            if use_axi:
+                axi_port = LiteDRAMAXIPort(
+                    port.data_width,
+                    port.address_width + log2_int(port.data_width//8))
+                axi2native = LiteDRAMAXI2Native(axi_port, port)
+                self.submodules += axi2native
+                self.submodules.wishbone_bridge = LiteDRAMWishbone2AXI(self.l2_cache.slave, axi_port)
+            else:
+                self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port)
 
     def do_finalize(self):
         if not self.integrated_main_ram_size: