Explicitly order function arguments

diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 5b168d52481f86883d0faf73c4d9cbb906fad923..034731b87c1b58f482c95b2a2b856811df6c2088 100644 (file)
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -48,14 +48,25 @@ struct AlumaccWorker
                RTLIL::SigSpec cached_cf, cached_of, cached_sf;
 
                RTLIL::SigSpec get_lt() {
-                       if (GetSize(cached_lt) == 0)
-                               cached_lt = is_signed ? alu_cell->module->Xor(NEW_ID, get_of(), get_sf()) : get_cf();
+                       if (GetSize(cached_lt) == 0) {
+                               if (is_signed) {
+                                       get_of();
+                                       get_sf();
+                                       cached_lt = alu_cell->module->Xor(NEW_ID, cached_of, cached_sf);
+                               }
+                               else
+                                       cached_lt = get_cf();
+                       }
                        return cached_lt;
                }
 
                RTLIL::SigSpec get_gt() {
-                       if (GetSize(cached_gt) == 0)
-                               cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->get_src_attribute());
+                       if (GetSize(cached_gt) == 0) {
+                               get_lt();
+                               get_eq();
+                               SigSpec Or = alu_cell->module->Or(NEW_ID, cached_lt, cached_eq);
+                               cached_gt = alu_cell->module->Not(NEW_ID, Or, false, alu_cell->get_src_attribute());
+                       }
                        return cached_gt;
                }