syscall_emul, riscv: add override keyword to RISCV Process class

Change-Id: I2a146ae57aac3787389997961208474a97e7c155
Reviewed-on: https://gem5-review.googlesource.com/3360
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Alec Roelke <ar4jc@virginia.edu>

diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh
index f732a44363943222789cd27b0a6c6152a5e25db7..2a27f350eb945768491e9df67acf259d4ed10c7a 100644 (file)
--- a/src/arch/riscv/process.hh
+++ b/src/arch/riscv/process.hh
@@ -48,17 +48,19 @@ class RiscvProcess : public Process
   protected:
     RiscvProcess(ProcessParams * params, ObjectFile *objFile);
 
-    void initState();
+    void initState() override;
 
     template<class IntType>
     void argsInit(int pageSize);
 
   public:
-    RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
+    RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override;
     /// Explicitly import the otherwise hidden getSyscallArg
     using Process::getSyscallArg;
-    void setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val);
-    void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
+    void setSyscallArg(ThreadContext *tc, int i,
+                       RiscvISA::IntReg val) override;
+    void setSyscallReturn(ThreadContext *tc,
+                          SyscallReturn return_value) override;
 
     virtual bool mmapGrowsDown() const override { return false; }
 };