Re: [libre-riscv-dev] cache SRAM organisation

diff --git a/4f/d8cd23a9b96c0b97306d2f8c090a1759275486 b/4f/d8cd23a9b96c0b97306d2f8c090a1759275486
new file mode 100644 (file)
index 0000000..df54b09
--- /dev/null
+++ b/4f/d8cd23a9b96c0b97306d2f8c090a1759275486
@@ -0,0 +1,98 @@
+Return-path: <libre-riscv-dev-bounces@lists.libre-riscv.org>
+Envelope-to: publicinbox@libre-riscv.org
+Delivery-date: Thu, 26 Mar 2020 20:18:41 +0000
+Received: from localhost ([::1] helo=libre-riscv.org)
+       by libre-riscv.org with esmtp (Exim 4.89)
+       (envelope-from <libre-riscv-dev-bounces@lists.libre-riscv.org>)
+       id 1jHYxc-0004dx-Ar; Thu, 26 Mar 2020 20:18:40 +0000
+Received: from vps2.stafverhaegen.be ([85.10.201.15])
+ by libre-riscv.org with esmtp (Exim 4.89)
+ (envelope-from <staf@fibraservi.eu>) id 1jHYxa-0004dr-W8
+ for libre-riscv-dev@lists.libre-riscv.org; Thu, 26 Mar 2020 20:18:39 +0000
+Received: from hpdc7800 (hpdc7800 [10.0.0.1])
+ by vps2.stafverhaegen.be (Postfix) with ESMTP id BBDD711C0287
+ for <libre-riscv-dev@lists.libre-riscv.org>;
+ Thu, 26 Mar 2020 21:18:38 +0100 (CET)
+Message-ID: <b18283c7e7a93fa8afdef2f0a8679b26e4569528.camel@fibraservi.eu>
+From: Staf Verhaegen <staf@fibraservi.eu>
+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Thu, 26 Mar 2020 21:18:34 +0100
+In-Reply-To: <CAPweEDzEvtPYGKvGMvebmQzhJDhSgfvUOVZvB2WXxSbv_ebE8A@mail.gmail.com>
+References: <CAPweEDx5QCCKxSr1gfuyuw_2D68Ld8fK85bEmmMTZi8S3w2E9g@mail.gmail.com>
+ <29b1a9ecedda151dc9c8da6516c3691dfede62ef.camel@fibraservi.eu>
+ <CAPweEDwfqMczPjg=5Fvt1J_S8nx1YK44XhyBY8H1abuTNF6=xg@mail.gmail.com>
+ <6fa40cb78b3f8c013ca4953ccb4daa5c23e3b501.camel@fibraservi.eu>
+ <CAPweEDxiyTEsneXN65Kq0HsEsdL3wdY=NYayq2tz5egXJNCVfg@mail.gmail.com>
+ <e430ea6587d292166fd58460adf4dfebfad20c6d.camel@fibraservi.eu>
+ <CAPweEDzEvtPYGKvGMvebmQzhJDhSgfvUOVZvB2WXxSbv_ebE8A@mail.gmail.com>
+Organization: FibraServi bvba
+X-Mailer: Evolution 3.28.5 (3.28.5-5.el7) 
+Mime-Version: 1.0
+X-Content-Filtered-By: Mailman/MimeDel 2.1.23
+Subject: Re: [libre-riscv-dev] cache SRAM organisation
+X-BeenThere: libre-riscv-dev@lists.libre-riscv.org
+X-Mailman-Version: 2.1.23
+Precedence: list
+List-Id: Libre-RISCV General Development
+ <libre-riscv-dev.lists.libre-riscv.org>
+List-Unsubscribe: <http://lists.libre-riscv.org/mailman/options/libre-riscv-dev>, 
+ <mailto:libre-riscv-dev-request@lists.libre-riscv.org?subject=unsubscribe>
+List-Archive: <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/>
+List-Post: <mailto:libre-riscv-dev@lists.libre-riscv.org>
+List-Help: <mailto:libre-riscv-dev-request@lists.libre-riscv.org?subject=help>
+List-Subscribe: <http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev>, 
+ <mailto:libre-riscv-dev-request@lists.libre-riscv.org?subject=subscribe>
+Reply-To: Libre-RISCV General Development
+ <libre-riscv-dev@lists.libre-riscv.org>
+Content-Type: multipart/mixed; boundary="===============4158649065915056839=="
+Errors-To: libre-riscv-dev-bounces@lists.libre-riscv.org
+Sender: "libre-riscv-dev" <libre-riscv-dev-bounces@lists.libre-riscv.org>
+
+
+--===============4158649065915056839==
+Content-Type: multipart/signed; micalg="pgp-sha1"; protocol="application/pgp-signature";
+       boundary="=-wcVlnSjfnd6RyNT0EAqq"
+
+
+--=-wcVlnSjfnd6RyNT0EAqq
+Content-Type: text/plain; charset="UTF-8"
+Content-Transfer-Encoding: quoted-printable
+
+Luke Kenneth Casson Leighton schreef op do 26-03-2020 om 13:05 [+0000]:
+> On Thursday, March 26, 2020, Staf Verhaegen <staf@fibraservi.eu> wrote:
+> > Would like to make separate side remark here. In ASICs MUXes are relati=
+veexpensive gates with respect to delay and power. So if this principle isg=
+enerally applied over the whole design it will make it difficult to make ac=
+hip that is competitive in power/performance compared to ARM/x86 CPUs.
+>=20
+>=20
+> just the ALU pipeline registers.  we felt that the advantage of being abl=
+eto drop to say 500mhz and halve the number of pipeline stages to say 5, an=
+dalso be able to ramp up to 1.6ghz and double bavk up to 10 stages, waswort=
+h considering.
+
+What would be the advantage over running at 800Mhz with 5 pipeline stages ?
+
+greets,
+Staf.
+
+
+--=-wcVlnSjfnd6RyNT0EAqq--
+
+
+
+--===============4158649065915056839==
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: base64
+Content-Disposition: inline
+
+X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz
+Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn
+Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj
+di1kZXYK
+
+--===============4158649065915056839==--
+
+
+