(no commit message)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 534d913624653acfa8387c49327b984b9914d382..dbd097348d0b82cea24329afa75c5ad77c3f8995 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -101,7 +101,8 @@ linearly to larger sizes; SV Vectorisation iterates sequentially through these r
 
 Where the integer regfile in standard scalar
 OpenPOWER v3.0B/v3.1B is r0 to r31, SV extends this as r0 to r127.
-Likewise FP registers are extended to 128 (fp0 to fp127), and CRs are
+Likewise FP registers are extended to 128 (fp0 to fp127), and CR Fields
+are
 extended to 128 entries, CR0 thru CR127.
 
 The names of the registers therefore reflects a simple linear extension
@@ -118,8 +119,7 @@ RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.  This is
 ## Future expansion.
 
 With the way that EXTRA fields are defined and applied to register fields,
-future versions of SV may involve 256 or greater registers.  To accommodate 256 registers, numbering of Vectors will simply shift up by one bit, without
-requiring additional prefix bits.  Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register).  Beyond this, further discussion is out of scope for this version of svp64.
+future versions of SV may involve 256 or greater registers. Backwards binary compatibility may be achieved with a PCR bit (Program Compatibility Register).  Further discussion is out of scope for this version of SVP64.
 
 # Remapped Encoding (`RM[0:23]`)