fhdl/verilog: add simulation parameter to avoid simulation tricks in synthetizable...

it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.

diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py
index 4b4a6e3cfdb7fd487ab31d798ca6d859b9fe2854..dca8de6c8f5fc9d7c2b734c579facec873db5d27 100644 (file)
--- a/mibuild/generic_platform.py
+++ b/mibuild/generic_platform.py
@@ -274,11 +274,11 @@ class GenericPlatform:
 
        def get_verilog(self, fragment, **kwargs):
                return self._get_source(fragment, lambda f: verilog.convert(f, self.constraint_manager.get_io_signals(),
-                               return_ns=True, create_clock_domains=False, **kwargs))
+                               return_ns=True, create_clock_domains=False, simulation=False, **kwargs))
 
        def get_edif(self, fragment, cell_library, vendor, device, **kwargs):
                return self._get_source(fragment, lambda f: edif.convert(f, self.constraint_manager.get_io_signals(),
-                               cell_library, vendor, device, return_ns=True, **kwargs))
+                               cell_library, vendor, device, return_ns=True, simulation=False, **kwargs))
 
        def build(self, fragment):
                raise NotImplementedError("GenericPlatform.build must be overloaded")

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index 3b5e4cf5dea6c4188978d5cba6aff4efb6498bef..7f97fa0ddc72d26afe7a90504a676493e1c0759c 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -175,18 +175,19 @@ def _printheader(f, ios, name, ns):
        r += "\n"
        return r
 
-def _printcomb(f, ns, display_run):
+def _printcomb(f, ns, simulation, display_run):
        r = ""
        if f.comb:
-               # Generate a dummy event to get the simulator
-               # to run the combinatorial process once at the beginning.
-               syn_off = "// synthesis translate_off\n"
-               syn_on = "// synthesis translate_on\n"
-               dummy_s = Signal(name_override="dummy_s")
-               r += syn_off
-               r += "reg " + _printsig(ns, dummy_s) + ";\n"
-               r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n"
-               r += syn_on
+               if simulation:
+                       # Generate a dummy event to get the simulator
+                       # to run the combinatorial process once at the beginning.
+                       syn_off = "// synthesis translate_off\n"
+                       syn_on = "// synthesis translate_on\n"
+                       dummy_s = Signal(name_override="dummy_s")
+                       r += syn_off
+                       r += "reg " + _printsig(ns, dummy_s) + ";\n"
+                       r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n"
+                       r += syn_on
 
                groups = group_by_targets(f.comb)
 
@@ -194,10 +195,11 @@ def _printcomb(f, ns, display_run):
                        if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
                                r += "assign " + _printnode(ns, _AT_BLOCKING, 0, g[1][0])
                        else:
-                               dummy_d = Signal(name_override="dummy_d")
-                               r += "\n" + syn_off
-                               r += "reg " + _printsig(ns, dummy_d) + ";\n"
-                               r += syn_on
+                               if simulation:
+                                       dummy_d = Signal(name_override="dummy_d")
+                                       r += "\n" + syn_off
+                                       r += "reg " + _printsig(ns, dummy_d) + ";\n"
+                                       r += syn_on
 
                                r += "always @(*) begin\n"
                                if display_run:
@@ -205,9 +207,10 @@ def _printcomb(f, ns, display_run):
                                for t in g[0]:
                                        r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n"
                                r += _printnode(ns, _AT_NONBLOCKING, 1, g[1])
-                               r += syn_off
-                               r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
-                               r += syn_on
+                               if simulation:
+                                       r += syn_off
+                                       r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
+                                       r += syn_on
                                r += "end\n"
        r += "\n"
        return r
@@ -295,6 +298,7 @@ def convert(f, ios=None, name="top",
   return_ns=False,
   special_overrides=dict(),
   create_clock_domains=True,
+  simulation=True,
   display_run=False):
        if not isinstance(f, _Fragment):
                f = f.get_fragment()
@@ -324,7 +328,7 @@ def convert(f, ios=None, name="top",
 
        r = "/* Machine-generated using Migen */\n"
        r += _printheader(f, ios, name, ns)
-       r += _printcomb(f, ns, display_run)
+       r += _printcomb(f, ns, simulation, display_run)
        r += _printsync(f, ns)
        r += _printspecials(special_overrides, f.specials - lowered_specials, ns)
        r += _printinit(f, ios, ns)