transport_tb: add basic test for TX path

diff --git a/lib/sata/test/Makefile b/lib/sata/test/Makefile
index 3e9abba8ad314b5656dbbdf1caeee4bdbb64a96f..a15250be61fa1427fc47821c9ddc72a91b8e0aca 100644 (file)
--- a/lib/sata/test/Makefile
+++ b/lib/sata/test/Makefile
@@ -20,7 +20,7 @@ link_tb:
 transport_tb:
        $(CMD) transport_tb.py
 
-all: crc_tb scrambler_tb
+all: crc_tb scrambler_tb link_tb
 
 clean:
        rm crc scrambler *.vcd

diff --git a/lib/sata/test/bfm.py b/lib/sata/test/bfm.py
index 7b5d88192f0c6dcee6a51325c0eb887cc9f733ec..1b07705549b196d696df95bf84aa6359526c2947 100644 (file)
--- a/lib/sata/test/bfm.py
+++ b/lib/sata/test/bfm.py
@@ -327,6 +327,8 @@ class FIS_DATA(FIS):
        def __repr__(self):
                r = "FIS_DATA\n"
                r += FIS.__repr__(self)
+               for data in self.packet[1:]:
+                       r += "%08x\n" %data
                return r
 
 class FIS_PIO_SETUP_D2H(FIS):
@@ -365,7 +367,7 @@ class TransportLayer(Module):
                elif fis_type == fis_types["DMA_ACTIVATE_D2H"]:
                        fis = FIS_DMA_ACTIVATE_D2H(packet)
                elif fis_type == fis_types["DMA_SETUP"]:
-                       fis = FIS_SETUP(packet)
+                       fis = FIS_DMA_SETUP(packet)
                elif fis_type == fis_types["DATA"]:
                        fis = FIS_DATA(packet)
                elif fis_type == fis_types["PIO_SETUP_D2H"]:

diff --git a/lib/sata/test/transport_tb.py b/lib/sata/test/transport_tb.py
index 70104d3780b3730c439ea48df8df6651f8b74f8d..7c39bf9231ad6c1bea77a29fb99a3c143333593f 100644 (file)
--- a/lib/sata/test/transport_tb.py
+++ b/lib/sata/test/transport_tb.py
@@ -14,15 +14,39 @@ from lib.sata.test.common import *
 class TB(Module):
        def __init__(self):
                self.submodules.bfm = BFM(phy_debug=False,
-                               link_random_level=50, transport_debug=True, transport_loopback=True)
+                               link_random_level=0, transport_debug=True, transport_loopback=True)
                self.submodules.link = SATALinkLayer(self.bfm.phy)
                self.submodules.transport = SATATransportLayer(self.link)
 
-               self.comb += [
-                       self.transport.tx.cmd.stb.eq(1),
-                       self.transport.tx.cmd.type.eq(fis_types["REG_H2D"]),
-                       self.transport.tx.cmd.lba.eq(0x12345678)
-               ]
+       def gen_simulation(self, selfp):
+               for i in range(100):
+                       yield
+               selfp.transport.tx.cmd.stb = 1
+               selfp.transport.tx.cmd.type = fis_types["REG_H2D"]
+               selfp.transport.tx.cmd.lba = 0x0123456789
+               yield
+               while selfp.transport.tx.cmd.ack == 0:
+                       yield
+               selfp.transport.tx.cmd.stb = 1
+               selfp.transport.tx.cmd.type = fis_types["DMA_SETUP"]
+               selfp.transport.tx.cmd.dma_buffer_id = 0x0123456789ABCDEF
+               yield
+               while selfp.transport.tx.cmd.ack == 0:
+                       yield
+               selfp.transport.tx.cmd.stb = 1
+               selfp.transport.tx.cmd.type = fis_types["DATA"]
+               yield
+               for i in range(32):
+                       selfp.transport.tx.data.stb = 1
+                       #selfp.transport.tx.data.sop = (i==0)
+                       selfp.transport.tx.data.eop = (i==31)
+                       selfp.transport.tx.data.d = i
+                       if selfp.transport.tx.data.ack == 1:
+                               yield
+                       else:
+                               while selfp.transport.tx.data.ack == 0:
+                                       yield
+               selfp.transport.tx.cmd.stb = 0
 
 if __name__ == "__main__":
-       run_simulation(TB(), ncycles=256, vcd_name="my.vcd", keep_files=True)
+       run_simulation(TB(), ncycles=512, vcd_name="my.vcd", keep_files=True)