(match_operand:SI 2 "general_operand" "")))]
"TARGET_INLINE_INT_DIV"
{
- rtx op1_xf, op2_xf, op0_xf, op0_di, twon34;
+ rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp;
REAL_VALUE_TYPE twon34_r;
op0_xf = gen_reg_rtx (XFmode);
expand_float (op2_xf, operands[2], 0);
/* 2^-34 */
- real_2expN (&twon34_r, -34);
- twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, XFmode);
- twon34 = force_reg (XFmode, twon34);
+ twon34_exp = gen_reg_rtx (DImode);
+ emit_move_insn (twon34_exp, GEN_INT (65501));
+ twon34 = gen_reg_rtx (XFmode);
+ emit_insn (gen_setf_exp_xf (twon34, twon34_exp));
emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
(match_operand:SI 2 "general_operand" "")))]
"TARGET_INLINE_INT_DIV"
{
- rtx op1_xf, op2_xf, op0_xf, op0_di, twon34;
+ rtx op1_xf, op2_xf, op0_xf, op0_di, twon34, twon34_exp;
REAL_VALUE_TYPE twon34_r;
op0_xf = gen_reg_rtx (XFmode);
expand_float (op2_xf, operands[2], 1);
/* 2^-34 */
- real_2expN (&twon34_r, -34);
- twon34 = CONST_DOUBLE_FROM_REAL_VALUE (twon34_r, XFmode);
- twon34 = force_reg (XFmode, twon34);
+ twon34_exp = gen_reg_rtx (DImode);
+ emit_move_insn (twon34_exp, GEN_INT (65501));
+ twon34 = gen_reg_rtx (XFmode);
+ emit_insn (gen_setf_exp_xf (twon34, twon34_exp));
emit_insn (gen_divsi3_internal (op0_xf, op1_xf, op2_xf, twon34));
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
-(define_insn "*setf_exp_xf"
+(define_insn "setf_exp_xf"
[(set (match_operand:XF 0 "fr_register_operand" "=f")
(unspec:XF [(match_operand:DI 1 "register_operand" "r")]
UNSPEC_SETF_EXP))]