(no commit message)

diff --git a/openpower/sv/mv.swizzle.mdwn b/openpower/sv/mv.swizzle.mdwn
index f49e567a06da1f04bb4c0186ebd2ef11c1156124..0790f5fd826d9a3ae72a9137c84b56dd37c42663 100644 (file)
--- a/openpower/sv/mv.swizzle.mdwn
+++ b/openpower/sv/mv.swizzle.mdwn
@@ -87,7 +87,8 @@ copy the contents RA+1 into RT, but set RT+1 to zero.
 
 Also, making life easier, RT and RA are only permitted to be even
 (no overlapping can occur).  This makes RT (and RA) a "pair" exactly
-like `lq` and `stq`
+like `lq` and `stq`.  Swizzle instructions must be atomically indivisible:
+an Exception or Interrupt may not occur during the pair of Moves.
 
 **SVP64 Vectorised**