cpu/vexriscv: update submodule

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index 854f9bd2282c97251ce65e4117c5cf1630722004..8baad219885a47f65959a9cd4870691e84678db4 160000 (submodule)
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit 854f9bd2282c97251ce65e4117c5cf1630722004
+Subproject commit 8baad219885a47f65959a9cd4870691e84678db4