ac/gpu_info: add has_2d_tiling

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 7e40ffcf3e72c7ce58b0587769975886a5a2412f..906e76ba051f1292d00e7e577db296e2d1126100 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -337,6 +337,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
        info->has_sparse_vm_mappings =
                info->chip_class >= CIK && info->chip_class <= VI &&
                info->drm_minor >= 13;
+       info->has_2d_tiling = true;
 
        info->num_render_backends = amdinfo->rb_pipes;
        /* The value returned by the kernel driver was wrong. */
@@ -496,6 +497,7 @@ void ac_print_gpu_info(struct radeon_info *info)
        printf("    has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
        printf("    has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
        printf("    has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
+       printf("    has_2d_tiling = %u\n", info->has_2d_tiling);
 
        printf("Shader core info:\n");
        printf("    max_shader_clock = %i\n", info->max_shader_clock);

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 7caa6543695a158db015ac41901960c51ed3f32f..fb44f7c8af49d4dbc02d7cc0c15276a48c61934e 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -108,6 +108,7 @@ struct radeon_info {
        bool                        has_indirect_compute_dispatch;
        bool                        has_unaligned_shader_loads;
        bool                        has_sparse_vm_mappings;
+       bool                        has_2d_tiling;
 
        /* Shader cores. */
        uint32_t                    r600_max_quad_pipes; /* wave size / 16 */

diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c
index ef74cd457b8f81210dab19cf334165c621b9b977..757192f309cd78e5798be48504415ffa6183c903 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -198,11 +198,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
                       sscreen->info.has_gpu_reset_counter_query;
 
        case PIPE_CAP_TEXTURE_MULTISAMPLE:
-               /* 2D tiling on CIK is supported since DRM 2.35.0 */
-               return sscreen->info.chip_class < CIK ||
-                      (sscreen->info.drm_major == 2 &&
-                       sscreen->info.drm_minor >= 35) ||
-                      sscreen->info.drm_major == 3;
+               return sscreen->info.has_2d_tiling;
 
         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
                 return SI_MAP_BUFFER_ALIGNMENT;

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 3585b35af361b9a747d3b21c687ed6cf90a351d7..cb8c7ce9fcb3529b6dde2a0735a8685a34bebfc3 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -548,6 +548,8 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
     ws->info.has_unaligned_shader_loads = ws->info.chip_class == CIK &&
                                           ws->info.drm_minor >= 50;
     ws->info.has_sparse_vm_mappings = false;
+    /* 2D tiling on CIK is supported since DRM 2.35.0 */
+    ws->info.has_2d_tiling = ws->info.chip_class <= SI || ws->info.drm_minor >= 35;
 
     ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;