ruby: no piobus in se mode

Piobus was recently added to se scripts for ruby so that the interrupt
controller can be connected to something (required since the interrupt
controller sends address range messages).  This patch removes the piobus
and instead, the pio port of ruby port will now ignore the range change
messages in se mode.

diff --git a/configs/example/se.py b/configs/example/se.py
index d390fbad004a5032243a5740a7a36b01dc503940..97ad2c7de142353748516da18fa8bc7cfc5f31cc 100644 (file)
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -232,9 +232,7 @@ if options.ruby:
     system.physmem = MemClass(range=AddrRange(options.mem_size),
                               null = True)
     options.use_map = True
-
-    system.piobus = NoncoherentBus()
-    Ruby.create_system(options, system, system.piobus)
+    Ruby.create_system(options, system)
     assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
 
     for i in xrange(np):

diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index ec1266a907fa8d6830f72c8fd2eff9902419f763..110b6924dc2ce9441c16ebbfbc9c58d7d083fd2f 100644 (file)
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -46,6 +46,7 @@
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
 #include "mem/ruby/system/RubyPort.hh"
+#include "sim/full_system.hh"
 #include "sim/system.hh"
 
 RubyPort::RubyPort(const Params *p)
@@ -558,7 +559,7 @@ RubyPort::PioMasterPort::recvRangeChange()
 {
     RubyPort &r = static_cast<RubyPort &>(owner);
     r.gotAddrRanges--;
-    if (r.gotAddrRanges == 0) {
+    if (r.gotAddrRanges == 0 && FullSystem) {
         r.pioSlavePort.sendRangeChange();
     }
 }

diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index d3f4ad2ae93a18394bde39cb066fcb1eebe01772..94cb15ed45f0b4ac81b33e2dea1f99f5c68bcf7c 100644 (file)
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -79,8 +79,7 @@ system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
                                        voltage_domain = system.voltage_domain)
 
 system.mem_ranges = AddrRange('256MB')
-system.piobus = NoncoherentBus()
-Ruby.create_system(options, system, system.piobus)
+Ruby.create_system(options, system)
 
 # Create a separate clock for Ruby
 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,