--- /dev/null
+#as: -a32 -mpower7
+#objdump: -dr -Mpower7
+#name: POWER7 tests (includes DFP, Altivec and VSX)
+
+.*: +file format elf32-powerpc.*
+
+Disassembly of section \.text:
+
+0+00 <power7>:
+ 0: 7c 64 2e 98 lxvd2x vs3,r4,r5
+ 4: 7c 64 2e d8 lxvd2ux vs3,r4,r5
+ 8: 7d 64 2e 99 lxvd2x vs43,r4,r5
+ c: 7d 64 2e d9 lxvd2ux vs43,r4,r5
+ 10: 7c 64 2f 98 stxvd2x vs3,r4,r5
+ 14: 7c 64 2f d8 stxvd2ux vs3,r4,r5
+ 18: 7d 64 2f 99 stxvd2x vs43,r4,r5
+ 1c: 7d 64 2f d9 stxvd2ux vs43,r4,r5
+ 20: f0 64 28 50 xxmrghd vs3,vs4,vs5
+ 24: f1 6c 68 57 xxmrghd vs43,vs44,vs45
+ 28: f0 64 2b 50 xxmrgld vs3,vs4,vs5
+ 2c: f1 6c 6b 57 xxmrgld vs43,vs44,vs45
+ 30: f0 64 28 50 xxmrghd vs3,vs4,vs5
+ 34: f1 6c 68 57 xxmrghd vs43,vs44,vs45
+ 38: f0 64 2b 50 xxmrgld vs3,vs4,vs5
+ 3c: f1 6c 6b 57 xxmrgld vs43,vs44,vs45
+ 40: f0 64 29 50 xxpermdi vs3,vs4,vs5,1
+ 44: f1 6c 69 57 xxpermdi vs43,vs44,vs45,1
+ 48: f0 64 2a 50 xxpermdi vs3,vs4,vs5,2
+ 4c: f1 6c 6a 57 xxpermdi vs43,vs44,vs45,2
+ 50: f0 64 27 80 xvmovdp vs3,vs4
+ 54: f1 6c 67 87 xvmovdp vs43,vs44
+ 58: f0 64 27 80 xvmovdp vs3,vs4
+ 5c: f1 6c 67 87 xvmovdp vs43,vs44
+ 60: f0 64 2f 80 xvcpsgndp vs3,vs4,vs5
+ 64: f1 6c 6f 87 xvcpsgndp vs43,vs44,vs45
+ 68: 4c 00 03 24 doze
+ 6c: 4c 00 03 64 nap
+ 70: 4c 00 03 a4 sleep
+ 74: 4c 00 03 e4 rvwinkle
+ 78: 7c 83 01 34 prtyw r3,r4
+ 7c: 7d cd 01 74 prtyd r13,r14
+ 80: 7d 5c 02 a6 mfcfar r10
+ 84: 7d 7c 03 a6 mtcfar r11
+ 88: 7c 83 2b f8 cmpb r3,r4,r5
+ 8c: 7c c0 3c be mffgpr f6,r7
+ 90: 7d 00 4d be mftgpr r8,f9
+ 94: 7d 4b 66 2a lwzcix r10,r11,r12
+ 98: 7d ae 7e 2e lfdpx f13,r14,r15
+ 9c: ee 11 90 04 dadd f16,f17,f18
+ a0: fe 96 c0 04 daddq f20,f22,f24
+ a4: 7c 60 06 6c dss 3
+ a8: 7e 00 06 6c dssall
+ ac: 7c 25 22 ac dst r5,r4,1
+ b0: 7e 08 3a ac dstt r8,r7,0
+ b4: 7c 65 32 ec dstst r5,r6,3
+ b8: 7e 44 2a ec dststt r4,r5,2
+ bc: 4e 80 00 20 blr
static long extract_sprg (unsigned long, ppc_cpu_t, int *);
static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **);
static long extract_tbr (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_xt6 (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_xa6 (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_xb6 (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_xb6s (unsigned long, ppc_cpu_t, int *);
\f
/* The operands table.
#define URC URB + 1
{ 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
+ /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
+#define XS6 URC + 1
+#define XT6 XS6
+ { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
+
+ /* The XA field in an XX3 form instruction. This is split. */
+#define XA6 XT6 + 1
+ { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
+
+ /* The XB field in an XX3 form instruction. This is split. */
+#define XB6 XA6 + 1
+ { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
+
+ /* The XB field in an XX3 form instruction when it must be the same as
+ the XA field in the instruction. This is used in extended mnemonics
+ like xvmovdp. This is split. */
+#define XB6S XB6 + 1
+ { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
+
+ /* The DM field in an XX3 form instruction. */
+#define DM XB6S + 1
+ { 0x3, 8, NULL, NULL, 0 },
};
const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
ret = 0;
return ret;
}
+
+/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */
+
+static unsigned long
+insert_xt6 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5);
+}
+
+static long
+extract_xt6 (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f);
+}
+
+/* The XA field in an XX3 form instruction. This is split. */
+
+static unsigned long
+insert_xa6 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3);
+}
+
+static long
+extract_xa6 (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f);
+}
+
+/* The XB field in an XX3 form instruction. This is split. */
+
+static unsigned long
+insert_xb6 (unsigned long insn,
+ long value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
+}
+
+static long
+extract_xb6 (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f);
+}
+
+/* The XB field in an XX3 form instruction when it must be the same as
+ the XA field in the instruction. This is used for extended
+ mnemonics like xvmovdp. This operand is marked FAKE. The insertion
+ function just copies the XA field into the XB field, and the
+ extraction function just checks that the fields are the same. */
+
+static unsigned long
+insert_xb6s (unsigned long insn,
+ long value ATTRIBUTE_UNUSED,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1);
+}
+
+static long
+extract_xb6s (unsigned long insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
+ || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1)))
+ *invalid = 1;
+ return 0;
+}
\f
/* Macros used to form opcodes. */
/* An X form instruction. */
#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
+/* An XX3 form instruction. */
+#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3))
+
+#define XX3DM(op, xop, dm) (XX3 (op, ((unsigned long)(xop) & 0x1f)) \
+ | ((((unsigned long)(dm)) & 0x3) << 8))
+
/* A Z form instruction. */
#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))
/* The mask for an X form instruction. */
#define X_MASK XRC (0x3f, 0x3ff, 1)
+/* The mask for an XX1 form instruction. */
+#define XX1_MASK X (0x3f, 0x3ff)
+
+/* The mask for an XX3 form instruction. */
+#define XX3_MASK XX3 (0x3f, 0xff)
+
+/* The mask for an XX3 form instruction with the DM bits specified. */
+#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
+
/* The mask for a Z form instruction. */
#define Z_MASK ZRC (0x3f, 0x1ff, 1)
#define Z2_MASK ZRC (0x3f, 0xff, 1)
#define PPC860 PPC
#define PPCPS PPC_OPCODE_PPCPS
#define PPCVEC PPC_OPCODE_ALTIVEC
+#define PPCVSX PPC_OPCODE_VSX
#define POWER PPC_OPCODE_POWER
#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
{"divo.", XO(31,331,1,1), XO_MASK, M601, {RT, RA, RB}},
{"lduxe", X(31,831), X_MASK, BOOKE64, {RT, RA0, RB}},
+{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, {XT6, RA, RB}},
+
{"slbmfev", X(31,851), XRA_MASK, PPC64, {RT, RB}},
{"lbzcix", X(31,853), X_MASK, POWER6, {RT, RA0, RB}},
{"divso", XO(31,363,1,0), XO_MASK, M601, {RT, RA, RB}},
{"divso.", XO(31,363,1,1), XO_MASK, M601, {RT, RA, RB}},
+{"lxvd2ux", X(31,876), XX1_MASK, PPCVSX, {XT6, RA, RB}},
+
{"ldcix", X(31,885), X_MASK, POWER6, {RT, RA0, RB}},
{"stvlxl", X(31,903), X_MASK, CELL, {VS, RA0, RB}},
{"divwuo", XO(31,459,1,0), XO_MASK, PPC, {RT, RA, RB}},
{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, {RT, RA, RB}},
+{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, {XS6, RA, RB}},
+
{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, {RT, RA}},
{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, {RT, RA}},
{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}},
{"divwo", XO(31,491,1,0), XO_MASK, PPC, {RT, RA, RB}},
{"divwo.", XO(31,491,1,1), XO_MASK, PPC, {RT, RA, RB}},
+{"stxvd2ux", X(31,1004), XX1_MASK, PPCVSX, {XS6, RA, RB}},
+
{"tlbli", X(31,1010), XRTRA_MASK, PPC, {RB}},
{"stdcix", X(31,1013), X_MASK, POWER6, {RS, RA0, RB}},
{"stfq", OP(60), OP_MASK, POWER2, {FRS, D, RA}},
{"psq_st", OP(60), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}},
+
+{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, {XT6, XA6, XB6}},
+{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, {XT6, XA6, XB6}},
+{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, {XT6, XA6, XB6, DM}},
+{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6S}},
+{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6}},
+
{"psq_stu", OP(61), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}},
{"stfqu", OP(61), OP_MASK, POWER2, {FRS, D, RA}},
projects / binutils-gdb.git / commitdiff