CHIPSET(0x162B, bdw_gt3, "Intel(R) Broadwell")
CHIPSET(0x162D, bdw_gt3, "Intel(R) Broadwell")
CHIPSET(0x162E, bdw_gt3, "Intel(R) Broadwell")
+CHIPSET(0x22B0, chv, "Intel(R) Cherryview")
+CHIPSET(0x22B1, chv, "Intel(R) Cherryview")
+CHIPSET(0x22B2, chv, "Intel(R) Cherryview")
+CHIPSET(0x22B3, chv, "Intel(R) Cherryview")
GEN8_FEATURES, .gt = 3,
};
+/* Thread counts and URB limits are placeholders, and may not be accurate.
+ * These were copied from Haswell GT1, above.
+ */
+static const struct brw_device_info brw_device_info_chv = {
+ GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
+ .has_llc = false,
+ .max_vs_threads = 70,
+ .max_gs_threads = 70,
+ .max_wm_threads = 102,
+ .urb = {
+ .max_vs_entries = 640,
+ .max_gs_entries = 256,
+ }
+};
+
const struct brw_device_info *
brw_get_device_info(int devid)
{