[AArch64] Fix INSR for zero floats

We used INSR to handle zero integers but not zero floats.

2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/constraints.md (Z): Handle floating-point zeros too.
	* config/aarch64/predicates.md (aarch64_reg_or_zero): Likewise.

gcc/testsuite/
	* gcc.target/aarch64/sve/init_13.c: New test.

From-SVN: r274193

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ef6c201e29fe0a5021fc799b5c58b511d279a9f3..45050ed2f7bdc10b18354f7027dd4611e5f79632 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/constraints.md (Z): Handle floating-point zeros too.
+       * config/aarch64/predicates.md (aarch64_reg_or_zero): Likewise.
+
 2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
 
        * config/aarch64/aarch64-sve.md (vec_shl_insert_<mode>): Add

diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index 21f9549e660868900256157ea2f7154164ddd607..824000a842364e5ee2116ad63422d2a815efb119 100644 (file)
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -114,8 +114,8 @@
        (match_test "aarch64_float_const_zero_rtx_p (op)")))
 
 (define_constraint "Z"
-  "Integer constant zero."
-  (match_test "op == const0_rtx"))
+  "Integer or floating-point constant zero."
+  (match_test "op == CONST0_RTX (GET_MODE (op))"))
 
 (define_constraint "Ush"
   "A constraint that matches an absolute symbolic address high part."

diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 10100ca830a0cd753ef5759e3ce09914b1046d26..2cd0b87b28750fc6440a68c9f523ddf567bb5eb5 100644 (file)
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -57,9 +57,9 @@
             (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS"))))
 
 (define_predicate "aarch64_reg_or_zero"
-  (and (match_code "reg,subreg,const_int")
+  (and (match_code "reg,subreg,const_int,const_double")
        (ior (match_operand 0 "register_operand")
-           (match_test "op == const0_rtx"))))
+           (match_test "op == CONST0_RTX (GET_MODE (op))"))))
 
 (define_predicate "aarch64_reg_or_fp_zero"
   (ior (match_operand 0 "register_operand")

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 22cf0e97c125ef58cfce69b212238dd47b18db94..cf4cbabca69d304abad459c6c8d1147e4d0aeed9 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * gcc.target/aarch64/sve/init_13.c: New test.
+
 2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
 
        * gcc.target/aarch64/sve/init_12.c: Expect w1 to be moved into

diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_13.c b/gcc/testsuite/gcc.target/aarch64/sve/init_13.c
new file mode 100644 (file)
index 0000000..eea4170
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve/init_13.c
@@ -0,0 +1,17 @@
+/* { dg-do assemble { target aarch64_asm_sve_ok } } */
+/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+typedef float vnx4sf __attribute__((vector_size (32)));
+
+/*
+** foo:
+**     mov     (z[0-9]+\.s), s0
+**     insr    \1, wzr
+**     ...
+*/
+vnx4sf
+foo (float a)
+{
+  return (vnx4sf) { 0.0f, a, a, a, a, a, a, a };
+}