ruby: change slicc to allow for constructor args

The patch adds support to slicc for recognizing arguments that should be
passed to the constructor of a class. I did not like the fact that an explicit
check was being carried on the type 'TBETable' to figure out the arguments to
be passed to the constructor.
The patch also moves some of the member variables that are declared for all
the controllers to the base class AbstractController.

diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
index eb8e62d30bb577fd9caa3c3cf6851642224d523b..d12e44ba3b53552bd6c9bbd6b31a3e4aa05569da 100644 (file)
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
@@ -126,7 +126,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
     bool isPresent(Address);
   }
 
-  TBETable L1_TBEs, template="<L1Cache_TBE>";
+  TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 
   MessageBuffer mandatoryQueue, ordered="false";
 

diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
index fbdc10ac2e866a6026630ff5cb59cfe14ac0d1a8..849714c49a3ce5aaef03b634a8c2670b6c088837 100644 (file)
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
@@ -151,7 +151,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     bool isPresent(Address);
   }
 
-  TBETable L2_TBEs, template="<L2Cache_TBE>";
+  TBETable L2_TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
 
   void set_cache_entry(AbstractCacheEntry a);
   void unset_cache_entry();

diff --git a/src/mem/protocol/MESI_CMP_directory-dir.sm b/src/mem/protocol/MESI_CMP_directory-dir.sm
index d98326b34a0531b5f622265553f10b71a6d12960..0dbbafafaaf6f51e802baa774c53f8fff3dfa0da 100644 (file)
--- a/src/mem/protocol/MESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MESI_CMP_directory-dir.sm
@@ -105,7 +105,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
 
   // ** OBJECTS **
 
-  TBETable TBEs, template="<Directory_TBE>";
+  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   void set_tbe(TBE tbe);
   void unset_tbe();

diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index 5040eb85dacf561566ba191d17b8cf78af705d9c..91f060a3893e3985bae56d1f8b60701037c3485b 100644 (file)
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -98,7 +98,7 @@ machine(L1Cache, "MI Example L1 Cache")
 
 
   // STRUCTURES
-  TBETable TBEs, template="<L1Cache_TBE>";
+  TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 
   // PROTOTYPES
   void set_cache_entry(AbstractCacheEntry a);

diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm
index f15ccb14e92fcd9b32b2dd55544b10a9f5e49d76..edb571c1f7b39a2a11d9c1a2d2f324e8c41cbfc4 100644 (file)
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/protocol/MI_example-dir.sm
@@ -102,7 +102,7 @@ machine(Directory, "Directory protocol")
   }
 
   // ** OBJECTS **
-  TBETable TBEs, template="<Directory_TBE>";
+  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   void set_tbe(TBE b);
   void unset_tbe();

diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
index 6295f90fda3e79e3973da306444037519b9371f2..f6ed3200984b1eeaa485b4da453f3aa2ff6fd6bd 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -142,7 +142,7 @@ machine(L1Cache, "Directory protocol")
 
   MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
 
-  TBETable TBEs, template="<L1Cache_TBE>";
+  TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
   TimerTable useTimerTable;
   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
 

diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
index 2e4e66a7bb4a2037fcd7abe3e54470d704c58288..ba78cff9f0853c5c62915be242ccd36e6de18278 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -224,8 +224,7 @@ machine(L2Cache, "Token protocol")
     bool isTagPresent(Address);
   }
 
-
-  TBETable TBEs, template="<L2Cache_TBE>";
+  TBETable TBEs, template="<L2Cache_TBE>", constructor="m_number_of_TBEs";
   PerfectCacheMemory localDirectory, template="<L2Cache_DirEntry>";
 
   void set_cache_entry(AbstractCacheEntry b);

diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm
index 0dd4239a933e9d51e22ef81078c6911d5eb131f9..f458fccd86da6b9be1ac083361eb1882735f330d 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm
@@ -1,4 +1,3 @@
-
 /*
  * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
  * All rights reserved.
@@ -119,7 +118,7 @@ machine(Directory, "Directory protocol")
   }
 
   // ** OBJECTS **
-  TBETable TBEs, template="<Directory_TBE>";
+  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   void set_tbe(TBE b);
   void unset_tbe();

diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm
index e0a8a3eb58c6b0d7021d528bca856d94db7f8643..6d10305ea3a28e934552b289577f4b208fc29cec 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -44,7 +44,7 @@ machine(DMA, "DMA Controller")
 
   MessageBuffer mandatoryQueue, ordered="false";
   MessageBuffer triggerQueue, ordered="true";
-  TBETable TBEs, template="<DMA_TBE>";
+  TBETable TBEs, template="<DMA_TBE>", constructor="m_number_of_TBEs";
   State cur_state;
 
   void set_tbe(TBE b);

diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
index 8cf40974e5fde300b249452bfa65c6478f05c73e..a5de5e832eebe011490d12b3b877e3d22a4cde80 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -180,7 +180,7 @@ machine(L1Cache, "Token protocol")
   void wakeUpAllBuffers();
   void wakeUpBuffers(Address a);
 
-  TBETable L1_TBEs, template="<L1Cache_TBE>";
+  TBETable L1_TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 
   MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
 

diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm
index fd51e292441b4f7d0ea0cae95b3f57c13001d076..5a604555e67d421315ce2c5d3dc74a8875c5073d 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm
@@ -157,7 +157,7 @@ machine(Directory, "Token protocol")
   PersistentTable persistentTable;
   TimerTable reissueTimerTable;
 
-  TBETable TBEs, template="<Directory_TBE>";
+  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   bool starving, default="false";
   int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";

diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index a3fa1219f7a8f5a0fe8aae52045196769916c828..0f35b4277525568b3e6137cfb19b8a35b92c28b6 100644 (file)
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -173,7 +173,7 @@ machine(L1Cache, "AMD Hammer-like protocol")
     bool isPresent(Address);
   }
 
-  TBETable TBEs, template="<L1Cache_TBE>";
+  TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs";
 
   void set_cache_entry(AbstractCacheEntry b);
   void unset_cache_entry();

diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
index 22ca568a8a83ded3a13538b56e9c431937b8777a..5b752f7816d8cf78034f43e7d46717bd49a48b27 100644 (file)
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -184,7 +184,7 @@ machine(Directory, "AMD Hammer-like protocol")
 
   Set fwd_set;
 
-  TBETable TBEs, template="<Directory_TBE>";
+  TBETable TBEs, template="<Directory_TBE>", constructor="m_number_of_TBEs";
 
   Entry getDirectoryEntry(Address addr), return_by_pointer="yes" {
     Entry dir_entry := static_cast(Entry, "pointer", directory[addr]);

diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm
index 64b156938145572d47bad0d3b091482f168d364f..1e49e1d7b7306b926e81c36bf5934cc60683b38e 100644 (file)
--- a/src/mem/protocol/Network_test-cache.sm
+++ b/src/mem/protocol/Network_test-cache.sm
@@ -66,25 +66,6 @@ machine(L1Cache, "Network_test L1 Cache")
     DataBlock DataBlk,       desc="Data in the block";
   }
 
-  // TBE fields
-  structure(TBE, desc="...") {
-    State TBEState,          desc="Transient state";
-    DataBlock DataBlk,       desc="data for the block, required for concurrent writebacks";
-  }
-
-  structure(TBETable, external="yes") {
-    TBE lookup(Address);
-    void allocate(Address);
-    void deallocate(Address);
-    bool isPresent(Address);
-  }
-
-
-  // STRUCTURES
-
-  TBETable TBEs, template="<L1Cache_TBE>";
-
-
   // FUNCTIONS
 
   // cpu/testers/networktest/networktest.cc generates packets of the type
@@ -112,11 +93,11 @@ machine(L1Cache, "Network_test L1 Cache")
   }
 
 
-  State getState(TBE tbe, Entry cache_entry, Address addr) {
+  State getState(Entry cache_entry, Address addr) {
     return State:I;
   }
 
-  void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
+  void setState(Entry cache_entry, Address addr, State state) {
 
   }
 
@@ -146,9 +127,7 @@ machine(L1Cache, "Network_test L1 Cache")
     if (mandatoryQueue_in.isReady()) {
       peek(mandatoryQueue_in, RubyRequest) {
         trigger(mandatory_request_type_to_event(in_msg.Type),
-                in_msg.LineAddress,
-                getCacheEntry(in_msg.LineAddress),
-                TBEs[in_msg.LineAddress]);
+                in_msg.LineAddress, getCacheEntry(in_msg.LineAddress));
       }
     }
   }

diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
index 2a4281757a1fdcff6eb1c4349fb7bd4e9ba5367c..6c8cfc832979deef0299a082ab967eba9ce06163 100644 (file)
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -31,6 +31,7 @@
 external_type(int, primitive="yes", default="0");
 external_type(bool, primitive="yes", default="false");
 external_type(std::string, primitive="yes");
+external_type(uint32_t, primitive="yes");
 external_type(uint64, primitive="yes");
 external_type(Time, primitive="yes", default="0");
 external_type(PacketPtr, primitive="yes");

diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc
index eca68ad05437663d0574caf815ddd371b2118aeb..ac48db0c7a66730b21fb8b07bdbbea6a08b87467 100644 (file)
--- a/src/mem/ruby/slicc_interface/AbstractController.cc
+++ b/src/mem/ruby/slicc_interface/AbstractController.cc
@@ -32,5 +32,11 @@
 AbstractController::AbstractController(const Params *p)
     : SimObject(p), Consumer(this)
 {
-  p->ruby_system->registerAbstractController(this);
+    m_version = p->version;
+    m_transitions_per_cycle = p->transitions_per_cycle;
+    m_buffer_size = p->buffer_size;
+    m_recycle_latency = p->recycle_latency;
+    m_number_of_TBEs = p->number_of_TBEs;
+    m_is_blocking = false;
+    p->ruby_system->registerAbstractController(this);
 }

diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index 9ab924608b7d7597c331a56fae6013215d41797c..16b881b1f34faff5473ad862ea8826cd5c2328f3 100644 (file)
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -32,13 +32,14 @@
 #include <iostream>
 #include <string>
 
-#include "mem/packet.hh"
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
 #include "mem/ruby/common/DataBlock.hh"
 #include "mem/ruby/network/Network.hh"
 #include "mem/ruby/recorder/CacheRecorder.hh"
+#include "mem/ruby/system/MachineID.hh"
+#include "mem/packet.hh"
 #include "params/RubyController.hh"
 #include "sim/sim_object.hh"
 
@@ -82,6 +83,24 @@ class AbstractController : public SimObject, public Consumer
     //! Function for enqueuing a prefetch request
     virtual void enqueuePrefetch(const Address&, const RubyRequestType&)
     { fatal("Prefetches not implemented!");}
+
+  protected:
+    int m_transitions_per_cycle;
+    int m_buffer_size;
+    int m_recycle_latency;
+    std::string m_name;
+    std::map<std::string, std::string> m_cfg;
+    NodeID m_version;
+    Network* m_net_ptr;
+    MachineID m_machineID;
+    bool m_is_blocking;
+    std::map<Address, MessageBuffer*> m_block_map;
+    typedef std::vector<MessageBuffer*> MsgVecType;
+    typedef std::map< Address, MsgVecType* > WaitingBufType;
+    WaitingBufType m_waiting_buffers;
+    int m_max_in_port_rank;
+    int m_cur_in_port_rank;
+    int m_number_of_TBEs;
 };
 
 #endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__

diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index f07e521d35a1996b8e34544cb788f1a214580730..1547f992bd60839120ac2a189dcf8896cf9dcc5c 100644 (file)
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -33,6 +33,7 @@ import slicc.generate.html as html
 import re
 
 python_class_map = {"int": "Int",
+                    "uint32_t" : "UInt32",
                     "std::string": "String",
                     "bool": "Bool",
                     "CacheMemory": "RubyCache",
@@ -261,7 +262,6 @@ class $c_ident : public AbstractController
     void wakeUpAllBuffers();
     void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
     void print(std::ostream& out) const;
-    void printConfig(std::ostream& out) const;
     void wakeup();
     void printStats(std::ostream& out) const;
     void clearStats();
@@ -285,8 +285,6 @@ private:
                 code('${{param.type_ast.type}} m_${{param.ident}};')
 
         code('''
-int m_number_of_TBEs;
-
 TransitionResult doTransition(${ident}_Event event,
 ''')
 
@@ -319,21 +317,6 @@ TransitionResult doTransitionWorker(${ident}_Event event,
         code('''
                                     const Address& addr);
 
-std::string m_name;
-int m_transitions_per_cycle;
-int m_buffer_size;
-int m_recycle_latency;
-std::map<std::string, std::string> m_cfg;
-NodeID m_version;
-Network* m_net_ptr;
-MachineID m_machineID;
-bool m_is_blocking;
-std::map<Address, MessageBuffer*> m_block_map;
-typedef std::vector<MessageBuffer*> MsgVecType;
-typedef std::map< Address, MsgVecType* > WaitingBufType;
-WaitingBufType m_waiting_buffers;
-int m_max_in_port_rank;
-int m_cur_in_port_rank;
 static ${ident}_ProfileDumper s_profileDumper;
 ${ident}_Profiler m_profiler;
 static int m_num_controllers;
@@ -465,12 +448,6 @@ stringstream ${ident}_transitionComment;
 $c_ident::$c_ident(const Params *p)
     : AbstractController(p)
 {
-    m_version = p->version;
-    m_transitions_per_cycle = p->transitions_per_cycle;
-    m_buffer_size = p->buffer_size;
-    m_recycle_latency = p->recycle_latency;
-    m_number_of_TBEs = p->number_of_TBEs;
-    m_is_blocking = false;
     m_name = "${ident}";
 ''')
         #
@@ -574,14 +551,9 @@ $c_ident::init()
                     elif var.ident.find("mandatoryQueue") < 0:
                         th = var.get("template", "")
                         expr = "%s  = new %s%s" % (vid, vtype.c_ident, th)
-
                         args = ""
                         if "non_obj" not in vtype and not vtype.isEnumeration:
-                            if expr.find("TBETable") >= 0:
-                                args = "m_number_of_TBEs"
-                            else:
-                                args = var.get("constructor_hack", "")
-
+                            args = var.get("constructor", "")
                         code('$expr($args);')
 
                     code('assert($vid != NULL);')
@@ -825,16 +797,6 @@ $c_ident::print(ostream& out) const
     out << "[$c_ident " << m_version << "]";
 }
 
-void
-$c_ident::printConfig(ostream& out) const
-{
-    out << "$c_ident config: " << m_name << endl;
-    out << "  version: " << m_version << endl;
-    map<string, string>::const_iterator it;
-    for (it = m_cfg.begin(); it != m_cfg.end(); it++)
-        out << "  " << it->first << ": " << it->second << endl;
-}
-
 void
 $c_ident::printStats(ostream& out) const
 {