arm: Fix decoding of PMXEVTYPER_EL0 and PMCCFILTR_EL0

The aarch64 system register decoder is currently not decoding
PMXEVTYPER_EL0 and PMCCFILTR_EL0 correctly. This changeset updates the
decoder so that they are decoded using the values in table C5-6 in ARM
DDI 0478A.c.

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index d8c257f08b5f6ae07594fb65cce09e4b80c93ed4..2ad25627374a3c050cfb651a94153136c52f00f0 100644 (file)
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -3177,7 +3177,7 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
                       case 0:
                         return MISCREG_PMCCNTR_EL0;
                       case 1:
-                        return MISCREG_PMCCFILTR_EL0;
+                        return MISCREG_PMXEVTYPER_EL0;
                       case 2:
                         return MISCREG_PMXEVCNTR_EL0;
                     }
@@ -3434,6 +3434,11 @@ decodeAArch64SysReg(unsigned op0, unsigned op1,
                         return MISCREG_PMEVTYPER5_EL0;
                     }
                     break;
+                  case 15:
+                    switch (op2) {
+                      case 7:
+                        return MISCREG_PMCCFILTR_EL0;
+                    }
                 }
                 break;
               case 4: