update slides

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 037265a761dbf8281c883a11624d9774800110cf..b0e6cd9921dabcbdf950beb052d57792efedb4e0 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -142,8 +142,8 @@
  \begin{itemize}
    \item Same register(s) can have multiple "interpretations"\vspace{10pt}
    \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops\vspace{10pt}
-   \item (32-bit GREV plus 4-wide 32-bit SIMD plus 32-bit GREVI)\vspace{10pt}
-   \item 32-bit op followed by 16-bit op w/ 2x VL, 1/2 predicated\vspace{10pt}
+   \item (32-bit GREV plus 4-wide 32-bit SIMD plus 32-bit GREV)\vspace{10pt}
+   \item Same register(s) can be offset (no need for VSLIDE)\vspace{10pt}
   \end{itemize}
   Note:\vspace{10pt}
    \begin{itemize}