* config/tc-mips.c (append_insn): Remove now-redundant nops != 0
authorRichard Sandiford <rdsandiford@googlemail.com>
Wed, 9 Mar 2005 09:17:41 +0000 (09:17 +0000)
committerRichard Sandiford <rdsandiford@googlemail.com>
Wed, 9 Mar 2005 09:17:41 +0000 (09:17 +0000)
check from branch delay code.  Remove unnecessary check for branches.

gas/ChangeLog
gas/config/tc-mips.c

index e2efc11e6c7aa329397dfec6afc930bdab87a02e..340090ab6ad9f4d071e15756081d633ef1fbca21 100644 (file)
@@ -1,3 +1,8 @@
+2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
+
+       * config/tc-mips.c (append_insn): Remove now-redundant nops != 0
+       check from branch delay code.  Remove unnecessary check for branches.
+
 2005-03-09  Richard Sandiford  <rsandifo@redhat.com>
 
        * config/tc-mips.c (dummy_opcode): Delete.
index 5a3dedaa55b2290adfbfd42557c7860aeba9d845..77b5535beb92bb5b3737aa9042b65b5457f8e305 100644 (file)
@@ -2472,9 +2472,6 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
              /* If we have seen .set volatile or .set nomove, don't
                 optimize.  */
              || mips_opts.nomove != 0
-             /* If we had to emit any NOP instructions, then we
-                already know we can not swap.  */
-             || nops != 0
              /* We can't swap if the previous instruction's position
                 is fixed.  */
              || history[0].fixed_p
@@ -2536,11 +2533,6 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
                   /* Itbl support may require additional care here.  */
                  && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
                  && ! cop_mem_interlocks)
-             /* We can not swap with a branch instruction.  */
-             || (prev_pinfo
-                 & (INSN_UNCOND_BRANCH_DELAY
-                    | INSN_COND_BRANCH_DELAY
-                    | INSN_COND_BRANCH_LIKELY))
              /* We do not swap with a trap instruction, since it
                 complicates trap handlers to have the trap
                 instruction be in a delay slot.  */