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intel/fs/nir: Setup immediates based on type in i2b and f2b
author
Jason Ekstrand
<jason.ekstrand@intel.com>
Fri, 3 Nov 2017 01:30:04 +0000
(18:30 -0700)
committer
Jason Ekstrand
<jason.ekstrand@intel.com>
Tue, 7 Nov 2017 18:41:24 +0000
(10:41 -0800)
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
src/intel/compiler/brw_fs_nir.cpp
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diff --git
a/src/intel/compiler/brw_fs_nir.cpp
b/src/intel/compiler/brw_fs_nir.cpp
index 2f47b0253b2be70c553e88d6c0a9e6ae470f6271..99e652a4a0c513974d216b0b0c1b0bcb4299e79f 100644
(file)
--- a/
src/intel/compiler/brw_fs_nir.cpp
+++ b/
src/intel/compiler/brw_fs_nir.cpp
@@
-1125,12
+1125,13
@@
fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
if (instr->op == nir_op_f2b) {
zero = vgrf(glsl_type::double_type);
tmp = vgrf(glsl_type::double_type);
+ bld.MOV(zero, setup_imm_df(bld, 0.0));
} else {
zero = vgrf(glsl_type::int64_t_type);
tmp = vgrf(glsl_type::int64_t_type);
+ bld.MOV(zero, brw_imm_q(0));
}
- bld.MOV(zero, setup_imm_df(bld, 0.0));
/* A SIMD16 execution needs to be split in two instructions, so use
* a vgrf instead of the flag register as dst so instruction splitting
* works