fix LDST immed using EXTRA2 not EXTRA3 in tests to make

room for Pack/Unpack

diff --git a/src/openpower/decoder/isa/test_caller_svp64.py b/src/openpower/decoder/isa/test_caller_svp64.py
index 98d78b0bf32baa727c27a6082e1726ed4f7f5541..3bcaac46359098e728c6995af0ad9cda1cbf61eb 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64.py
+++ b/src/openpower/decoder/isa/test_caller_svp64.py
@@ -27,8 +27,8 @@ class DecoderTestCase(FHDLTestCase):
                         "addi 17, 0, 0x0008",
                         "addi 4, 0, 0x1234",
                         "addi 5, 0, 0x1235",
-                        "sv.stw *4, 0(*1)",
-                        "sv.lwz *8, 0(*1)"]
+                        "sv.stw *4, 0(*16)",
+                        "sv.lwz *8, 0(*16)"]
         """
         lst = SVP64Asm(["addi 16, 0, 0x0010",
                         "addi 17, 0, 0x0008",

diff --git a/src/openpower/decoder/isa/test_caller_svp64_ldst.py b/src/openpower/decoder/isa/test_caller_svp64_ldst.py
index c4be99d9d0e2285d01e8f2c754f9852e3b5b4238..f1cf58f2ad33cde340641f4218528e48cc11f2fc 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_ldst.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_ldst.py
@@ -30,12 +30,12 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.fpr(i), SelectableInt(expected[i], 64))
 
     def test_sv_load_store_elementstride(self):
-        """>>> lst = ["addi 1, 0, 0x0010",
-                        "addi 2, 0, 0x0008",
+        """>>> lst = ["addi 2, 0, 0x0010",
+                        "addi 3, 0, 0x0008",
                         "addi 4, 0, 0x1234",
                         "addi 5, 0, 0x1235",
-                        "sv.stw/els *4, 16(1)",
-                        "sv.lwz/els *8, 16(1)"]
+                        "sv.stw/els *4, 16(2)",
+                        "sv.lwz/els *8, 16(2)"]
 
         note: element stride mode is only enabled when RA is a scalar
         and when the immediate is non-zero
@@ -44,12 +44,12 @@ class DecoderTestCase(FHDLTestCase):
         for i in range(VL):
             EA = (RA|0) + EXTS(D) * i
         """
-        lst = SVP64Asm(["addi 1, 0, 0x0010",
-                        "addi 2, 0, 0x0008",
+        lst = SVP64Asm(["addi 2, 0, 0x0010",
+                        "addi 3, 0, 0x0008",
                         "addi 4, 0, 0x1234",
                         "addi 5, 0, 0x1235",
-                        "sv.stw/els *4, 24(1)",  # scalar r1 + 16 + 24*offs
-                        "sv.lwz/els *8, 24(1)"]) # scalar r1 + 16 + 24*offs
+                        "sv.stw/els *4, 24(2)",  # scalar r1 + 16 + 24*offs
+                        "sv.lwz/els *8, 24(2)"]) # scalar r1 + 16 + 24*offs
         lst = list(lst)
 
         # SVSTATE (in this case, VL=2)
@@ -122,11 +122,11 @@ class DecoderTestCase(FHDLTestCase):
         """>>> lst = ["addi 1, 0, 0x0010",
                         "addi 2, 0, 0x0004",
                         "addi 3, 0, 0x0002",
-                        "addi 5, 0, 0x101",
-                        "addi 6, 0, 0x202",
-                        "addi 7, 0, 0x303",
-                        "addi 8, 0, 0x404",
-                        "sv.stw *5, 0(1)",
+                        "addi 4, 0, 0x101",
+                        "addi 5, 0, 0x202",
+                        "addi 6, 0, 0x303",
+                        "addi 7, 0, 0x404",
+                        "sv.stw *4, 0(1)",
                         "sv.lwzsh *12, 4(1), 2"]
 
         shifted LD is computed as:
@@ -135,11 +135,11 @@ class DecoderTestCase(FHDLTestCase):
         """
         lst = SVP64Asm(["addi 1, 0, 0x0010",
                         "addi 2, 0, 0x0000",
-                        "addi 5, 0, 0x101",
-                        "addi 6, 0, 0x202",
-                        "addi 7, 0, 0x303",
-                        "addi 8, 0, 0x404",
-                        "sv.stw *5, 0(1)",  # scalar r1 + 0 + wordlen*offs
+                        "addi 4, 0, 0x101",
+                        "addi 5, 0, 0x202",
+                        "addi 6, 0, 0x303",
+                        "addi 7, 0, 0x404",
+                        "sv.stw *4, 0(1)",  # scalar r1 + 0 + wordlen*offs
                         "sv.lwzsh *12, 4(1), 2"]) # bit-reversed
         lst = list(lst)
 
@@ -158,10 +158,10 @@ class DecoderTestCase(FHDLTestCase):
                                    (24, 0x040400000303)])
             print(sim.gpr(1))
             # from STs
-            self.assertEqual(sim.gpr(5), SelectableInt(0x101, 64))
-            self.assertEqual(sim.gpr(6), SelectableInt(0x202, 64))
-            self.assertEqual(sim.gpr(7), SelectableInt(0x303, 64))
-            self.assertEqual(sim.gpr(8), SelectableInt(0x404, 64))
+            self.assertEqual(sim.gpr(4), SelectableInt(0x101, 64))
+            self.assertEqual(sim.gpr(5), SelectableInt(0x202, 64))
+            self.assertEqual(sim.gpr(6), SelectableInt(0x303, 64))
+            self.assertEqual(sim.gpr(7), SelectableInt(0x404, 64))
             # r1=0x10, RC=0, offs=4: contents of memory expected at:
             #    element 0:   EA = r1 + 0b00*4 => 0x10 + 0b00*4 => 0x10
             #    element 1:   EA = r1 + 0b01*4 => 0x10 + 0b01*4 => 0x18
@@ -181,11 +181,11 @@ class DecoderTestCase(FHDLTestCase):
         """>>> lst = ["addi 1, 0, 0x0010",
                         "addi 2, 0, 0x0004",
                         "addi 3, 0, 0x0002",
-                        "addi 5, 0, 0x101",
-                        "addi 6, 0, 0x202",
-                        "addi 7, 0, 0x303",
-                        "addi 8, 0, 0x404",
-                        "sv.std *5, 0(1)",
+                        "addi 4, 0, 0x101",
+                        "addi 5, 0, 0x202",
+                        "addi 6, 0, 0x303",
+                        "addi 7, 0, 0x404",
+                        "sv.std *4, 0(1)",
                         "sv.lfdbr *12, 4(1), 2"]
 
         shifted LD is computed as:
@@ -194,11 +194,11 @@ class DecoderTestCase(FHDLTestCase):
         """
         lst = SVP64Asm(["addi 1, 0, 0x0010",
                         "addi 2, 0, 0x0000",
-                        "addi 5, 0, 0x101",
-                        "addi 6, 0, 0x202",
-                        "addi 7, 0, 0x303",
-                        "addi 8, 0, 0x404",
-                        "sv.std *5, 0(1)", # scalar r1 + 0 + wordlen*offs
+                        "addi 4, 0, 0x101",
+                        "addi 5, 0, 0x202",
+                        "addi 6, 0, 0x303",
+                        "addi 7, 0, 0x404",
+                        "sv.std *4, 0(1)", # scalar r1 + 0 + wordlen*offs
                         "sv.lfdsh *12, 8(1), 2"]) # shifted
         lst = list(lst)
 
@@ -223,10 +223,10 @@ class DecoderTestCase(FHDLTestCase):
                                   ])
             print(sim.gpr(1))
             # from STs
-            self.assertEqual(sim.gpr(5), SelectableInt(0x101, 64))
-            self.assertEqual(sim.gpr(6), SelectableInt(0x202, 64))
-            self.assertEqual(sim.gpr(7), SelectableInt(0x303, 64))
-            self.assertEqual(sim.gpr(8), SelectableInt(0x404, 64))
+            self.assertEqual(sim.gpr(4), SelectableInt(0x101, 64))
+            self.assertEqual(sim.gpr(5), SelectableInt(0x202, 64))
+            self.assertEqual(sim.gpr(6), SelectableInt(0x303, 64))
+            self.assertEqual(sim.gpr(7), SelectableInt(0x404, 64))
             # r1=0x10, RC=0, offs=4: contents of memory expected at:
             #    element 0:   EA = r1 + bitrev(0b00)*4 => 0x10 + 0b00*4 => 0x10
             #    element 1:   EA = r1 + bitrev(0b01)*4 => 0x10 + 0b10*4 => 0x18