boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000
-console=/gem5/dist/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
init_param=0
-kernel=/gem5/dist/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/gem5/dist/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
[system.cpu0]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu0.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu0.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu0.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
+[system.cpu0.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu0.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
[system.cpu1]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu1.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu1.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu1.interrupts
isa=system.cpu1.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu1.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
+[system.cpu1.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu1.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
[system.disk0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
+Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:09:21
-gem5 started Jan 4 2013 21:41:13
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:29:25
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-info: Launching CPU 1 @ 107840000
-Exiting @ tick 1897857556000 because m5_exit instruction encountered
+info: Launching CPU 1 @ 107825000
+Exiting @ tick 1901719660500 because m5_exit instruction encountered
sim_ticks 1901719660500 # Number of ticks simulated
final_tick 1901719660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 128809 # Simulator instruction rate (inst/s)
-host_op_rate 128809 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4317556960 # Simulator tick rate (ticks/s)
-host_mem_usage 340604 # Number of bytes of host memory used
-host_seconds 440.46 # Real time elapsed on the host
+host_inst_rate 97307 # Simulator instruction rate (inst/s)
+host_op_rate 97307 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3261646555 # Simulator tick rate (ticks/s)
+host_mem_usage 383552 # Number of bytes of host memory used
+host_seconds 583.06 # Real time elapsed on the host
sim_insts 56735321 # Number of instructions simulated
sim_ops 56735321 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 857600 # Number of bytes read from this memory
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.cpu0.branchPred.lookups 12372868 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 10433314 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 330387 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 8151024 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 5278103 # Number of BTB hits
+system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.branchPred.BTBHitPct 64.753864 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 784011 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 32544 # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.numCycles 101814962 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 12372868 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 10433314 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 330387 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 8151024 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 5278103 # Number of BTB hits
-system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 784011 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 32544 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 24931217 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 63627814 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 12372868 # Number of branches that fetch encountered
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.branchPred.lookups 2617746 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 2161338 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 77903 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 1516620 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 873996 # Number of BTB hits
+system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.branchPred.BTBHitPct 57.627883 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 182212 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 8242 # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.numCycles 16039611 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 2617746 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 2161338 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 77903 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 1516620 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 873996 # Number of BTB hits
-system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 182212 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 8242 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 6032367 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 12375417 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 2617746 # Number of branches that fetch encountered
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000
-console=/gem5/dist/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
init_param=0
-kernel=/gem5/dist/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/gem5/dist/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
[system.disk0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
+Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:09:21
-gem5 started Jan 4 2013 21:39:46
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:39:31
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1854349611000 because m5_exit instruction encountered
+Exiting @ tick 1854344296500 because m5_exit instruction encountered
sim_ticks 1854344296500 # Number of ticks simulated
final_tick 1854344296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 131278 # Simulator instruction rate (inst/s)
-host_op_rate 131278 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4595190559 # Simulator tick rate (ticks/s)
-host_mem_usage 336376 # Number of bytes of host memory used
-host_seconds 403.54 # Real time elapsed on the host
+host_inst_rate 90928 # Simulator instruction rate (inst/s)
+host_op_rate 90928 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3182808238 # Simulator tick rate (ticks/s)
+host_mem_usage 379332 # Number of bytes of host memory used
+host_seconds 582.61 # Real time elapsed on the host
sim_insts 52976017 # Number of instructions simulated
sim_ops 52976017 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 964864 # Number of bytes read from this memory
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
+system.cpu.branchPred.lookups 13851594 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11614390 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 401305 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9533712 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 5819078 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 61.036855 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 909714 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 39020 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 108725026 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 13851594 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 11614390 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 401305 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 9533712 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 5819078 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 909714 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 39020 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 28116472 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 70876145 # Number of instructions fetch has processed
system.cpu.fetch.Branches 13851594 # Number of branches that fetch encountered
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000
-console=/arm/scratch/sysexplr/dist/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
init_param=0
-kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/arm/scratch/sysexplr/dist/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
[system.cpu0]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
[system.cpu1]
type=TimingSimpleCPU
children=dtb interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
[system.cpu2]
type=DerivO3CPU
-children=dtb fuPool interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dtb fuPool interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu2.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu2.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu2.interrupts
isa=system.cpu2.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu2.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
wbWidth=8
workload=
+[system.cpu2.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu2.dtb]
type=AlphaTLB
size=64
[system.disk0.image.child]
type=RawDiskImage
-image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/arm/scratch/sysexplr/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/arm/scratch/sysexplr/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
+Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 11 2012 16:31:37
-gem5 started Dec 11 2012 16:31:53
-gem5 executing on e103721-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:29:38
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
info: Entering event queue @ 10452679000. Starting simulation...
switching cpus
-info: Entering event queue @ 10452683500. Starting simulation...
+info: Entering event queue @ 10452682000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 11452683500. Starting simulation...
+info: Entering event queue @ 11452682000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 12452683500. Starting simulation...
+info: Entering event queue @ 12452682000. Starting simulation...
+info: Entering event queue @ 12452693500. Starting simulation...
switching cpus
-info: Entering event queue @ 12452684500. Starting simulation...
+info: Entering event queue @ 12452696000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 13452684500. Starting simulation...
+info: Entering event queue @ 13452696000. Starting simulation...
switching cpus
-info: Entering event queue @ 13452690000. Starting simulation...
+info: Entering event queue @ 13452709500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 14452690000. Starting simulation...
+info: Entering event queue @ 14452709500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 15452690000. Starting simulation...
+info: Entering event queue @ 15452709500. Starting simulation...
+info: Entering event queue @ 15452713500. Starting simulation...
switching cpus
-info: Entering event queue @ 15452691000. Starting simulation...
+info: Entering event queue @ 15452714500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 16452691000. Starting simulation...
+info: Entering event queue @ 16452714500. Starting simulation...
switching cpus
-info: Entering event queue @ 16452704500. Starting simulation...
+info: Entering event queue @ 16452717000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 17452704500. Starting simulation...
+info: Entering event queue @ 17452717000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 18452704500. Starting simulation...
+info: Entering event queue @ 18452717000. Starting simulation...
+info: Entering event queue @ 18452728500. Starting simulation...
switching cpus
-info: Entering event queue @ 18452705500. Starting simulation...
+info: Entering event queue @ 18452732000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 19452705500. Starting simulation...
-info: Entering event queue @ 19452711000. Starting simulation...
+info: Entering event queue @ 19452732000. Starting simulation...
+info: Entering event queue @ 19452741000. Starting simulation...
switching cpus
-info: Entering event queue @ 19452715500. Starting simulation...
+info: Entering event queue @ 19452745500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 20452715500. Starting simulation...
+info: Entering event queue @ 20452745500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 21452715500. Starting simulation...
+info: Entering event queue @ 21452745500. Starting simulation...
switching cpus
-info: Entering event queue @ 21452716000. Starting simulation...
+info: Entering event queue @ 21452746000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 22452716000. Starting simulation...
-info: Entering event queue @ 22452727500. Starting simulation...
+info: Entering event queue @ 22452746000. Starting simulation...
switching cpus
-info: Entering event queue @ 22452733000. Starting simulation...
+info: Entering event queue @ 22452748000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 23452733000. Starting simulation...
+info: Entering event queue @ 23452748000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 24452733000. Starting simulation...
+info: Entering event queue @ 24452748000. Starting simulation...
switching cpus
-info: Entering event queue @ 24452734000. Starting simulation...
+info: Entering event queue @ 24452750000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 25452734000. Starting simulation...
+info: Entering event queue @ 25452750000. Starting simulation...
+info: Entering event queue @ 25452773000. Starting simulation...
switching cpus
-info: Entering event queue @ 25452745500. Starting simulation...
+info: Entering event queue @ 25452778500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 26452745500. Starting simulation...
+info: Entering event queue @ 26452778500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 27452745500. Starting simulation...
+info: Entering event queue @ 27452778500. Starting simulation...
+info: Entering event queue @ 27452782500. Starting simulation...
switching cpus
-info: Entering event queue @ 27452746500. Starting simulation...
+info: Entering event queue @ 27452786000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 28452746500. Starting simulation...
-info: Entering event queue @ 28452758500. Starting simulation...
-info: Entering event queue @ 28452769000. Starting simulation...
+info: Entering event queue @ 28452786000. Starting simulation...
+info: Entering event queue @ 28452802500. Starting simulation...
switching cpus
-info: Entering event queue @ 28452773500. Starting simulation...
+info: Entering event queue @ 28452808000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 29452773500. Starting simulation...
+info: Entering event queue @ 29452808000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 30452773500. Starting simulation...
+info: Entering event queue @ 30452808000. Starting simulation...
switching cpus
-info: Entering event queue @ 30452992500. Starting simulation...
+info: Entering event queue @ 30452820500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 31452992500. Starting simulation...
+info: Entering event queue @ 31452820500. Starting simulation...
switching cpus
-info: Entering event queue @ 31452995500. Starting simulation...
+info: Entering event queue @ 31452823500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 32452995500. Starting simulation...
+info: Entering event queue @ 32452823500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 33452995500. Starting simulation...
+info: Entering event queue @ 33452823500. Starting simulation...
switching cpus
-info: Entering event queue @ 33452996500. Starting simulation...
+info: Entering event queue @ 33452824500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 34452996500. Starting simulation...
+info: Entering event queue @ 34452824500. Starting simulation...
switching cpus
-info: Entering event queue @ 34452999500. Starting simulation...
+info: Entering event queue @ 34452827500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 35452999500. Starting simulation...
+info: Entering event queue @ 35452827500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 36452999500. Starting simulation...
+info: Entering event queue @ 36452827500. Starting simulation...
switching cpus
-info: Entering event queue @ 36453000500. Starting simulation...
+info: Entering event queue @ 36452828500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 37453000500. Starting simulation...
+info: Entering event queue @ 37452828500. Starting simulation...
switching cpus
-info: Entering event queue @ 37453003500. Starting simulation...
+info: Entering event queue @ 37452831500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 38453003500. Starting simulation...
+info: Entering event queue @ 38452831500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 39453003500. Starting simulation...
+info: Entering event queue @ 39452831500. Starting simulation...
switching cpus
-info: Entering event queue @ 39453004500. Starting simulation...
+info: Entering event queue @ 39452832500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 40453004500. Starting simulation...
+info: Entering event queue @ 40452832500. Starting simulation...
switching cpus
-info: Entering event queue @ 40453007500. Starting simulation...
+info: Entering event queue @ 40452835500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 41453007500. Starting simulation...
+info: Entering event queue @ 41452835500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 42453007500. Starting simulation...
+info: Entering event queue @ 42452835500. Starting simulation...
switching cpus
-info: Entering event queue @ 42453008500. Starting simulation...
+info: Entering event queue @ 42452836500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 43453008500. Starting simulation...
+info: Entering event queue @ 43452836500. Starting simulation...
switching cpus
info: Entering event queue @ 43945335500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
info: Entering event queue @ 304757835500. Starting simulation...
switching cpus
-info: Entering event queue @ 304758059500. Starting simulation...
+info: Entering event queue @ 304758051500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 305758059500. Starting simulation...
+info: Entering event queue @ 305758051500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 306758059500. Starting simulation...
+info: Entering event queue @ 306758051500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 307758059500. Starting simulation...
+info: Entering event queue @ 307758051500. Starting simulation...
switching cpus
info: Entering event queue @ 308593773000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
info: Entering event queue @ 624093773500. Starting simulation...
switching cpus
-info: Entering event queue @ 624216549000. Starting simulation...
+info: Entering event queue @ 624218766000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 625216549000. Starting simulation...
+info: Entering event queue @ 625218766000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 626216549000. Starting simulation...
+info: Entering event queue @ 626218766000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 627216549000. Starting simulation...
+info: Entering event queue @ 627218766000. Starting simulation...
switching cpus
info: Entering event queue @ 627929709000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 1157273460500. Starting simulation...
switching cpus
-info: Entering event queue @ 1157273461500. Starting simulation...
+info: Entering event queue @ 1157273461000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1158273461500. Starting simulation...
+info: Entering event queue @ 1158273461000. Starting simulation...
switching cpus
-info: Entering event queue @ 1159361690000. Starting simulation...
+info: Entering event queue @ 1159361004000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1160361690000. Starting simulation...
+info: Entering event queue @ 1160361004000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1161361690000. Starting simulation...
+info: Entering event queue @ 1161361004000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1162361690000. Starting simulation...
+info: Entering event queue @ 1162361004000. Starting simulation...
switching cpus
-info: Entering event queue @ 1162361693000. Starting simulation...
+info: Entering event queue @ 1162361007000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1163361693000. Starting simulation...
+info: Entering event queue @ 1163361007000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1164361693000. Starting simulation...
+info: Entering event queue @ 1164361007000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1165361693000. Starting simulation...
+info: Entering event queue @ 1165361007000. Starting simulation...
switching cpus
-info: Entering event queue @ 1165361696000. Starting simulation...
+info: Entering event queue @ 1165361010000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1166361696000. Starting simulation...
+info: Entering event queue @ 1166361010000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1167361696000. Starting simulation...
+info: Entering event queue @ 1167361010000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1168361696000. Starting simulation...
+info: Entering event queue @ 1168361010000. Starting simulation...
switching cpus
info: Entering event queue @ 1168945335500. Starting simulation...
Switching CPUs...
info: Entering event queue @ 1755882835500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1756882835500. Starting simulation...
switching cpus
-info: Entering event queue @ 1756882836500. Starting simulation...
+info: Entering event queue @ 1756882835500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1757882836500. Starting simulation...
+info: Entering event queue @ 1757882835500. Starting simulation...
switching cpus
info: Entering event queue @ 1758789085500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 1768601585500. Starting simulation...
switching cpus
-info: Entering event queue @ 1768601586500. Starting simulation...
+info: Entering event queue @ 1768601735500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1769601586500. Starting simulation...
+info: Entering event queue @ 1769601735500. Starting simulation...
switching cpus
info: Entering event queue @ 1770507835500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1777414085500. Starting simulation...
switching cpus
-info: Entering event queue @ 1777414489000. Starting simulation...
+info: Entering event queue @ 1777414674000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1778414489000. Starting simulation...
+info: Entering event queue @ 1778414674000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1779414489000. Starting simulation...
+info: Entering event queue @ 1779414674000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1780414489000. Starting simulation...
+info: Entering event queue @ 1780414674000. Starting simulation...
switching cpus
info: Entering event queue @ 1781250023000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1819406274000. Starting simulation...
switching cpus
-info: Entering event queue @ 1819406280500. Starting simulation...
+info: Entering event queue @ 1819406403500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1820406280500. Starting simulation...
+info: Entering event queue @ 1820406403500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1821406280500. Starting simulation...
+info: Entering event queue @ 1821406403500. Starting simulation...
switching cpus
-info: Entering event queue @ 1821406281500. Starting simulation...
+info: Entering event queue @ 1821406404500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1822406281500. Starting simulation...
-info: Entering event queue @ 1822406288500. Starting simulation...
+info: Entering event queue @ 1822406404500. Starting simulation...
switching cpus
-info: Entering event queue @ 1822406293000. Starting simulation...
+info: Entering event queue @ 1822406407500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1823406293000. Starting simulation...
+info: Entering event queue @ 1823406407500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1824406293000. Starting simulation...
+info: Entering event queue @ 1824406407500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1825406293000. Starting simulation...
+info: Entering event queue @ 1825406407500. Starting simulation...
switching cpus
info: Entering event queue @ 1826171898000. Starting simulation...
Switching CPUs...
Switching CPUs...
Next CPU: AtomicSimpleCPU
info: Entering event queue @ 1829171898000. Starting simulation...
-info: Entering event queue @ 1829171911500. Starting simulation...
-info: Entering event queue @ 1829171916500. Starting simulation...
+info: Entering event queue @ 1829171913500. Starting simulation...
switching cpus
-info: Entering event queue @ 1829171921000. Starting simulation...
+info: Entering event queue @ 1829171918000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1830171921000. Starting simulation...
+info: Entering event queue @ 1830171918000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1831171921000. Starting simulation...
+info: Entering event queue @ 1831171918000. Starting simulation...
switching cpus
-info: Entering event queue @ 1831171922000. Starting simulation...
+info: Entering event queue @ 1831171920000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1832171922000. Starting simulation...
+info: Entering event queue @ 1832171920000. Starting simulation...
switching cpus
info: Entering event queue @ 1833007835500. Starting simulation...
Switching CPUs...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 1838914085500. Starting simulation...
+info: Entering event queue @ 1838914092000. Starting simulation...
switching cpus
-info: Entering event queue @ 1838914086500. Starting simulation...
+info: Entering event queue @ 1838914095500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1839914086500. Starting simulation...
+info: Entering event queue @ 1839914095500. Starting simulation...
+info: Entering event queue @ 1839914105000. Starting simulation...
switching cpus
-info: Entering event queue @ 1839914091000. Starting simulation...
+info: Entering event queue @ 1839914109500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1840914091000. Starting simulation...
+info: Entering event queue @ 1840914109500. Starting simulation...
sim_ticks 1841687115500 # Number of ticks simulated
final_tick 1841687115500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 299654 # Simulator instruction rate (inst/s)
-host_op_rate 299654 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 8001020229 # Simulator tick rate (ticks/s)
-host_mem_usage 317816 # Number of bytes of host memory used
-host_seconds 230.18 # Real time elapsed on the host
+host_inst_rate 216690 # Simulator instruction rate (inst/s)
+host_op_rate 216690 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5785819991 # Simulator tick rate (ticks/s)
+host_mem_usage 360768 # Number of bytes of host memory used
+host_seconds 318.31 # Real time elapsed on the host
sim_insts 68974794 # Number of instructions simulated
sim_ops 68974794 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 474496 # Number of bytes read from this memory
system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode
system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode
system.cpu1.kern.swap_context 0 # number of times the context was actually changed
+system.cpu2.branchPred.lookups 8367198 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 7675066 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 129021 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 6898028 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 5713360 # Number of BTB hits
+system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu2.branchPred.BTBHitPct 82.825990 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 286292 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 15213 # Number of incorrect RAS predictions.
system.cpu2.dtb.fetch_hits 0 # ITB hits
system.cpu2.dtb.fetch_misses 0 # ITB misses
system.cpu2.dtb.fetch_acv 0 # ITB acv
system.cpu2.numCycles 30553382 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.BPredUnit.lookups 8367198 # Number of BP lookups
-system.cpu2.BPredUnit.condPredicted 7675066 # Number of conditional branches predicted
-system.cpu2.BPredUnit.condIncorrect 129021 # Number of conditional branches incorrect
-system.cpu2.BPredUnit.BTBLookups 6898028 # Number of BTB lookups
-system.cpu2.BPredUnit.BTBHits 5713360 # Number of BTB hits
-system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.BPredUnit.usedRAS 286292 # Number of times the RAS was used to get a target.
-system.cpu2.BPredUnit.RASInCorrect 15213 # Number of incorrect RAS predictions.
system.cpu2.fetch.icacheStallCycles 8548806 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 34839646 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 8367198 # Number of branches that fetch encountered
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/gem5/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=DerivO3CPU
-children=checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=system.cpu.checker
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.checker]
type=O3Checker
children=dtb isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
warn: instruction 'mcr dccimvac' unimplemented
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
-warn: 5947838000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
-warn: 5955222500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
-warn: 5964126500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
-warn: 6000836500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
-warn: 6016396500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
+warn: 5659150500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
+warn: 5667223500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
+warn: 5701468500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
+warn: 5716197500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
+warn: 6234360500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
warn: LCD dual screen mode not supported
-warn: 51807341500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
+warn: 51492621000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
-warn: 2473965329500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
-warn: 2487749656500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2488961741500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
-warn: 2510016165000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2510533208500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2516263747000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
-warn: 2516773890500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
-warn: 2517336143500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
-warn: 2517337246000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
-warn: 2517887293500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
+warn: 2473679746000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
+warn: 2487454314500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2488664454000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
+warn: 2509713816500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2510230497500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2515951942000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
+warn: 2516461974500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
+warn: 2517022987000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
+warn: 2517024145000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
+warn: 2517574344000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
hack: be nice to actually delete the event here
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 5 2013 01:50:21
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:57:44
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2523517846500 because m5_exit instruction encountered
+Exiting @ tick 2523204701000 because m5_exit instruction encountered
sim_ticks 2523204701000 # Number of ticks simulated
final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 55288 # Simulator instruction rate (inst/s)
-host_op_rate 71140 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2313219719 # Simulator tick rate (ticks/s)
-host_mem_usage 409988 # Number of bytes of host memory used
-host_seconds 1090.78 # Real time elapsed on the host
+host_inst_rate 41110 # Simulator instruction rate (inst/s)
+host_op_rate 52896 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1720016966 # Simulator tick rate (ticks/s)
+host_mem_usage 452892 # Number of bytes of host memory used
+host_seconds 1466.97 # Real time elapsed on the host
sim_insts 60306320 # Number of instructions simulated
sim_ops 77597310 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.cpu.branchPred.lookups 14400111 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11483411 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 706790 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9536193 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7670918 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 80.440046 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1400062 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72720 # Number of incorrect RAS predictions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 14986991 # DTB read hits
system.cpu.numCycles 469830472 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 14400111 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 11483411 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 706790 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 9536193 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7670918 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1400062 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 72720 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/gem5/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu0.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu0.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu0.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
+[system.cpu0.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu0.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
[system.cpu1]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu1.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu1.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu1.interrupts
isa=system.cpu1.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu1.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
+[system.cpu1.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu1.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 5 2013 02:00:26
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 22:02:35
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2603185215000 because m5_exit instruction encountered
+Exiting @ tick 1092968826500 because m5_exit instruction encountered
sim_ticks 1092968826500 # Number of ticks simulated
final_tick 1092968826500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 64747 # Simulator instruction rate (inst/s)
-host_op_rate 83356 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1148881552 # Simulator tick rate (ticks/s)
-host_mem_usage 415112 # Number of bytes of host memory used
-host_seconds 951.33 # Real time elapsed on the host
+host_inst_rate 49884 # Simulator instruction rate (inst/s)
+host_op_rate 64220 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 885142778 # Simulator tick rate (ticks/s)
+host_mem_usage 458008 # Number of bytes of host memory used
+host_seconds 1234.79 # Real time elapsed on the host
sim_insts 61595972 # Number of instructions simulated
sim_ops 79298956 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.cpu0.branchPred.lookups 6012491 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 4585363 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 296577 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 3765620 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 2919015 # Number of BTB hits
+system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.branchPred.BTBHitPct 77.517514 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 674578 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 28863 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 8918270 # DTB read hits
system.cpu0.numCycles 67785734 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 6012491 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 4585363 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 296577 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 3765620 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 2919015 # Number of BTB hits
-system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 674578 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 28863 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 11763968 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 32049970 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 6012491 # Number of branches that fetch encountered
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.branchPred.lookups 8781590 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 7165099 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 410272 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 5784510 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 4949628 # Number of BTB hits
+system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.branchPred.BTBHitPct 85.566937 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 773605 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 42847 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 42721233 # DTB read hits
system.cpu1.numCycles 406854445 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 8781590 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 7165099 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 410272 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 5784510 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 4949628 # Number of BTB hits
-system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 773605 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 42847 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 18987687 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 60514486 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 8781590 # Number of branches that fetch encountered
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/gem5/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 5 2013 01:42:51
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:42:21
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2523517846500 because m5_exit instruction encountered
+Exiting @ tick 2523204701000 because m5_exit instruction encountered
sim_ticks 2523204701000 # Number of ticks simulated
final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 64094 # Simulator instruction rate (inst/s)
-host_op_rate 82471 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2681679652 # Simulator tick rate (ticks/s)
-host_mem_usage 409992 # Number of bytes of host memory used
-host_seconds 940.90 # Real time elapsed on the host
+host_inst_rate 50114 # Simulator instruction rate (inst/s)
+host_op_rate 64483 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2096764175 # Simulator tick rate (ticks/s)
+host_mem_usage 452888 # Number of bytes of host memory used
+host_seconds 1203.38 # Real time elapsed on the host
sim_insts 60306320 # Number of instructions simulated
sim_ops 77597310 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.cpu.branchPred.lookups 14400111 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11483411 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 706790 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9536193 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7670918 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 80.440046 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1400062 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72720 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 51212683 # DTB read hits
system.cpu.numCycles 469830472 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 14400111 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 11483411 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 706790 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 9536193 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7670918 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1400062 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 72720 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/gem5/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
[system.cpu1]
type=TimingSimpleCPU
children=dtb interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
[system.cpu2]
type=DerivO3CPU
-children=dtb fuPool interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dtb fuPool interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu2.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu2.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu2.interrupts
isa=system.cpu2.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu2.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
wbWidth=8
workload=
+[system.cpu2.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu2.dtb]
type=ArmTLB
children=walker
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 5 2013 02:09:50
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 22:03:06
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
info: Entering event queue @ 3000001000. Starting simulation...
switching cpus
-info: Entering event queue @ 3000008500. Starting simulation...
+info: Entering event queue @ 3000004000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 4000008500. Starting simulation...
+info: Entering event queue @ 4000004000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 5000008500. Starting simulation...
+info: Entering event queue @ 5000004000. Starting simulation...
switching cpus
-info: Entering event queue @ 5000009000. Starting simulation...
+info: Entering event queue @ 5000004500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 6000009000. Starting simulation...
+info: Entering event queue @ 6000004500. Starting simulation...
switching cpus
-info: Entering event queue @ 6000041500. Starting simulation...
+info: Entering event queue @ 6000011000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 7000041500. Starting simulation...
+info: Entering event queue @ 7000011000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 8000041500. Starting simulation...
+info: Entering event queue @ 8000011000. Starting simulation...
switching cpus
-info: Entering event queue @ 8000042500. Starting simulation...
+info: Entering event queue @ 8000065000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 9000042500. Starting simulation...
-info: Entering event queue @ 9000050500. Starting simulation...
-info: Entering event queue @ 9000061000. Starting simulation...
+info: Entering event queue @ 9000065000. Starting simulation...
+info: Entering event queue @ 9000075500. Starting simulation...
switching cpus
-info: Entering event queue @ 9000065500. Starting simulation...
+info: Entering event queue @ 9000080000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
+info: Entering event queue @ 10000080000. Starting simulation...
switching cpus
-info: Entering event queue @ 10000065500. Starting simulation...
+info: Entering event queue @ 10000082500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 11000065500. Starting simulation...
+info: Entering event queue @ 11000082500. Starting simulation...
switching cpus
-info: Entering event queue @ 11000066500. Starting simulation...
+info: Entering event queue @ 11000084500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 12000066500. Starting simulation...
-info: Entering event queue @ 12000080000. Starting simulation...
-switching cpus
info: Entering event queue @ 12000084500. Starting simulation...
+switching cpus
+info: Entering event queue @ 12000089500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 13000084500. Starting simulation...
+info: Entering event queue @ 13000089500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 14000084500. Starting simulation...
+info: Entering event queue @ 14000089500. Starting simulation...
switching cpus
-info: Entering event queue @ 14000088000. Starting simulation...
+info: Entering event queue @ 14000090500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 15000088000. Starting simulation...
+info: Entering event queue @ 15000090500. Starting simulation...
switching cpus
-info: Entering event queue @ 15000331000. Starting simulation...
+info: Entering event queue @ 15000095000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 16000331000. Starting simulation...
+info: Entering event queue @ 16000095000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 17000331000. Starting simulation...
+info: Entering event queue @ 17000095000. Starting simulation...
switching cpus
-info: Entering event queue @ 17000332000. Starting simulation...
+info: Entering event queue @ 17000096000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 18000332000. Starting simulation...
-info: Entering event queue @ 26175972000. Starting simulation...
-info: Entering event queue @ 26175979000. Starting simulation...
+info: Entering event queue @ 18000096000. Starting simulation...
+info: Entering event queue @ 26044720500. Starting simulation...
+info: Entering event queue @ 26044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 26175983500. Starting simulation...
+info: Entering event queue @ 26044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 27175983500. Starting simulation...
+info: Entering event queue @ 27044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 28175983500. Starting simulation...
+info: Entering event queue @ 28044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 29175983500. Starting simulation...
-info: Entering event queue @ 36175972000. Starting simulation...
-info: Entering event queue @ 36175979000. Starting simulation...
+info: Entering event queue @ 29044727500. Starting simulation...
+info: Entering event queue @ 36044720500. Starting simulation...
+info: Entering event queue @ 36044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 36175983500. Starting simulation...
+info: Entering event queue @ 36044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 37175983500. Starting simulation...
+info: Entering event queue @ 37044727500. Starting simulation...
switching cpus
-info: Entering event queue @ 37175984000. Starting simulation...
+info: Entering event queue @ 37044728000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 38175984000. Starting simulation...
-info: Entering event queue @ 38175999500. Starting simulation...
+info: Entering event queue @ 38044728000. Starting simulation...
+info: Entering event queue @ 38044743500. Starting simulation...
switching cpus
-info: Entering event queue @ 38176040500. Starting simulation...
+info: Entering event queue @ 38044784500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 39176040500. Starting simulation...
+info: Entering event queue @ 39044784500. Starting simulation...
switching cpus
-info: Entering event queue @ 39176113500. Starting simulation...
+info: Entering event queue @ 39044856000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 40176113500. Starting simulation...
+info: Entering event queue @ 40044856000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 41176113500. Starting simulation...
+info: Entering event queue @ 41044856000. Starting simulation...
switching cpus
-info: Entering event queue @ 41176114500. Starting simulation...
+info: Entering event queue @ 41044857500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 42176114500. Starting simulation...
+info: Entering event queue @ 42044857500. Starting simulation...
switching cpus
-info: Entering event queue @ 42176477500. Starting simulation...
+info: Entering event queue @ 42045164500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
+info: Entering event queue @ 43045164500. Starting simulation...
switching cpus
-info: Entering event queue @ 43176477500. Starting simulation...
+info: Entering event queue @ 43045165500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 44176477500. Starting simulation...
+info: Entering event queue @ 44045165500. Starting simulation...
switching cpus
-info: Entering event queue @ 44176479000. Starting simulation...
+info: Entering event queue @ 44045166000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 45176479000. Starting simulation...
-info: Entering event queue @ 45176488000. Starting simulation...
+info: Entering event queue @ 45045166000. Starting simulation...
switching cpus
-info: Entering event queue @ 45176492500. Starting simulation...
+info: Entering event queue @ 45045171000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 46176492500. Starting simulation...
+info: Entering event queue @ 46045171000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 47176492500. Starting simulation...
-info: Entering event queue @ 47176497000. Starting simulation...
+info: Entering event queue @ 47045171000. Starting simulation...
switching cpus
-info: Entering event queue @ 47176499500. Starting simulation...
+info: Entering event queue @ 47045181500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 48176499500. Starting simulation...
-info: Entering event queue @ 48176506500. Starting simulation...
-info: Entering event queue @ 48176516500. Starting simulation...
-info: Entering event queue @ 48176521000. Starting simulation...
+info: Entering event queue @ 48045181500. Starting simulation...
switching cpus
-info: Entering event queue @ 48176522000. Starting simulation...
+info: Entering event queue @ 48045187000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 49176522000. Starting simulation...
+info: Entering event queue @ 49045187000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 50176522000. Starting simulation...
+info: Entering event queue @ 50045187000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 51176522000. Starting simulation...
-info: Entering event queue @ 56175972000. Starting simulation...
-info: Entering event queue @ 56175979000. Starting simulation...
+info: Entering event queue @ 51045187000. Starting simulation...
+info: Entering event queue @ 56044720500. Starting simulation...
+info: Entering event queue @ 56044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 56175983500. Starting simulation...
+info: Entering event queue @ 56044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 57175983500. Starting simulation...
+info: Entering event queue @ 57044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 58175983500. Starting simulation...
+info: Entering event queue @ 58044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 59175983500. Starting simulation...
-info: Entering event queue @ 66175972000. Starting simulation...
-info: Entering event queue @ 66175979000. Starting simulation...
+info: Entering event queue @ 59044727500. Starting simulation...
+info: Entering event queue @ 66044720500. Starting simulation...
+info: Entering event queue @ 66044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 66175983500. Starting simulation...
+info: Entering event queue @ 66044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 67175983500. Starting simulation...
+info: Entering event queue @ 67044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 68175983500. Starting simulation...
+info: Entering event queue @ 68044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 69175983500. Starting simulation...
-info: Entering event queue @ 76175972000. Starting simulation...
-info: Entering event queue @ 76175979000. Starting simulation...
+info: Entering event queue @ 69044727500. Starting simulation...
+info: Entering event queue @ 76044720500. Starting simulation...
+info: Entering event queue @ 76044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 76175983500. Starting simulation...
+info: Entering event queue @ 76044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 77175983500. Starting simulation...
+info: Entering event queue @ 77044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 78175983500. Starting simulation...
+info: Entering event queue @ 78044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 79175983500. Starting simulation...
-info: Entering event queue @ 86175972000. Starting simulation...
-info: Entering event queue @ 86175979000. Starting simulation...
+info: Entering event queue @ 79044727500. Starting simulation...
+info: Entering event queue @ 86044720500. Starting simulation...
+info: Entering event queue @ 86044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 86175983500. Starting simulation...
+info: Entering event queue @ 86044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 87175983500. Starting simulation...
+info: Entering event queue @ 87044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 88175983500. Starting simulation...
+info: Entering event queue @ 88044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 89175983500. Starting simulation...
-info: Entering event queue @ 96175973000. Starting simulation...
-info: Entering event queue @ 96175982000. Starting simulation...
+info: Entering event queue @ 89044727500. Starting simulation...
+info: Entering event queue @ 96044720500. Starting simulation...
+info: Entering event queue @ 96044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 96175986500. Starting simulation...
+info: Entering event queue @ 96044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 97175986500. Starting simulation...
+info: Entering event queue @ 97044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 98175986500. Starting simulation...
+info: Entering event queue @ 98044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 99175986500. Starting simulation...
-info: Entering event queue @ 106175972000. Starting simulation...
-info: Entering event queue @ 106175978500. Starting simulation...
+info: Entering event queue @ 99044727500. Starting simulation...
+info: Entering event queue @ 106044720500. Starting simulation...
+info: Entering event queue @ 106044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 106175979000. Starting simulation...
+info: Entering event queue @ 106044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 107175979000. Starting simulation...
+info: Entering event queue @ 107044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 108175979000. Starting simulation...
+info: Entering event queue @ 108044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 109175979000. Starting simulation...
-info: Entering event queue @ 116175972000. Starting simulation...
-info: Entering event queue @ 116175978500. Starting simulation...
+info: Entering event queue @ 109044727500. Starting simulation...
+info: Entering event queue @ 116044720500. Starting simulation...
+info: Entering event queue @ 116044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 116175979000. Starting simulation...
+info: Entering event queue @ 116044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 117175979000. Starting simulation...
+info: Entering event queue @ 117044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 118175979000. Starting simulation...
+info: Entering event queue @ 118044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 119175979000. Starting simulation...
-info: Entering event queue @ 126175972000. Starting simulation...
-info: Entering event queue @ 126175978500. Starting simulation...
+info: Entering event queue @ 119044727500. Starting simulation...
+info: Entering event queue @ 126044720500. Starting simulation...
+info: Entering event queue @ 126044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 126175979000. Starting simulation...
+info: Entering event queue @ 126044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 127175979000. Starting simulation...
+info: Entering event queue @ 127044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 128175979000. Starting simulation...
+info: Entering event queue @ 128044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 129175979000. Starting simulation...
-info: Entering event queue @ 136175972000. Starting simulation...
-info: Entering event queue @ 136175978500. Starting simulation...
+info: Entering event queue @ 129044727500. Starting simulation...
+info: Entering event queue @ 136044720500. Starting simulation...
+info: Entering event queue @ 136044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 136175979000. Starting simulation...
+info: Entering event queue @ 136044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 137175979000. Starting simulation...
+info: Entering event queue @ 137044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 138175979000. Starting simulation...
+info: Entering event queue @ 138044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 139175979000. Starting simulation...
-info: Entering event queue @ 146175972000. Starting simulation...
-info: Entering event queue @ 146175979000. Starting simulation...
+info: Entering event queue @ 139044727500. Starting simulation...
+info: Entering event queue @ 146044720500. Starting simulation...
+info: Entering event queue @ 146044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 146175983500. Starting simulation...
+info: Entering event queue @ 146044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 147175983500. Starting simulation...
+info: Entering event queue @ 147044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 148175983500. Starting simulation...
+info: Entering event queue @ 148044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 149175983500. Starting simulation...
-info: Entering event queue @ 156175972000. Starting simulation...
-info: Entering event queue @ 156175979000. Starting simulation...
+info: Entering event queue @ 149044727500. Starting simulation...
+info: Entering event queue @ 156044720500. Starting simulation...
+info: Entering event queue @ 156044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 156175983500. Starting simulation...
+info: Entering event queue @ 156044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 157175983500. Starting simulation...
+info: Entering event queue @ 157044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 158175983500. Starting simulation...
+info: Entering event queue @ 158044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 159175983500. Starting simulation...
-info: Entering event queue @ 166175972000. Starting simulation...
-info: Entering event queue @ 166175978500. Starting simulation...
+info: Entering event queue @ 159044727500. Starting simulation...
+info: Entering event queue @ 166044720500. Starting simulation...
+info: Entering event queue @ 166044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 166175979000. Starting simulation...
+info: Entering event queue @ 166044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 167175979000. Starting simulation...
+info: Entering event queue @ 167044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 168175979000. Starting simulation...
+info: Entering event queue @ 168044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 169175979000. Starting simulation...
-info: Entering event queue @ 176175972000. Starting simulation...
-info: Entering event queue @ 176175978500. Starting simulation...
+info: Entering event queue @ 169044727500. Starting simulation...
+info: Entering event queue @ 176044720500. Starting simulation...
+info: Entering event queue @ 176044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 176175979000. Starting simulation...
+info: Entering event queue @ 176044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 177175979000. Starting simulation...
+info: Entering event queue @ 177044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 178175979000. Starting simulation...
+info: Entering event queue @ 178044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 179175979000. Starting simulation...
-info: Entering event queue @ 186175972000. Starting simulation...
-info: Entering event queue @ 186175978500. Starting simulation...
+info: Entering event queue @ 179044727500. Starting simulation...
+info: Entering event queue @ 186044720500. Starting simulation...
+info: Entering event queue @ 186044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 186175979000. Starting simulation...
+info: Entering event queue @ 186044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 187175979000. Starting simulation...
+info: Entering event queue @ 187044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 188175979000. Starting simulation...
+info: Entering event queue @ 188044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 189175979000. Starting simulation...
-info: Entering event queue @ 196175972000. Starting simulation...
-info: Entering event queue @ 196175978500. Starting simulation...
+info: Entering event queue @ 189044727500. Starting simulation...
+info: Entering event queue @ 196044720500. Starting simulation...
+info: Entering event queue @ 196044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 196175979000. Starting simulation...
+info: Entering event queue @ 196044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 197175979000. Starting simulation...
+info: Entering event queue @ 197044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 198175979000. Starting simulation...
+info: Entering event queue @ 198044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 199175979000. Starting simulation...
-info: Entering event queue @ 206175972000. Starting simulation...
-info: Entering event queue @ 206175979000. Starting simulation...
+info: Entering event queue @ 199044727500. Starting simulation...
+info: Entering event queue @ 206044720500. Starting simulation...
+info: Entering event queue @ 206044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 206175983500. Starting simulation...
+info: Entering event queue @ 206044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 207175983500. Starting simulation...
+info: Entering event queue @ 207044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 208175983500. Starting simulation...
+info: Entering event queue @ 208044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 209175983500. Starting simulation...
-info: Entering event queue @ 216175972000. Starting simulation...
-info: Entering event queue @ 216175979000. Starting simulation...
+info: Entering event queue @ 209044727500. Starting simulation...
+info: Entering event queue @ 216044720500. Starting simulation...
+info: Entering event queue @ 216044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 216175983500. Starting simulation...
+info: Entering event queue @ 216044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 217175983500. Starting simulation...
+info: Entering event queue @ 217044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 218175983500. Starting simulation...
+info: Entering event queue @ 218044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 219175983500. Starting simulation...
-info: Entering event queue @ 226175972000. Starting simulation...
-info: Entering event queue @ 226175979000. Starting simulation...
+info: Entering event queue @ 219044727500. Starting simulation...
+info: Entering event queue @ 226044720500. Starting simulation...
+info: Entering event queue @ 226044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 226175983500. Starting simulation...
+info: Entering event queue @ 226044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 227175983500. Starting simulation...
+info: Entering event queue @ 227044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 228175983500. Starting simulation...
+info: Entering event queue @ 228044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 229175983500. Starting simulation...
-info: Entering event queue @ 236175972000. Starting simulation...
-info: Entering event queue @ 236175979000. Starting simulation...
+info: Entering event queue @ 229044727500. Starting simulation...
+info: Entering event queue @ 236044720500. Starting simulation...
+info: Entering event queue @ 236044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 236175983500. Starting simulation...
+info: Entering event queue @ 236044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 237175983500. Starting simulation...
+info: Entering event queue @ 237044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 238175983500. Starting simulation...
+info: Entering event queue @ 238044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 239175983500. Starting simulation...
-info: Entering event queue @ 246175972000. Starting simulation...
-info: Entering event queue @ 246175979000. Starting simulation...
+info: Entering event queue @ 239044727500. Starting simulation...
+info: Entering event queue @ 246044720500. Starting simulation...
+info: Entering event queue @ 246044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 246175983500. Starting simulation...
+info: Entering event queue @ 246044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 247175983500. Starting simulation...
+info: Entering event queue @ 247044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 248175983500. Starting simulation...
+info: Entering event queue @ 248044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 249175983500. Starting simulation...
-info: Entering event queue @ 256175973000. Starting simulation...
-info: Entering event queue @ 256175984500. Starting simulation...
+info: Entering event queue @ 249044727500. Starting simulation...
+info: Entering event queue @ 256044720500. Starting simulation...
+info: Entering event queue @ 256044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 256175989000. Starting simulation...
+info: Entering event queue @ 256044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 257175989000. Starting simulation...
+info: Entering event queue @ 257044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 258175989000. Starting simulation...
+info: Entering event queue @ 258044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 259175989000. Starting simulation...
-info: Entering event queue @ 266175972000. Starting simulation...
-info: Entering event queue @ 266979463000. Starting simulation...
+info: Entering event queue @ 259044727500. Starting simulation...
+info: Entering event queue @ 266044720500. Starting simulation...
+info: Entering event queue @ 266847937000. Starting simulation...
switching cpus
-info: Entering event queue @ 266979465000. Starting simulation...
+info: Entering event queue @ 266847939000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 267979465000. Starting simulation...
+info: Entering event queue @ 267847939000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 268979465000. Starting simulation...
+info: Entering event queue @ 268847939000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 269979465000. Starting simulation...
-info: Entering event queue @ 276175972000. Starting simulation...
-info: Entering event queue @ 276175978500. Starting simulation...
+info: Entering event queue @ 269847939000. Starting simulation...
+info: Entering event queue @ 276044720500. Starting simulation...
+info: Entering event queue @ 276044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 276175979000. Starting simulation...
+info: Entering event queue @ 276044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 277175979000. Starting simulation...
+info: Entering event queue @ 277044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 278175979000. Starting simulation...
+info: Entering event queue @ 278044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 279175979000. Starting simulation...
-info: Entering event queue @ 286175972000. Starting simulation...
-info: Entering event queue @ 286175978500. Starting simulation...
+info: Entering event queue @ 279044727500. Starting simulation...
+info: Entering event queue @ 286044720500. Starting simulation...
+info: Entering event queue @ 286044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 286175979000. Starting simulation...
+info: Entering event queue @ 286044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 287175979000. Starting simulation...
+info: Entering event queue @ 287044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 288175979000. Starting simulation...
+info: Entering event queue @ 288044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 289175979000. Starting simulation...
-info: Entering event queue @ 296175972000. Starting simulation...
-info: Entering event queue @ 296175978500. Starting simulation...
+info: Entering event queue @ 289044727500. Starting simulation...
+info: Entering event queue @ 296044720500. Starting simulation...
+info: Entering event queue @ 296044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 296175979000. Starting simulation...
+info: Entering event queue @ 296044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 297175979000. Starting simulation...
+info: Entering event queue @ 297044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 298175979000. Starting simulation...
-info: Entering event queue @ 299715607000. Starting simulation...
+info: Entering event queue @ 298044727500. Starting simulation...
+info: Entering event queue @ 299584231000. Starting simulation...
switching cpus
-info: Entering event queue @ 299715609000. Starting simulation...
+info: Entering event queue @ 299584233000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 300715609000. Starting simulation...
-info: Entering event queue @ 306175972000. Starting simulation...
-info: Entering event queue @ 306175979000. Starting simulation...
+info: Entering event queue @ 300584233000. Starting simulation...
+info: Entering event queue @ 306044720500. Starting simulation...
+info: Entering event queue @ 306044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 306175983500. Starting simulation...
+info: Entering event queue @ 306044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 307175983500. Starting simulation...
+info: Entering event queue @ 307044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 308175983500. Starting simulation...
+info: Entering event queue @ 308044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 309175983500. Starting simulation...
-info: Entering event queue @ 316175972000. Starting simulation...
-info: Entering event queue @ 316175979000. Starting simulation...
+info: Entering event queue @ 309044727500. Starting simulation...
+info: Entering event queue @ 316044720500. Starting simulation...
+info: Entering event queue @ 316044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 316175983500. Starting simulation...
+info: Entering event queue @ 316044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 317175983500. Starting simulation...
+info: Entering event queue @ 317044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 318175983500. Starting simulation...
+info: Entering event queue @ 318044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 319175983500. Starting simulation...
-info: Entering event queue @ 326175972000. Starting simulation...
-info: Entering event queue @ 326175978500. Starting simulation...
+info: Entering event queue @ 319044727500. Starting simulation...
+info: Entering event queue @ 326044720500. Starting simulation...
+info: Entering event queue @ 326044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 326175979000. Starting simulation...
+info: Entering event queue @ 326044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 327175979000. Starting simulation...
+info: Entering event queue @ 327044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 328175979000. Starting simulation...
+info: Entering event queue @ 328044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 329175979000. Starting simulation...
-info: Entering event queue @ 336175972000. Starting simulation...
-info: Entering event queue @ 336175978500. Starting simulation...
+info: Entering event queue @ 329044727500. Starting simulation...
+info: Entering event queue @ 336044720500. Starting simulation...
+info: Entering event queue @ 336044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 336175979000. Starting simulation...
+info: Entering event queue @ 336044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 337175979000. Starting simulation...
+info: Entering event queue @ 337044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 338175979000. Starting simulation...
+info: Entering event queue @ 338044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 339175979000. Starting simulation...
-info: Entering event queue @ 346175972000. Starting simulation...
-info: Entering event queue @ 346175978500. Starting simulation...
+info: Entering event queue @ 339044727500. Starting simulation...
+info: Entering event queue @ 346044720500. Starting simulation...
+info: Entering event queue @ 346044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 346175979000. Starting simulation...
+info: Entering event queue @ 346044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 347175979000. Starting simulation...
+info: Entering event queue @ 347044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 348175979000. Starting simulation...
+info: Entering event queue @ 348044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 349175979000. Starting simulation...
-info: Entering event queue @ 356175972000. Starting simulation...
-info: Entering event queue @ 356175978500. Starting simulation...
+info: Entering event queue @ 349044727500. Starting simulation...
+info: Entering event queue @ 356044720500. Starting simulation...
+info: Entering event queue @ 356044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 356175979000. Starting simulation...
+info: Entering event queue @ 356044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 357175979000. Starting simulation...
+info: Entering event queue @ 357044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 358175979000. Starting simulation...
+info: Entering event queue @ 358044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 359175979000. Starting simulation...
-info: Entering event queue @ 366175972000. Starting simulation...
-info: Entering event queue @ 366175979000. Starting simulation...
+info: Entering event queue @ 359044727500. Starting simulation...
+info: Entering event queue @ 366044720500. Starting simulation...
+info: Entering event queue @ 366044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 366175983500. Starting simulation...
+info: Entering event queue @ 366044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 367175983500. Starting simulation...
+info: Entering event queue @ 367044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 368175983500. Starting simulation...
+info: Entering event queue @ 368044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 369175983500. Starting simulation...
-info: Entering event queue @ 376175972000. Starting simulation...
-info: Entering event queue @ 376175979000. Starting simulation...
+info: Entering event queue @ 369044727500. Starting simulation...
+info: Entering event queue @ 376044720500. Starting simulation...
+info: Entering event queue @ 376044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 376175983500. Starting simulation...
+info: Entering event queue @ 376044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 377175983500. Starting simulation...
+info: Entering event queue @ 377044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 378175983500. Starting simulation...
+info: Entering event queue @ 378044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 379175983500. Starting simulation...
-info: Entering event queue @ 386175973000. Starting simulation...
-info: Entering event queue @ 386175980000. Starting simulation...
+info: Entering event queue @ 379044727500. Starting simulation...
+info: Entering event queue @ 386044720500. Starting simulation...
+info: Entering event queue @ 386044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 386175984500. Starting simulation...
+info: Entering event queue @ 386044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 387175984500. Starting simulation...
+info: Entering event queue @ 387044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 388175984500. Starting simulation...
+info: Entering event queue @ 388044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 389175984500. Starting simulation...
+info: Entering event queue @ 389044727500. Starting simulation...
+info: Entering event queue @ 396044720500. Starting simulation...
+info: Entering event queue @ 396044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 396175973000. Starting simulation...
+info: Entering event queue @ 396044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 397175973000. Starting simulation...
+info: Entering event queue @ 397044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 398175973000. Starting simulation...
+info: Entering event queue @ 398044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 399175973000. Starting simulation...
-info: Entering event queue @ 406175973000. Starting simulation...
-info: Entering event queue @ 406175981500. Starting simulation...
+info: Entering event queue @ 399044727500. Starting simulation...
+info: Entering event queue @ 406044720500. Starting simulation...
+info: Entering event queue @ 406044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 406175986000. Starting simulation...
+info: Entering event queue @ 406044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 407175986000. Starting simulation...
+info: Entering event queue @ 407044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 408175986000. Starting simulation...
+info: Entering event queue @ 408044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 409175986000. Starting simulation...
-info: Entering event queue @ 416175972000. Starting simulation...
-info: Entering event queue @ 416175979000. Starting simulation...
+info: Entering event queue @ 409044727500. Starting simulation...
+info: Entering event queue @ 416044720500. Starting simulation...
+info: Entering event queue @ 416044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 416175983500. Starting simulation...
+info: Entering event queue @ 416044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 417175983500. Starting simulation...
+info: Entering event queue @ 417044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 418175983500. Starting simulation...
+info: Entering event queue @ 418044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 419175983500. Starting simulation...
-info: Entering event queue @ 426175972000. Starting simulation...
-info: Entering event queue @ 426175978500. Starting simulation...
+info: Entering event queue @ 419044727500. Starting simulation...
+info: Entering event queue @ 426044720500. Starting simulation...
+info: Entering event queue @ 426044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 426175979000. Starting simulation...
+info: Entering event queue @ 426044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 427175979000. Starting simulation...
+info: Entering event queue @ 427044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 428175979000. Starting simulation...
+info: Entering event queue @ 428044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 429175979000. Starting simulation...
-info: Entering event queue @ 436175972000. Starting simulation...
-info: Entering event queue @ 436175978500. Starting simulation...
+info: Entering event queue @ 429044727500. Starting simulation...
+info: Entering event queue @ 436044720500. Starting simulation...
+info: Entering event queue @ 436044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 436175979000. Starting simulation...
+info: Entering event queue @ 436044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 437175979000. Starting simulation...
+info: Entering event queue @ 437044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 438175979000. Starting simulation...
+info: Entering event queue @ 438044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 439175979000. Starting simulation...
-info: Entering event queue @ 446175972000. Starting simulation...
-info: Entering event queue @ 446175978500. Starting simulation...
+info: Entering event queue @ 439044727500. Starting simulation...
+info: Entering event queue @ 446044720500. Starting simulation...
+info: Entering event queue @ 446044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 446175979000. Starting simulation...
+info: Entering event queue @ 446044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 447175979000. Starting simulation...
+info: Entering event queue @ 447044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 448175979000. Starting simulation...
+info: Entering event queue @ 448044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 449175979000. Starting simulation...
-info: Entering event queue @ 456175972000. Starting simulation...
-info: Entering event queue @ 456175978500. Starting simulation...
+info: Entering event queue @ 449044727500. Starting simulation...
+info: Entering event queue @ 456044720500. Starting simulation...
+info: Entering event queue @ 456044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 456175979000. Starting simulation...
+info: Entering event queue @ 456044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 457175979000. Starting simulation...
+info: Entering event queue @ 457044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 458175979000. Starting simulation...
+info: Entering event queue @ 458044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 459175979000. Starting simulation...
-info: Entering event queue @ 466175972000. Starting simulation...
-info: Entering event queue @ 466175979000. Starting simulation...
+info: Entering event queue @ 459044727500. Starting simulation...
+info: Entering event queue @ 466044720500. Starting simulation...
+info: Entering event queue @ 466044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 466175983500. Starting simulation...
+info: Entering event queue @ 466044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 467175983500. Starting simulation...
+info: Entering event queue @ 467044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 468175983500. Starting simulation...
+info: Entering event queue @ 468044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 469175983500. Starting simulation...
-info: Entering event queue @ 476175972000. Starting simulation...
-info: Entering event queue @ 476175979000. Starting simulation...
+info: Entering event queue @ 469044727500. Starting simulation...
+info: Entering event queue @ 476044720500. Starting simulation...
+info: Entering event queue @ 476044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 476175983500. Starting simulation...
+info: Entering event queue @ 476044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 477175983500. Starting simulation...
+info: Entering event queue @ 477044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 478175983500. Starting simulation...
+info: Entering event queue @ 478044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 479175983500. Starting simulation...
-info: Entering event queue @ 486175972000. Starting simulation...
-info: Entering event queue @ 486175978500. Starting simulation...
+info: Entering event queue @ 479044727500. Starting simulation...
+info: Entering event queue @ 486044720500. Starting simulation...
+info: Entering event queue @ 486044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 486175979000. Starting simulation...
+info: Entering event queue @ 486044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 487175979000. Starting simulation...
+info: Entering event queue @ 487044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 488175979000. Starting simulation...
+info: Entering event queue @ 488044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 489175979000. Starting simulation...
-info: Entering event queue @ 496175972000. Starting simulation...
-info: Entering event queue @ 496175978500. Starting simulation...
+info: Entering event queue @ 489044727500. Starting simulation...
+info: Entering event queue @ 496044720500. Starting simulation...
+info: Entering event queue @ 496044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 496175979000. Starting simulation...
+info: Entering event queue @ 496044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 497175979000. Starting simulation...
+info: Entering event queue @ 497044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 498175979000. Starting simulation...
+info: Entering event queue @ 498044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 499175979000. Starting simulation...
-info: Entering event queue @ 506175972000. Starting simulation...
-info: Entering event queue @ 506175978500. Starting simulation...
+info: Entering event queue @ 499044727500. Starting simulation...
+info: Entering event queue @ 506044720500. Starting simulation...
+info: Entering event queue @ 506044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 506175979000. Starting simulation...
+info: Entering event queue @ 506044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 507175979000. Starting simulation...
+info: Entering event queue @ 507044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 508175979000. Starting simulation...
+info: Entering event queue @ 508044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 509175979000. Starting simulation...
-info: Entering event queue @ 516175972000. Starting simulation...
-info: Entering event queue @ 516175978500. Starting simulation...
+info: Entering event queue @ 509044727500. Starting simulation...
+info: Entering event queue @ 516044720500. Starting simulation...
+info: Entering event queue @ 516044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 516175979000. Starting simulation...
+info: Entering event queue @ 516044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 517175979000. Starting simulation...
+info: Entering event queue @ 517044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 518175979000. Starting simulation...
+info: Entering event queue @ 518044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 519175979000. Starting simulation...
-info: Entering event queue @ 526175972000. Starting simulation...
-info: Entering event queue @ 526175979000. Starting simulation...
+info: Entering event queue @ 519044727500. Starting simulation...
+info: Entering event queue @ 526044720500. Starting simulation...
+info: Entering event queue @ 526044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 526175983500. Starting simulation...
+info: Entering event queue @ 526044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 527175983500. Starting simulation...
+info: Entering event queue @ 527044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 528175983500. Starting simulation...
-info: Entering event queue @ 528869056000. Starting simulation...
+info: Entering event queue @ 528044727500. Starting simulation...
+info: Entering event queue @ 528737989000. Starting simulation...
switching cpus
-info: Entering event queue @ 528869058000. Starting simulation...
+info: Entering event queue @ 528737991000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 529869058000. Starting simulation...
-info: Entering event queue @ 536175972000. Starting simulation...
-info: Entering event queue @ 536175979000. Starting simulation...
+info: Entering event queue @ 529737991000. Starting simulation...
+info: Entering event queue @ 536044720500. Starting simulation...
+info: Entering event queue @ 536044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 536175983500. Starting simulation...
+info: Entering event queue @ 536044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 537175983500. Starting simulation...
+info: Entering event queue @ 537044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 538175983500. Starting simulation...
+info: Entering event queue @ 538044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 539175983500. Starting simulation...
+info: Entering event queue @ 539044727500. Starting simulation...
+info: Entering event queue @ 546044720500. Starting simulation...
+info: Entering event queue @ 546044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 546175973000. Starting simulation...
+info: Entering event queue @ 546044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 547175973000. Starting simulation...
+info: Entering event queue @ 547044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 548175973000. Starting simulation...
+info: Entering event queue @ 548044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 549175973000. Starting simulation...
-info: Entering event queue @ 556175973000. Starting simulation...
-info: Entering event queue @ 556175985000. Starting simulation...
+info: Entering event queue @ 549044727500. Starting simulation...
+info: Entering event queue @ 556044720500. Starting simulation...
+info: Entering event queue @ 556044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 556175989500. Starting simulation...
+info: Entering event queue @ 556044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 557175989500. Starting simulation...
+info: Entering event queue @ 557044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 558175989500. Starting simulation...
+info: Entering event queue @ 558044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 559175989500. Starting simulation...
+info: Entering event queue @ 559044727500. Starting simulation...
+info: Entering event queue @ 566044720500. Starting simulation...
+info: Entering event queue @ 566044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 566175973000. Starting simulation...
+info: Entering event queue @ 566044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 567175973000. Starting simulation...
+info: Entering event queue @ 567044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 568175973000. Starting simulation...
+info: Entering event queue @ 568044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 569175973000. Starting simulation...
+info: Entering event queue @ 569044727500. Starting simulation...
+info: Entering event queue @ 576044720500. Starting simulation...
+info: Entering event queue @ 576044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 576175973000. Starting simulation...
+info: Entering event queue @ 576044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 577175973000. Starting simulation...
+info: Entering event queue @ 577044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 578175973000. Starting simulation...
+info: Entering event queue @ 578044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 579175973000. Starting simulation...
+info: Entering event queue @ 579044727500. Starting simulation...
+info: Entering event queue @ 586044720500. Starting simulation...
+info: Entering event queue @ 586044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 586175973000. Starting simulation...
+info: Entering event queue @ 586044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 587175973000. Starting simulation...
+info: Entering event queue @ 587044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 588175973000. Starting simulation...
+info: Entering event queue @ 588044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 589175973000. Starting simulation...
-info: Entering event queue @ 596175973000. Starting simulation...
-info: Entering event queue @ 596175981500. Starting simulation...
+info: Entering event queue @ 589044727500. Starting simulation...
+info: Entering event queue @ 596044720500. Starting simulation...
+info: Entering event queue @ 596044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 596175986000. Starting simulation...
+info: Entering event queue @ 596044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 597175986000. Starting simulation...
+info: Entering event queue @ 597044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 598175986000. Starting simulation...
+info: Entering event queue @ 598044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 599175986000. Starting simulation...
+info: Entering event queue @ 599044727500. Starting simulation...
+info: Entering event queue @ 606044720500. Starting simulation...
+info: Entering event queue @ 606044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 606175973000. Starting simulation...
+info: Entering event queue @ 606044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 607175973000. Starting simulation...
+info: Entering event queue @ 607044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 608175973000. Starting simulation...
+info: Entering event queue @ 608044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 609175973000. Starting simulation...
-info: Entering event queue @ 616175972000. Starting simulation...
-info: Entering event queue @ 616175978500. Starting simulation...
+info: Entering event queue @ 609044727500. Starting simulation...
+info: Entering event queue @ 616044720500. Starting simulation...
+info: Entering event queue @ 616044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 616175979000. Starting simulation...
+info: Entering event queue @ 616044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 617175979000. Starting simulation...
+info: Entering event queue @ 617044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 618175979000. Starting simulation...
+info: Entering event queue @ 618044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 619175979000. Starting simulation...
-info: Entering event queue @ 626175972000. Starting simulation...
-info: Entering event queue @ 627078091000. Starting simulation...
+info: Entering event queue @ 619044727500. Starting simulation...
+info: Entering event queue @ 626044720500. Starting simulation...
+info: Entering event queue @ 626946715000. Starting simulation...
switching cpus
-info: Entering event queue @ 627078093000. Starting simulation...
+info: Entering event queue @ 626946717000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 628078093000. Starting simulation...
+info: Entering event queue @ 627946717000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 629078093000. Starting simulation...
+info: Entering event queue @ 628946717000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 630078093000. Starting simulation...
-info: Entering event queue @ 636175972000. Starting simulation...
-info: Entering event queue @ 636175978500. Starting simulation...
+info: Entering event queue @ 629946717000. Starting simulation...
+info: Entering event queue @ 636044720500. Starting simulation...
+info: Entering event queue @ 636044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 636175979000. Starting simulation...
+info: Entering event queue @ 636044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 637175979000. Starting simulation...
+info: Entering event queue @ 637044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 638175979000. Starting simulation...
+info: Entering event queue @ 638044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 639175979000. Starting simulation...
-info: Entering event queue @ 646175972000. Starting simulation...
-info: Entering event queue @ 646175978500. Starting simulation...
+info: Entering event queue @ 639044727500. Starting simulation...
+info: Entering event queue @ 646044720500. Starting simulation...
+info: Entering event queue @ 646044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 646175979000. Starting simulation...
+info: Entering event queue @ 646044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 647175979000. Starting simulation...
+info: Entering event queue @ 647044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 648175979000. Starting simulation...
+info: Entering event queue @ 648044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 649175979000. Starting simulation...
-info: Entering event queue @ 656175972000. Starting simulation...
-info: Entering event queue @ 656175979000. Starting simulation...
+info: Entering event queue @ 649044727500. Starting simulation...
+info: Entering event queue @ 656044720500. Starting simulation...
+info: Entering event queue @ 656044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 656175983500. Starting simulation...
+info: Entering event queue @ 656044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 657175983500. Starting simulation...
+info: Entering event queue @ 657044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 658175983500. Starting simulation...
-info: Entering event queue @ 659814382000. Starting simulation...
+info: Entering event queue @ 658044727500. Starting simulation...
+info: Entering event queue @ 659682856000. Starting simulation...
switching cpus
-info: Entering event queue @ 659814384000. Starting simulation...
+info: Entering event queue @ 659682858000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 660814384000. Starting simulation...
-info: Entering event queue @ 666175972000. Starting simulation...
-info: Entering event queue @ 666175979000. Starting simulation...
+info: Entering event queue @ 660682858000. Starting simulation...
+info: Entering event queue @ 666044720500. Starting simulation...
+info: Entering event queue @ 666044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 666175983500. Starting simulation...
+info: Entering event queue @ 666044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 667175983500. Starting simulation...
+info: Entering event queue @ 667044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 668175983500. Starting simulation...
+info: Entering event queue @ 668044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 669175983500. Starting simulation...
-info: Entering event queue @ 676175972000. Starting simulation...
-info: Entering event queue @ 676175978500. Starting simulation...
+info: Entering event queue @ 669044727500. Starting simulation...
+info: Entering event queue @ 676044720500. Starting simulation...
+info: Entering event queue @ 676044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 676175979000. Starting simulation...
+info: Entering event queue @ 676044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 677175979000. Starting simulation...
+info: Entering event queue @ 677044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 678175979000. Starting simulation...
+info: Entering event queue @ 678044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 679175979000. Starting simulation...
-info: Entering event queue @ 686175972000. Starting simulation...
-info: Entering event queue @ 686175978500. Starting simulation...
+info: Entering event queue @ 679044727500. Starting simulation...
+info: Entering event queue @ 686044720500. Starting simulation...
+info: Entering event queue @ 686044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 686175979000. Starting simulation...
+info: Entering event queue @ 686044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 687175979000. Starting simulation...
+info: Entering event queue @ 687044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 688175979000. Starting simulation...
+info: Entering event queue @ 688044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 689175979000. Starting simulation...
-info: Entering event queue @ 696175972000. Starting simulation...
-info: Entering event queue @ 696175978500. Starting simulation...
+info: Entering event queue @ 689044727500. Starting simulation...
+info: Entering event queue @ 696044720500. Starting simulation...
+info: Entering event queue @ 696044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 696175979000. Starting simulation...
+info: Entering event queue @ 696044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 697175979000. Starting simulation...
+info: Entering event queue @ 697044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 698175979000. Starting simulation...
+info: Entering event queue @ 698044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 699175979000. Starting simulation...
-info: Entering event queue @ 706175972000. Starting simulation...
-info: Entering event queue @ 706175978500. Starting simulation...
+info: Entering event queue @ 699044727500. Starting simulation...
+info: Entering event queue @ 706044720500. Starting simulation...
+info: Entering event queue @ 706044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 706175979000. Starting simulation...
+info: Entering event queue @ 706044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 707175979000. Starting simulation...
+info: Entering event queue @ 707044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 708175979000. Starting simulation...
+info: Entering event queue @ 708044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 709175979000. Starting simulation...
-info: Entering event queue @ 716175972000. Starting simulation...
-info: Entering event queue @ 716175979000. Starting simulation...
+info: Entering event queue @ 709044727500. Starting simulation...
+info: Entering event queue @ 716044720500. Starting simulation...
+info: Entering event queue @ 716044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 716175983500. Starting simulation...
+info: Entering event queue @ 716044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 717175983500. Starting simulation...
+info: Entering event queue @ 717044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 718175983500. Starting simulation...
+info: Entering event queue @ 718044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 719175983500. Starting simulation...
-info: Entering event queue @ 726175972000. Starting simulation...
-info: Entering event queue @ 726175979000. Starting simulation...
+info: Entering event queue @ 719044727500. Starting simulation...
+info: Entering event queue @ 726044720500. Starting simulation...
+info: Entering event queue @ 726044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 726175983500. Starting simulation...
+info: Entering event queue @ 726044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 727175983500. Starting simulation...
+info: Entering event queue @ 727044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 728175983500. Starting simulation...
+info: Entering event queue @ 728044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 729175983500. Starting simulation...
-info: Entering event queue @ 736175973000. Starting simulation...
-info: Entering event queue @ 736175981000. Starting simulation...
+info: Entering event queue @ 729044727500. Starting simulation...
+info: Entering event queue @ 736044720500. Starting simulation...
+info: Entering event queue @ 736044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 736175985500. Starting simulation...
+info: Entering event queue @ 736044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 737175985500. Starting simulation...
+info: Entering event queue @ 737044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 738175985500. Starting simulation...
+info: Entering event queue @ 738044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 739175985500. Starting simulation...
-info: Entering event queue @ 746175973000. Starting simulation...
-info: Entering event queue @ 746175980500. Starting simulation...
+info: Entering event queue @ 739044727500. Starting simulation...
+info: Entering event queue @ 746044720500. Starting simulation...
+info: Entering event queue @ 746044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 746175985000. Starting simulation...
+info: Entering event queue @ 746044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 747175985000. Starting simulation...
+info: Entering event queue @ 747044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 748175985000. Starting simulation...
+info: Entering event queue @ 748044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 749175985000. Starting simulation...
-info: Entering event queue @ 756175972000. Starting simulation...
-info: Entering event queue @ 756175979000. Starting simulation...
+info: Entering event queue @ 749044727500. Starting simulation...
+info: Entering event queue @ 756044720500. Starting simulation...
+info: Entering event queue @ 756044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 756175983500. Starting simulation...
+info: Entering event queue @ 756044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 757175983500. Starting simulation...
+info: Entering event queue @ 757044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 758175983500. Starting simulation...
+info: Entering event queue @ 758044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 759175983500. Starting simulation...
-info: Entering event queue @ 766175973000. Starting simulation...
-info: Entering event queue @ 766175980000. Starting simulation...
+info: Entering event queue @ 759044727500. Starting simulation...
+info: Entering event queue @ 766044720500. Starting simulation...
+info: Entering event queue @ 766044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 766175984500. Starting simulation...
+info: Entering event queue @ 766044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 767175984500. Starting simulation...
+info: Entering event queue @ 767044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 768175984500. Starting simulation...
+info: Entering event queue @ 768044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 769175984500. Starting simulation...
-info: Entering event queue @ 776175972000. Starting simulation...
-info: Entering event queue @ 776175978500. Starting simulation...
+info: Entering event queue @ 769044727500. Starting simulation...
+info: Entering event queue @ 776044720500. Starting simulation...
+info: Entering event queue @ 776044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 776175979000. Starting simulation...
+info: Entering event queue @ 776044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 777175979000. Starting simulation...
+info: Entering event queue @ 777044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 778175979000. Starting simulation...
+info: Entering event queue @ 778044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 779175979000. Starting simulation...
-info: Entering event queue @ 786175972000. Starting simulation...
-info: Entering event queue @ 786175978500. Starting simulation...
+info: Entering event queue @ 779044727500. Starting simulation...
+info: Entering event queue @ 786044720500. Starting simulation...
+info: Entering event queue @ 786044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 786175979000. Starting simulation...
+info: Entering event queue @ 786044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 787175979000. Starting simulation...
+info: Entering event queue @ 787044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 788175979000. Starting simulation...
+info: Entering event queue @ 788044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 789175979000. Starting simulation...
-info: Entering event queue @ 796175972000. Starting simulation...
-info: Entering event queue @ 796175978500. Starting simulation...
+info: Entering event queue @ 789044727500. Starting simulation...
+info: Entering event queue @ 796044720500. Starting simulation...
+info: Entering event queue @ 796044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 796175979000. Starting simulation...
+info: Entering event queue @ 796044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 797175979000. Starting simulation...
+info: Entering event queue @ 797044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 798175979000. Starting simulation...
+info: Entering event queue @ 798044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 799175979000. Starting simulation...
-info: Entering event queue @ 806175972000. Starting simulation...
-info: Entering event queue @ 806175978500. Starting simulation...
+info: Entering event queue @ 799044727500. Starting simulation...
+info: Entering event queue @ 806044720500. Starting simulation...
+info: Entering event queue @ 806044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 806175979000. Starting simulation...
+info: Entering event queue @ 806044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 807175979000. Starting simulation...
+info: Entering event queue @ 807044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 808175979000. Starting simulation...
+info: Entering event queue @ 808044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 809175979000. Starting simulation...
-info: Entering event queue @ 816175972000. Starting simulation...
-info: Entering event queue @ 816175979000. Starting simulation...
+info: Entering event queue @ 809044727500. Starting simulation...
+info: Entering event queue @ 816044720500. Starting simulation...
+info: Entering event queue @ 816044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 816175983500. Starting simulation...
+info: Entering event queue @ 816044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 817175983500. Starting simulation...
+info: Entering event queue @ 817044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 818175983500. Starting simulation...
+info: Entering event queue @ 818044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 819175983500. Starting simulation...
-info: Entering event queue @ 826175972000. Starting simulation...
-info: Entering event queue @ 826175979000. Starting simulation...
+info: Entering event queue @ 819044727500. Starting simulation...
+info: Entering event queue @ 826044720500. Starting simulation...
+info: Entering event queue @ 826044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 826175983500. Starting simulation...
+info: Entering event queue @ 826044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 827175983500. Starting simulation...
+info: Entering event queue @ 827044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 828175983500. Starting simulation...
+info: Entering event queue @ 828044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 829175983500. Starting simulation...
-info: Entering event queue @ 836175972000. Starting simulation...
-info: Entering event queue @ 836175978500. Starting simulation...
+info: Entering event queue @ 829044727500. Starting simulation...
+info: Entering event queue @ 836044720500. Starting simulation...
+info: Entering event queue @ 836044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 836175979000. Starting simulation...
+info: Entering event queue @ 836044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 837175979000. Starting simulation...
+info: Entering event queue @ 837044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 838175979000. Starting simulation...
+info: Entering event queue @ 838044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 839175979000. Starting simulation...
-info: Entering event queue @ 846175972000. Starting simulation...
-info: Entering event queue @ 846175978500. Starting simulation...
+info: Entering event queue @ 839044727500. Starting simulation...
+info: Entering event queue @ 846044720500. Starting simulation...
+info: Entering event queue @ 846044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 846175979000. Starting simulation...
+info: Entering event queue @ 846044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 847175979000. Starting simulation...
+info: Entering event queue @ 847044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 848175979000. Starting simulation...
+info: Entering event queue @ 848044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 849175979000. Starting simulation...
-info: Entering event queue @ 856175972000. Starting simulation...
-info: Entering event queue @ 856231996000. Starting simulation...
+info: Entering event queue @ 849044727500. Starting simulation...
+info: Entering event queue @ 856044720500. Starting simulation...
+info: Entering event queue @ 856100473000. Starting simulation...
switching cpus
-info: Entering event queue @ 856231998000. Starting simulation...
+info: Entering event queue @ 856100475000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 857231998000. Starting simulation...
+info: Entering event queue @ 857100475000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 858231998000. Starting simulation...
+info: Entering event queue @ 858100475000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 859231998000. Starting simulation...
-info: Entering event queue @ 866175972000. Starting simulation...
-info: Entering event queue @ 866175978500. Starting simulation...
+info: Entering event queue @ 859100475000. Starting simulation...
+info: Entering event queue @ 866044720500. Starting simulation...
+info: Entering event queue @ 866044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 866175979000. Starting simulation...
+info: Entering event queue @ 866044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 867175979000. Starting simulation...
+info: Entering event queue @ 867044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 868175979000. Starting simulation...
+info: Entering event queue @ 868044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 869175979000. Starting simulation...
-info: Entering event queue @ 876175972000. Starting simulation...
-info: Entering event queue @ 876175979000. Starting simulation...
+info: Entering event queue @ 869044727500. Starting simulation...
+info: Entering event queue @ 876044720500. Starting simulation...
+info: Entering event queue @ 876044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 876175983500. Starting simulation...
+info: Entering event queue @ 876044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 877175983500. Starting simulation...
+info: Entering event queue @ 877044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 878175983500. Starting simulation...
+info: Entering event queue @ 878044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 879175983500. Starting simulation...
-info: Entering event queue @ 886175972000. Starting simulation...
-info: Entering event queue @ 886175979000. Starting simulation...
+info: Entering event queue @ 879044727500. Starting simulation...
+info: Entering event queue @ 886044720500. Starting simulation...
+info: Entering event queue @ 886044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 886175983500. Starting simulation...
+info: Entering event queue @ 886044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 887175983500. Starting simulation...
+info: Entering event queue @ 887044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 888175983500. Starting simulation...
-info: Entering event queue @ 888968137000. Starting simulation...
+info: Entering event queue @ 888044727500. Starting simulation...
+info: Entering event queue @ 888837073000. Starting simulation...
switching cpus
-info: Entering event queue @ 888968139000. Starting simulation...
+info: Entering event queue @ 888837075000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 889968139000. Starting simulation...
-info: Entering event queue @ 896175973000. Starting simulation...
-info: Entering event queue @ 896175981000. Starting simulation...
+info: Entering event queue @ 889837075000. Starting simulation...
+info: Entering event queue @ 896044720500. Starting simulation...
+info: Entering event queue @ 896044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 896175985500. Starting simulation...
+info: Entering event queue @ 896044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 897175985500. Starting simulation...
+info: Entering event queue @ 897044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 898175985500. Starting simulation...
+info: Entering event queue @ 898044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 899175985500. Starting simulation...
+info: Entering event queue @ 899044727500. Starting simulation...
+info: Entering event queue @ 906044720500. Starting simulation...
+info: Entering event queue @ 906044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 906175973000. Starting simulation...
+info: Entering event queue @ 906044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 907175973000. Starting simulation...
+info: Entering event queue @ 907044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 908175973000. Starting simulation...
+info: Entering event queue @ 908044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 909175973000. Starting simulation...
-info: Entering event queue @ 916175972000. Starting simulation...
-info: Entering event queue @ 916175979000. Starting simulation...
+info: Entering event queue @ 909044727500. Starting simulation...
+info: Entering event queue @ 916044720500. Starting simulation...
+info: Entering event queue @ 916044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 916175983500. Starting simulation...
+info: Entering event queue @ 916044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 917175983500. Starting simulation...
+info: Entering event queue @ 917044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 918175983500. Starting simulation...
+info: Entering event queue @ 918044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 919175983500. Starting simulation...
-info: Entering event queue @ 926175973000. Starting simulation...
-info: Entering event queue @ 926175981500. Starting simulation...
+info: Entering event queue @ 919044727500. Starting simulation...
+info: Entering event queue @ 926044720500. Starting simulation...
+info: Entering event queue @ 926044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 926175986000. Starting simulation...
+info: Entering event queue @ 926044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 927175986000. Starting simulation...
+info: Entering event queue @ 927044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 928175986000. Starting simulation...
+info: Entering event queue @ 928044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 929175986000. Starting simulation...
-info: Entering event queue @ 936175972000. Starting simulation...
-info: Entering event queue @ 936175978500. Starting simulation...
+info: Entering event queue @ 929044727500. Starting simulation...
+info: Entering event queue @ 936044720500. Starting simulation...
+info: Entering event queue @ 936044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 936175979000. Starting simulation...
+info: Entering event queue @ 936044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 937175979000. Starting simulation...
+info: Entering event queue @ 937044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 938175979000. Starting simulation...
+info: Entering event queue @ 938044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 939175979000. Starting simulation...
-info: Entering event queue @ 946175972000. Starting simulation...
-info: Entering event queue @ 946175978500. Starting simulation...
+info: Entering event queue @ 939044727500. Starting simulation...
+info: Entering event queue @ 946044720500. Starting simulation...
+info: Entering event queue @ 946044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 946175979000. Starting simulation...
+info: Entering event queue @ 946044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 947175979000. Starting simulation...
+info: Entering event queue @ 947044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 948175979000. Starting simulation...
+info: Entering event queue @ 948044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 949175979000. Starting simulation...
-info: Entering event queue @ 956175972000. Starting simulation...
-info: Entering event queue @ 956175978500. Starting simulation...
+info: Entering event queue @ 949044727500. Starting simulation...
+info: Entering event queue @ 956044720500. Starting simulation...
+info: Entering event queue @ 956044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 956175979000. Starting simulation...
+info: Entering event queue @ 956044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 957175979000. Starting simulation...
+info: Entering event queue @ 957044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 958175979000. Starting simulation...
+info: Entering event queue @ 958044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 959175979000. Starting simulation...
-info: Entering event queue @ 966175972000. Starting simulation...
-info: Entering event queue @ 966175978500. Starting simulation...
+info: Entering event queue @ 959044727500. Starting simulation...
+info: Entering event queue @ 966044720500. Starting simulation...
+info: Entering event queue @ 966044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 966175979000. Starting simulation...
+info: Entering event queue @ 966044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 967175979000. Starting simulation...
+info: Entering event queue @ 967044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 968175979000. Starting simulation...
+info: Entering event queue @ 968044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 969175979000. Starting simulation...
-info: Entering event queue @ 976175972000. Starting simulation...
-info: Entering event queue @ 976175979000. Starting simulation...
+info: Entering event queue @ 969044727500. Starting simulation...
+info: Entering event queue @ 976044720500. Starting simulation...
+info: Entering event queue @ 976044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 976175983500. Starting simulation...
+info: Entering event queue @ 976044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 977175983500. Starting simulation...
+info: Entering event queue @ 977044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 978175983500. Starting simulation...
+info: Entering event queue @ 978044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 979175983500. Starting simulation...
-info: Entering event queue @ 986175973000. Starting simulation...
-info: Entering event queue @ 987176863000. Starting simulation...
+info: Entering event queue @ 979044727500. Starting simulation...
+info: Entering event queue @ 986044720500. Starting simulation...
+info: Entering event queue @ 987045796000. Starting simulation...
switching cpus
-info: Entering event queue @ 987176865000. Starting simulation...
+info: Entering event queue @ 987045798000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 988176865000. Starting simulation...
+info: Entering event queue @ 988045798000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 989176865000. Starting simulation...
+info: Entering event queue @ 989045798000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 990176865000. Starting simulation...
-info: Entering event queue @ 996175972000. Starting simulation...
-info: Entering event queue @ 996175978500. Starting simulation...
+info: Entering event queue @ 990045798000. Starting simulation...
+info: Entering event queue @ 996044720500. Starting simulation...
+info: Entering event queue @ 996044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 996175979000. Starting simulation...
+info: Entering event queue @ 996044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 997175979000. Starting simulation...
+info: Entering event queue @ 997044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 998175979000. Starting simulation...
+info: Entering event queue @ 998044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 999175979000. Starting simulation...
-info: Entering event queue @ 1006175972000. Starting simulation...
-info: Entering event queue @ 1006175978500. Starting simulation...
+info: Entering event queue @ 999044727500. Starting simulation...
+info: Entering event queue @ 1006044720500. Starting simulation...
+info: Entering event queue @ 1006044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1006175979000. Starting simulation...
+info: Entering event queue @ 1006044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1007175979000. Starting simulation...
+info: Entering event queue @ 1007044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1008175979000. Starting simulation...
+info: Entering event queue @ 1008044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1009175979000. Starting simulation...
-info: Entering event queue @ 1016175972000. Starting simulation...
-info: Entering event queue @ 1016175978500. Starting simulation...
+info: Entering event queue @ 1009044727500. Starting simulation...
+info: Entering event queue @ 1016044720500. Starting simulation...
+info: Entering event queue @ 1016044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1016175979000. Starting simulation...
+info: Entering event queue @ 1016044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1017175979000. Starting simulation...
+info: Entering event queue @ 1017044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1018175979000. Starting simulation...
+info: Entering event queue @ 1018044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1019175979000. Starting simulation...
-info: Entering event queue @ 1026175972000. Starting simulation...
-info: Entering event queue @ 1026175978500. Starting simulation...
+info: Entering event queue @ 1019044727500. Starting simulation...
+info: Entering event queue @ 1026044720500. Starting simulation...
+info: Entering event queue @ 1026044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1026175979000. Starting simulation...
+info: Entering event queue @ 1026044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1027175979000. Starting simulation...
+info: Entering event queue @ 1027044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1028175979000. Starting simulation...
+info: Entering event queue @ 1028044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1029175979000. Starting simulation...
-info: Entering event queue @ 1036175972000. Starting simulation...
-info: Entering event queue @ 1036175979000. Starting simulation...
+info: Entering event queue @ 1029044727500. Starting simulation...
+info: Entering event queue @ 1036044720500. Starting simulation...
+info: Entering event queue @ 1036044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1036175983500. Starting simulation...
+info: Entering event queue @ 1036044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1037175983500. Starting simulation...
+info: Entering event queue @ 1037044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1038175983500. Starting simulation...
+info: Entering event queue @ 1038044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1039175983500. Starting simulation...
-info: Entering event queue @ 1046175972000. Starting simulation...
-info: Entering event queue @ 1046175979000. Starting simulation...
+info: Entering event queue @ 1039044727500. Starting simulation...
+info: Entering event queue @ 1046044720500. Starting simulation...
+info: Entering event queue @ 1046044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1046175983500. Starting simulation...
+info: Entering event queue @ 1046044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1047175983500. Starting simulation...
+info: Entering event queue @ 1047044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1048175983500. Starting simulation...
+info: Entering event queue @ 1048044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1049175983500. Starting simulation...
-info: Entering event queue @ 1056175972000. Starting simulation...
-info: Entering event queue @ 1056175979000. Starting simulation...
+info: Entering event queue @ 1049044727500. Starting simulation...
+info: Entering event queue @ 1056044720500. Starting simulation...
+info: Entering event queue @ 1056044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1056175983500. Starting simulation...
+info: Entering event queue @ 1056044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1057175983500. Starting simulation...
+info: Entering event queue @ 1057044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1058175983500. Starting simulation...
+info: Entering event queue @ 1058044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1059175983500. Starting simulation...
-info: Entering event queue @ 1066175972000. Starting simulation...
-info: Entering event queue @ 1066175979000. Starting simulation...
+info: Entering event queue @ 1059044727500. Starting simulation...
+info: Entering event queue @ 1066044720500. Starting simulation...
+info: Entering event queue @ 1066044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1066175983500. Starting simulation...
+info: Entering event queue @ 1066044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1067175983500. Starting simulation...
+info: Entering event queue @ 1067044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1068175983500. Starting simulation...
+info: Entering event queue @ 1068044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1069175983500. Starting simulation...
-info: Entering event queue @ 1076175972000. Starting simulation...
-info: Entering event queue @ 1076175979000. Starting simulation...
+info: Entering event queue @ 1069044727500. Starting simulation...
+info: Entering event queue @ 1076044720500. Starting simulation...
+info: Entering event queue @ 1076044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1076175983500. Starting simulation...
+info: Entering event queue @ 1076044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1077175983500. Starting simulation...
+info: Entering event queue @ 1077044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1078175983500. Starting simulation...
+info: Entering event queue @ 1078044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1079175983500. Starting simulation...
-info: Entering event queue @ 1086175973000. Starting simulation...
-info: Entering event queue @ 1086175981500. Starting simulation...
+info: Entering event queue @ 1079044727500. Starting simulation...
+info: Entering event queue @ 1086044720500. Starting simulation...
+info: Entering event queue @ 1086044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1086175986000. Starting simulation...
+info: Entering event queue @ 1086044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1087175986000. Starting simulation...
+info: Entering event queue @ 1087044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1088175986000. Starting simulation...
+info: Entering event queue @ 1088044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1089175986000. Starting simulation...
-info: Entering event queue @ 1096175972000. Starting simulation...
-info: Entering event queue @ 1096175978500. Starting simulation...
+info: Entering event queue @ 1089044727500. Starting simulation...
+info: Entering event queue @ 1096044720500. Starting simulation...
+info: Entering event queue @ 1096044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1096175979000. Starting simulation...
+info: Entering event queue @ 1096044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1097175979000. Starting simulation...
+info: Entering event queue @ 1097044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1098175979000. Starting simulation...
+info: Entering event queue @ 1098044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1099175979000. Starting simulation...
-info: Entering event queue @ 1106175972000. Starting simulation...
-info: Entering event queue @ 1106175978500. Starting simulation...
+info: Entering event queue @ 1099044727500. Starting simulation...
+info: Entering event queue @ 1106044720500. Starting simulation...
+info: Entering event queue @ 1106044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1106175979000. Starting simulation...
+info: Entering event queue @ 1106044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1107175979000. Starting simulation...
+info: Entering event queue @ 1107044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1108175979000. Starting simulation...
+info: Entering event queue @ 1108044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1109175979000. Starting simulation...
-info: Entering event queue @ 1116175972000. Starting simulation...
-info: Entering event queue @ 1116175978500. Starting simulation...
+info: Entering event queue @ 1109044727500. Starting simulation...
+info: Entering event queue @ 1116044720500. Starting simulation...
+info: Entering event queue @ 1116044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1116175979000. Starting simulation...
+info: Entering event queue @ 1116044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1117175979000. Starting simulation...
+info: Entering event queue @ 1117044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1118175979000. Starting simulation...
+info: Entering event queue @ 1118044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1119175979000. Starting simulation...
-info: Entering event queue @ 1126175972000. Starting simulation...
-info: Entering event queue @ 1126175978500. Starting simulation...
+info: Entering event queue @ 1119044727500. Starting simulation...
+info: Entering event queue @ 1126044720500. Starting simulation...
+info: Entering event queue @ 1126044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1126175979000. Starting simulation...
+info: Entering event queue @ 1126044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1127175979000. Starting simulation...
+info: Entering event queue @ 1127044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1128175979000. Starting simulation...
+info: Entering event queue @ 1128044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1129175979000. Starting simulation...
-info: Entering event queue @ 1136175972000. Starting simulation...
-info: Entering event queue @ 1136175979000. Starting simulation...
+info: Entering event queue @ 1129044727500. Starting simulation...
+info: Entering event queue @ 1136044720500. Starting simulation...
+info: Entering event queue @ 1136044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1136175983500. Starting simulation...
+info: Entering event queue @ 1136044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1137175983500. Starting simulation...
+info: Entering event queue @ 1137044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1138175983500. Starting simulation...
+info: Entering event queue @ 1138044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1139175983500. Starting simulation...
-info: Entering event queue @ 1146175972000. Starting simulation...
-info: Entering event queue @ 1146175979000. Starting simulation...
+info: Entering event queue @ 1139044727500. Starting simulation...
+info: Entering event queue @ 1146044720500. Starting simulation...
+info: Entering event queue @ 1146044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1146175983500. Starting simulation...
+info: Entering event queue @ 1146044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1147175983500. Starting simulation...
+info: Entering event queue @ 1147044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1148175983500. Starting simulation...
+info: Entering event queue @ 1148044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1149175983500. Starting simulation...
-info: Entering event queue @ 1156175972000. Starting simulation...
-info: Entering event queue @ 1156175978500. Starting simulation...
+info: Entering event queue @ 1149044727500. Starting simulation...
+info: Entering event queue @ 1156044720500. Starting simulation...
+info: Entering event queue @ 1156044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1156175979000. Starting simulation...
+info: Entering event queue @ 1156044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1157175979000. Starting simulation...
+info: Entering event queue @ 1157044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1158175979000. Starting simulation...
+info: Entering event queue @ 1158044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1159175979000. Starting simulation...
-info: Entering event queue @ 1166175972000. Starting simulation...
-info: Entering event queue @ 1166175978500. Starting simulation...
+info: Entering event queue @ 1159044727500. Starting simulation...
+info: Entering event queue @ 1166044720500. Starting simulation...
+info: Entering event queue @ 1166044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1166175979000. Starting simulation...
+info: Entering event queue @ 1166044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1167175979000. Starting simulation...
+info: Entering event queue @ 1167044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1168175979000. Starting simulation...
+info: Entering event queue @ 1168044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1169175979000. Starting simulation...
-info: Entering event queue @ 1176175972000. Starting simulation...
-info: Entering event queue @ 1176175978500. Starting simulation...
+info: Entering event queue @ 1169044727500. Starting simulation...
+info: Entering event queue @ 1176044720500. Starting simulation...
+info: Entering event queue @ 1176044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1176175979000. Starting simulation...
+info: Entering event queue @ 1176044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1177175979000. Starting simulation...
+info: Entering event queue @ 1177044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1178175979000. Starting simulation...
+info: Entering event queue @ 1178044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1179175979000. Starting simulation...
-info: Entering event queue @ 1186175972000. Starting simulation...
-info: Entering event queue @ 1186175978500. Starting simulation...
+info: Entering event queue @ 1179044727500. Starting simulation...
+info: Entering event queue @ 1186044720500. Starting simulation...
+info: Entering event queue @ 1186044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1186175979000. Starting simulation...
+info: Entering event queue @ 1186044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1187175979000. Starting simulation...
+info: Entering event queue @ 1187044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1188175979000. Starting simulation...
+info: Entering event queue @ 1188044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1189175979000. Starting simulation...
-info: Entering event queue @ 1196175972000. Starting simulation...
-info: Entering event queue @ 1196175979000. Starting simulation...
+info: Entering event queue @ 1189044727500. Starting simulation...
+info: Entering event queue @ 1196044720500. Starting simulation...
+info: Entering event queue @ 1196044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1196175983500. Starting simulation...
+info: Entering event queue @ 1196044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1197175983500. Starting simulation...
+info: Entering event queue @ 1197044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1198175983500. Starting simulation...
+info: Entering event queue @ 1198044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1199175983500. Starting simulation...
-info: Entering event queue @ 1206175972000. Starting simulation...
-info: Entering event queue @ 1206175979000. Starting simulation...
+info: Entering event queue @ 1199044727500. Starting simulation...
+info: Entering event queue @ 1206044720500. Starting simulation...
+info: Entering event queue @ 1206044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1206175983500. Starting simulation...
+info: Entering event queue @ 1206044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1207175983500. Starting simulation...
+info: Entering event queue @ 1207044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1208175983500. Starting simulation...
+info: Entering event queue @ 1208044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1209175983500. Starting simulation...
-info: Entering event queue @ 1216175973000. Starting simulation...
-info: Entering event queue @ 1216330621000. Starting simulation...
+info: Entering event queue @ 1209044727500. Starting simulation...
+info: Entering event queue @ 1216044720500. Starting simulation...
+info: Entering event queue @ 1216199554000. Starting simulation...
switching cpus
-info: Entering event queue @ 1216330623000. Starting simulation...
+info: Entering event queue @ 1216199556000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1217330623000. Starting simulation...
+info: Entering event queue @ 1217199556000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1218330623000. Starting simulation...
+info: Entering event queue @ 1218199556000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1219330623000. Starting simulation...
-info: Entering event queue @ 1226175973000. Starting simulation...
-info: Entering event queue @ 1226175980500. Starting simulation...
+info: Entering event queue @ 1219199556000. Starting simulation...
+info: Entering event queue @ 1226044720500. Starting simulation...
+info: Entering event queue @ 1226044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1226175985000. Starting simulation...
+info: Entering event queue @ 1226044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1227175985000. Starting simulation...
+info: Entering event queue @ 1227044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1228175985000. Starting simulation...
+info: Entering event queue @ 1228044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1229175985000. Starting simulation...
-info: Entering event queue @ 1236175972000. Starting simulation...
-info: Entering event queue @ 1236175979000. Starting simulation...
+info: Entering event queue @ 1229044727500. Starting simulation...
+info: Entering event queue @ 1236044720500. Starting simulation...
+info: Entering event queue @ 1236044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1236175983500. Starting simulation...
+info: Entering event queue @ 1236044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1237175983500. Starting simulation...
+info: Entering event queue @ 1237044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1238175983500. Starting simulation...
+info: Entering event queue @ 1238044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1239175983500. Starting simulation...
-info: Entering event queue @ 1246175973000. Starting simulation...
-info: Entering event queue @ 1246175981500. Starting simulation...
+info: Entering event queue @ 1239044727500. Starting simulation...
+info: Entering event queue @ 1246044720500. Starting simulation...
+info: Entering event queue @ 1246044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1246175986000. Starting simulation...
+info: Entering event queue @ 1246044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1247175986000. Starting simulation...
+info: Entering event queue @ 1247044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1248175986000. Starting simulation...
-info: Entering event queue @ 1249067221000. Starting simulation...
+info: Entering event queue @ 1248044727500. Starting simulation...
+info: Entering event queue @ 1248935845000. Starting simulation...
switching cpus
-info: Entering event queue @ 1249067223000. Starting simulation...
+info: Entering event queue @ 1248935847000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1250067223000. Starting simulation...
-info: Entering event queue @ 1256175972000. Starting simulation...
-info: Entering event queue @ 1256175978500. Starting simulation...
+info: Entering event queue @ 1249935847000. Starting simulation...
+info: Entering event queue @ 1256044720500. Starting simulation...
+info: Entering event queue @ 1256044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1256175979000. Starting simulation...
+info: Entering event queue @ 1256044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1257175979000. Starting simulation...
+info: Entering event queue @ 1257044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1258175979000. Starting simulation...
+info: Entering event queue @ 1258044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1259175979000. Starting simulation...
-info: Entering event queue @ 1266175972000. Starting simulation...
-info: Entering event queue @ 1266175978500. Starting simulation...
+info: Entering event queue @ 1259044727500. Starting simulation...
+info: Entering event queue @ 1266044720500. Starting simulation...
+info: Entering event queue @ 1266044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1266175979000. Starting simulation...
+info: Entering event queue @ 1266044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1267175979000. Starting simulation...
+info: Entering event queue @ 1267044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1268175979000. Starting simulation...
+info: Entering event queue @ 1268044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1269175979000. Starting simulation...
-info: Entering event queue @ 1276175972000. Starting simulation...
-info: Entering event queue @ 1276175978500. Starting simulation...
+info: Entering event queue @ 1269044727500. Starting simulation...
+info: Entering event queue @ 1276044720500. Starting simulation...
+info: Entering event queue @ 1276044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1276175979000. Starting simulation...
+info: Entering event queue @ 1276044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1277175979000. Starting simulation...
+info: Entering event queue @ 1277044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1278175979000. Starting simulation...
+info: Entering event queue @ 1278044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1279175979000. Starting simulation...
-info: Entering event queue @ 1286175972000. Starting simulation...
-info: Entering event queue @ 1286175978500. Starting simulation...
+info: Entering event queue @ 1279044727500. Starting simulation...
+info: Entering event queue @ 1286044720500. Starting simulation...
+info: Entering event queue @ 1286044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1286175979000. Starting simulation...
+info: Entering event queue @ 1286044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1287175979000. Starting simulation...
+info: Entering event queue @ 1287044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1288175979000. Starting simulation...
+info: Entering event queue @ 1288044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1289175979000. Starting simulation...
-info: Entering event queue @ 1296175972000. Starting simulation...
-info: Entering event queue @ 1296175979000. Starting simulation...
+info: Entering event queue @ 1289044727500. Starting simulation...
+info: Entering event queue @ 1296044720500. Starting simulation...
+info: Entering event queue @ 1296044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1296175983500. Starting simulation...
+info: Entering event queue @ 1296044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1297175983500. Starting simulation...
+info: Entering event queue @ 1297044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1298175983500. Starting simulation...
+info: Entering event queue @ 1298044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1299175983500. Starting simulation...
-info: Entering event queue @ 1306175972000. Starting simulation...
-info: Entering event queue @ 1306175979000. Starting simulation...
+info: Entering event queue @ 1299044727500. Starting simulation...
+info: Entering event queue @ 1306044720500. Starting simulation...
+info: Entering event queue @ 1306044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1306175983500. Starting simulation...
+info: Entering event queue @ 1306044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1307175983500. Starting simulation...
+info: Entering event queue @ 1307044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1308175983500. Starting simulation...
+info: Entering event queue @ 1308044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1309175983500. Starting simulation...
-info: Entering event queue @ 1316175972000. Starting simulation...
-info: Entering event queue @ 1316175978500. Starting simulation...
+info: Entering event queue @ 1309044727500. Starting simulation...
+info: Entering event queue @ 1316044720500. Starting simulation...
+info: Entering event queue @ 1316044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1316175979000. Starting simulation...
+info: Entering event queue @ 1316044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1317175979000. Starting simulation...
+info: Entering event queue @ 1317044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1318175979000. Starting simulation...
+info: Entering event queue @ 1318044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1319175979000. Starting simulation...
-info: Entering event queue @ 1326175972000. Starting simulation...
-info: Entering event queue @ 1326175978500. Starting simulation...
+info: Entering event queue @ 1319044727500. Starting simulation...
+info: Entering event queue @ 1326044720500. Starting simulation...
+info: Entering event queue @ 1326044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1326175979000. Starting simulation...
+info: Entering event queue @ 1326044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1327175979000. Starting simulation...
+info: Entering event queue @ 1327044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1328175979000. Starting simulation...
+info: Entering event queue @ 1328044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1329175979000. Starting simulation...
-info: Entering event queue @ 1336175972000. Starting simulation...
-info: Entering event queue @ 1336175978500. Starting simulation...
+info: Entering event queue @ 1329044727500. Starting simulation...
+info: Entering event queue @ 1336044720500. Starting simulation...
+info: Entering event queue @ 1336044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1336175979000. Starting simulation...
+info: Entering event queue @ 1336044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1337175979000. Starting simulation...
+info: Entering event queue @ 1337044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1338175979000. Starting simulation...
+info: Entering event queue @ 1338044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1339175979000. Starting simulation...
-info: Entering event queue @ 1346175972000. Starting simulation...
-info: Entering event queue @ 1347275947000. Starting simulation...
+info: Entering event queue @ 1339044727500. Starting simulation...
+info: Entering event queue @ 1346044720500. Starting simulation...
+info: Entering event queue @ 1347144421000. Starting simulation...
switching cpus
-info: Entering event queue @ 1347275949000. Starting simulation...
+info: Entering event queue @ 1347144423000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1348275949000. Starting simulation...
+info: Entering event queue @ 1348144423000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1349275949000. Starting simulation...
+info: Entering event queue @ 1349144423000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1350275949000. Starting simulation...
-info: Entering event queue @ 1356175972000. Starting simulation...
-info: Entering event queue @ 1356175979000. Starting simulation...
+info: Entering event queue @ 1350144423000. Starting simulation...
+info: Entering event queue @ 1356044720500. Starting simulation...
+info: Entering event queue @ 1356044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1356175983500. Starting simulation...
+info: Entering event queue @ 1356044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1357175983500. Starting simulation...
+info: Entering event queue @ 1357044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1358175983500. Starting simulation...
+info: Entering event queue @ 1358044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1359175983500. Starting simulation...
-info: Entering event queue @ 1366175972000. Starting simulation...
-info: Entering event queue @ 1366175979000. Starting simulation...
+info: Entering event queue @ 1359044727500. Starting simulation...
+info: Entering event queue @ 1366044720500. Starting simulation...
+info: Entering event queue @ 1366044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1366175983500. Starting simulation...
+info: Entering event queue @ 1366044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1367175983500. Starting simulation...
+info: Entering event queue @ 1367044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1368175983500. Starting simulation...
+info: Entering event queue @ 1368044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1369175983500. Starting simulation...
+info: Entering event queue @ 1369044727500. Starting simulation...
+info: Entering event queue @ 1376044720500. Starting simulation...
+info: Entering event queue @ 1376044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1376175973000. Starting simulation...
+info: Entering event queue @ 1376044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1377175973000. Starting simulation...
+info: Entering event queue @ 1377044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1378175973000. Starting simulation...
+info: Entering event queue @ 1378044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1379175973000. Starting simulation...
+info: Entering event queue @ 1379044727500. Starting simulation...
+info: Entering event queue @ 1386044720500. Starting simulation...
+info: Entering event queue @ 1386044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1386175973000. Starting simulation...
+info: Entering event queue @ 1386044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1387175973000. Starting simulation...
+info: Entering event queue @ 1387044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1388175973000. Starting simulation...
+info: Entering event queue @ 1388044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1389175973000. Starting simulation...
-info: Entering event queue @ 1396175973000. Starting simulation...
-info: Entering event queue @ 1396175981500. Starting simulation...
+info: Entering event queue @ 1389044727500. Starting simulation...
+info: Entering event queue @ 1396044720500. Starting simulation...
+info: Entering event queue @ 1396044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1396175986000. Starting simulation...
+info: Entering event queue @ 1396044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1397175986000. Starting simulation...
+info: Entering event queue @ 1397044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1398175986000. Starting simulation...
+info: Entering event queue @ 1398044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1399175986000. Starting simulation...
+info: Entering event queue @ 1399044727500. Starting simulation...
+info: Entering event queue @ 1406044720500. Starting simulation...
+info: Entering event queue @ 1406044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1406175973000. Starting simulation...
+info: Entering event queue @ 1406044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1407175973000. Starting simulation...
+info: Entering event queue @ 1407044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1408175973000. Starting simulation...
+info: Entering event queue @ 1408044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1409175973000. Starting simulation...
-info: Entering event queue @ 1416175972000. Starting simulation...
-info: Entering event queue @ 1416175978500. Starting simulation...
+info: Entering event queue @ 1409044727500. Starting simulation...
+info: Entering event queue @ 1416044720500. Starting simulation...
+info: Entering event queue @ 1416044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1416175979000. Starting simulation...
+info: Entering event queue @ 1416044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1417175979000. Starting simulation...
+info: Entering event queue @ 1417044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1418175979000. Starting simulation...
+info: Entering event queue @ 1418044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1419175979000. Starting simulation...
-info: Entering event queue @ 1426175972000. Starting simulation...
-info: Entering event queue @ 1426175978500. Starting simulation...
+info: Entering event queue @ 1419044727500. Starting simulation...
+info: Entering event queue @ 1426044720500. Starting simulation...
+info: Entering event queue @ 1426044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1426175979000. Starting simulation...
+info: Entering event queue @ 1426044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1427175979000. Starting simulation...
+info: Entering event queue @ 1427044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1428175979000. Starting simulation...
+info: Entering event queue @ 1428044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1429175979000. Starting simulation...
-info: Entering event queue @ 1436175972000. Starting simulation...
-info: Entering event queue @ 1436175978500. Starting simulation...
+info: Entering event queue @ 1429044727500. Starting simulation...
+info: Entering event queue @ 1436044720500. Starting simulation...
+info: Entering event queue @ 1436044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1436175979000. Starting simulation...
+info: Entering event queue @ 1436044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1437175979000. Starting simulation...
+info: Entering event queue @ 1437044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1438175979000. Starting simulation...
+info: Entering event queue @ 1438044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1439175979000. Starting simulation...
-info: Entering event queue @ 1446175972000. Starting simulation...
-info: Entering event queue @ 1446175978500. Starting simulation...
+info: Entering event queue @ 1439044727500. Starting simulation...
+info: Entering event queue @ 1446044720500. Starting simulation...
+info: Entering event queue @ 1446044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1446175979000. Starting simulation...
+info: Entering event queue @ 1446044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1447175979000. Starting simulation...
+info: Entering event queue @ 1447044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1448175979000. Starting simulation...
+info: Entering event queue @ 1448044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1449175979000. Starting simulation...
-info: Entering event queue @ 1456175972000. Starting simulation...
-info: Entering event queue @ 1456175979000. Starting simulation...
+info: Entering event queue @ 1449044727500. Starting simulation...
+info: Entering event queue @ 1456044720500. Starting simulation...
+info: Entering event queue @ 1456044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1456175983500. Starting simulation...
+info: Entering event queue @ 1456044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1457175983500. Starting simulation...
+info: Entering event queue @ 1457044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1458175983500. Starting simulation...
+info: Entering event queue @ 1458044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1459175983500. Starting simulation...
-info: Entering event queue @ 1466175972000. Starting simulation...
-info: Entering event queue @ 1466175979000. Starting simulation...
+info: Entering event queue @ 1459044727500. Starting simulation...
+info: Entering event queue @ 1466044720500. Starting simulation...
+info: Entering event queue @ 1466044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1466175983500. Starting simulation...
+info: Entering event queue @ 1466044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1467175983500. Starting simulation...
+info: Entering event queue @ 1467044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1468175983500. Starting simulation...
+info: Entering event queue @ 1468044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1469175983500. Starting simulation...
-info: Entering event queue @ 1476175972000. Starting simulation...
-info: Entering event queue @ 1476175978500. Starting simulation...
+info: Entering event queue @ 1469044727500. Starting simulation...
+info: Entering event queue @ 1476044720500. Starting simulation...
+info: Entering event queue @ 1476044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1476175979000. Starting simulation...
+info: Entering event queue @ 1476044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1477175979000. Starting simulation...
+info: Entering event queue @ 1477044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1478175979000. Starting simulation...
+info: Entering event queue @ 1478044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1479175979000. Starting simulation...
-info: Entering event queue @ 1486175972000. Starting simulation...
-info: Entering event queue @ 1486175978500. Starting simulation...
+info: Entering event queue @ 1479044727500. Starting simulation...
+info: Entering event queue @ 1486044720500. Starting simulation...
+info: Entering event queue @ 1486044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1486175979000. Starting simulation...
+info: Entering event queue @ 1486044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1487175979000. Starting simulation...
+info: Entering event queue @ 1487044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1488175979000. Starting simulation...
+info: Entering event queue @ 1488044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1489175979000. Starting simulation...
-info: Entering event queue @ 1496175972000. Starting simulation...
-info: Entering event queue @ 1496175978500. Starting simulation...
+info: Entering event queue @ 1489044727500. Starting simulation...
+info: Entering event queue @ 1496044720500. Starting simulation...
+info: Entering event queue @ 1496044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1496175979000. Starting simulation...
+info: Entering event queue @ 1496044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1497175979000. Starting simulation...
+info: Entering event queue @ 1497044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1498175979000. Starting simulation...
+info: Entering event queue @ 1498044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1499175979000. Starting simulation...
-info: Entering event queue @ 1506175972000. Starting simulation...
-info: Entering event queue @ 1506175978500. Starting simulation...
+info: Entering event queue @ 1499044727500. Starting simulation...
+info: Entering event queue @ 1506044720500. Starting simulation...
+info: Entering event queue @ 1506044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1506175979000. Starting simulation...
+info: Entering event queue @ 1506044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1507175979000. Starting simulation...
+info: Entering event queue @ 1507044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1508175979000. Starting simulation...
+info: Entering event queue @ 1508044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1509175979000. Starting simulation...
-info: Entering event queue @ 1516175972000. Starting simulation...
-info: Entering event queue @ 1516175979000. Starting simulation...
+info: Entering event queue @ 1509044727500. Starting simulation...
+info: Entering event queue @ 1516044720500. Starting simulation...
+info: Entering event queue @ 1516044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1516175983500. Starting simulation...
+info: Entering event queue @ 1516044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1517175983500. Starting simulation...
+info: Entering event queue @ 1517044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1518175983500. Starting simulation...
+info: Entering event queue @ 1518044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1519175983500. Starting simulation...
-info: Entering event queue @ 1526175972000. Starting simulation...
-info: Entering event queue @ 1526175979000. Starting simulation...
+info: Entering event queue @ 1519044727500. Starting simulation...
+info: Entering event queue @ 1526044720500. Starting simulation...
+info: Entering event queue @ 1526044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1526175983500. Starting simulation...
+info: Entering event queue @ 1526044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1527175983500. Starting simulation...
+info: Entering event queue @ 1527044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1528175983500. Starting simulation...
+info: Entering event queue @ 1528044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1529175983500. Starting simulation...
+info: Entering event queue @ 1529044727500. Starting simulation...
+info: Entering event queue @ 1536044720500. Starting simulation...
+info: Entering event queue @ 1536044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1536175973000. Starting simulation...
+info: Entering event queue @ 1536044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1537175973000. Starting simulation...
+info: Entering event queue @ 1537044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1538175973000. Starting simulation...
+info: Entering event queue @ 1538044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1539175973000. Starting simulation...
+info: Entering event queue @ 1539044727500. Starting simulation...
+info: Entering event queue @ 1546044720500. Starting simulation...
+info: Entering event queue @ 1546044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1546175973000. Starting simulation...
+info: Entering event queue @ 1546044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1547175973000. Starting simulation...
+info: Entering event queue @ 1547044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1548175973000. Starting simulation...
+info: Entering event queue @ 1548044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1549175973000. Starting simulation...
-info: Entering event queue @ 1556175972000. Starting simulation...
-info: Entering event queue @ 1556175979000. Starting simulation...
+info: Entering event queue @ 1549044727500. Starting simulation...
+info: Entering event queue @ 1556044720500. Starting simulation...
+info: Entering event queue @ 1556044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1556175983500. Starting simulation...
+info: Entering event queue @ 1556044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1557175983500. Starting simulation...
+info: Entering event queue @ 1557044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1558175983500. Starting simulation...
+info: Entering event queue @ 1558044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1559175983500. Starting simulation...
-info: Entering event queue @ 1566175973000. Starting simulation...
-info: Entering event queue @ 1566175981500. Starting simulation...
+info: Entering event queue @ 1559044727500. Starting simulation...
+info: Entering event queue @ 1566044720500. Starting simulation...
+info: Entering event queue @ 1566044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1566175986000. Starting simulation...
+info: Entering event queue @ 1566044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1567175986000. Starting simulation...
+info: Entering event queue @ 1567044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1568175986000. Starting simulation...
+info: Entering event queue @ 1568044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1569175986000. Starting simulation...
-info: Entering event queue @ 1576175972000. Starting simulation...
-info: Entering event queue @ 1576429705000. Starting simulation...
+info: Entering event queue @ 1569044727500. Starting simulation...
+info: Entering event queue @ 1576044720500. Starting simulation...
+info: Entering event queue @ 1576298326000. Starting simulation...
switching cpus
-info: Entering event queue @ 1576429707000. Starting simulation...
+info: Entering event queue @ 1576298328000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1577429707000. Starting simulation...
+info: Entering event queue @ 1577298328000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1578429707000. Starting simulation...
+info: Entering event queue @ 1578298328000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1579429707000. Starting simulation...
-info: Entering event queue @ 1586175972000. Starting simulation...
-info: Entering event queue @ 1586175978500. Starting simulation...
+info: Entering event queue @ 1579298328000. Starting simulation...
+info: Entering event queue @ 1586044720500. Starting simulation...
+info: Entering event queue @ 1586044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1586175979000. Starting simulation...
+info: Entering event queue @ 1586044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1587175979000. Starting simulation...
+info: Entering event queue @ 1587044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1588175979000. Starting simulation...
+info: Entering event queue @ 1588044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1589175979000. Starting simulation...
-info: Entering event queue @ 1596175972000. Starting simulation...
-info: Entering event queue @ 1596175978500. Starting simulation...
+info: Entering event queue @ 1589044727500. Starting simulation...
+info: Entering event queue @ 1596044720500. Starting simulation...
+info: Entering event queue @ 1596044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1596175979000. Starting simulation...
+info: Entering event queue @ 1596044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1597175979000. Starting simulation...
+info: Entering event queue @ 1597044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1598175979000. Starting simulation...
+info: Entering event queue @ 1598044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1599175979000. Starting simulation...
-info: Entering event queue @ 1606175972000. Starting simulation...
-info: Entering event queue @ 1606175978500. Starting simulation...
+info: Entering event queue @ 1599044727500. Starting simulation...
+info: Entering event queue @ 1606044720500. Starting simulation...
+info: Entering event queue @ 1606044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1606175979000. Starting simulation...
+info: Entering event queue @ 1606044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1607175979000. Starting simulation...
+info: Entering event queue @ 1607044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1608175979000. Starting simulation...
-info: Entering event queue @ 1609165996000. Starting simulation...
+info: Entering event queue @ 1608044727500. Starting simulation...
+info: Entering event queue @ 1609034473000. Starting simulation...
switching cpus
-info: Entering event queue @ 1609165998000. Starting simulation...
+info: Entering event queue @ 1609034475000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1610165998000. Starting simulation...
-info: Entering event queue @ 1616175972000. Starting simulation...
-info: Entering event queue @ 1616175979000. Starting simulation...
+info: Entering event queue @ 1610034475000. Starting simulation...
+info: Entering event queue @ 1616044720500. Starting simulation...
+info: Entering event queue @ 1616044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1616175983500. Starting simulation...
+info: Entering event queue @ 1616044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1617175983500. Starting simulation...
+info: Entering event queue @ 1617044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1618175983500. Starting simulation...
+info: Entering event queue @ 1618044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1619175983500. Starting simulation...
-info: Entering event queue @ 1626175972000. Starting simulation...
-info: Entering event queue @ 1626175979000. Starting simulation...
+info: Entering event queue @ 1619044727500. Starting simulation...
+info: Entering event queue @ 1626044720500. Starting simulation...
+info: Entering event queue @ 1626044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1626175983500. Starting simulation...
+info: Entering event queue @ 1626044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1627175983500. Starting simulation...
+info: Entering event queue @ 1627044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1628175983500. Starting simulation...
+info: Entering event queue @ 1628044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1629175983500. Starting simulation...
-info: Entering event queue @ 1636175972000. Starting simulation...
-info: Entering event queue @ 1636175978500. Starting simulation...
+info: Entering event queue @ 1629044727500. Starting simulation...
+info: Entering event queue @ 1636044720500. Starting simulation...
+info: Entering event queue @ 1636044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1636175979000. Starting simulation...
+info: Entering event queue @ 1636044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1637175979000. Starting simulation...
+info: Entering event queue @ 1637044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1638175979000. Starting simulation...
+info: Entering event queue @ 1638044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1639175979000. Starting simulation...
-info: Entering event queue @ 1646175972000. Starting simulation...
-info: Entering event queue @ 1646175978500. Starting simulation...
+info: Entering event queue @ 1639044727500. Starting simulation...
+info: Entering event queue @ 1646044720500. Starting simulation...
+info: Entering event queue @ 1646044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1646175979000. Starting simulation...
+info: Entering event queue @ 1646044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1647175979000. Starting simulation...
+info: Entering event queue @ 1647044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1648175979000. Starting simulation...
+info: Entering event queue @ 1648044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1649175979000. Starting simulation...
-info: Entering event queue @ 1656175972000. Starting simulation...
-info: Entering event queue @ 1656175978500. Starting simulation...
+info: Entering event queue @ 1649044727500. Starting simulation...
+info: Entering event queue @ 1656044720500. Starting simulation...
+info: Entering event queue @ 1656044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1656175979000. Starting simulation...
+info: Entering event queue @ 1656044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1657175979000. Starting simulation...
+info: Entering event queue @ 1657044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1658175979000. Starting simulation...
+info: Entering event queue @ 1658044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1659175979000. Starting simulation...
-info: Entering event queue @ 1666175972000. Starting simulation...
-info: Entering event queue @ 1666175978500. Starting simulation...
+info: Entering event queue @ 1659044727500. Starting simulation...
+info: Entering event queue @ 1666044720500. Starting simulation...
+info: Entering event queue @ 1666044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1666175979000. Starting simulation...
+info: Entering event queue @ 1666044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1667175979000. Starting simulation...
+info: Entering event queue @ 1667044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1668175979000. Starting simulation...
+info: Entering event queue @ 1668044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1669175979000. Starting simulation...
-info: Entering event queue @ 1676175972000. Starting simulation...
-info: Entering event queue @ 1676175979000. Starting simulation...
+info: Entering event queue @ 1669044727500. Starting simulation...
+info: Entering event queue @ 1676044720500. Starting simulation...
+info: Entering event queue @ 1676044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1676175983500. Starting simulation...
+info: Entering event queue @ 1676044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1677175983500. Starting simulation...
+info: Entering event queue @ 1677044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1678175983500. Starting simulation...
+info: Entering event queue @ 1678044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1679175983500. Starting simulation...
-info: Entering event queue @ 1686175972000. Starting simulation...
-info: Entering event queue @ 1686175979000. Starting simulation...
+info: Entering event queue @ 1679044727500. Starting simulation...
+info: Entering event queue @ 1686044720500. Starting simulation...
+info: Entering event queue @ 1686044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1686175983500. Starting simulation...
+info: Entering event queue @ 1686044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1687175983500. Starting simulation...
+info: Entering event queue @ 1687044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1688175983500. Starting simulation...
+info: Entering event queue @ 1688044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1689175983500. Starting simulation...
+info: Entering event queue @ 1689044727500. Starting simulation...
+info: Entering event queue @ 1696044720500. Starting simulation...
+info: Entering event queue @ 1696044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1696175973000. Starting simulation...
+info: Entering event queue @ 1696044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1697175973000. Starting simulation...
+info: Entering event queue @ 1697044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1698175973000. Starting simulation...
+info: Entering event queue @ 1698044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1699175973000. Starting simulation...
-info: Entering event queue @ 1706175973000. Starting simulation...
-info: Entering event queue @ 1707375031000. Starting simulation...
+info: Entering event queue @ 1699044727500. Starting simulation...
+info: Entering event queue @ 1706044720500. Starting simulation...
+info: Entering event queue @ 1707243505000. Starting simulation...
switching cpus
-info: Entering event queue @ 1707375033000. Starting simulation...
+info: Entering event queue @ 1707243507000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1708375033000. Starting simulation...
+info: Entering event queue @ 1708243507000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1709375033000. Starting simulation...
+info: Entering event queue @ 1709243507000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1710375033000. Starting simulation...
-info: Entering event queue @ 1716175972000. Starting simulation...
-info: Entering event queue @ 1716175979000. Starting simulation...
+info: Entering event queue @ 1710243507000. Starting simulation...
+info: Entering event queue @ 1716044720500. Starting simulation...
+info: Entering event queue @ 1716044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1716175983500. Starting simulation...
+info: Entering event queue @ 1716044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1717175983500. Starting simulation...
+info: Entering event queue @ 1717044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1718175983500. Starting simulation...
+info: Entering event queue @ 1718044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1719175983500. Starting simulation...
-info: Entering event queue @ 1726175973000. Starting simulation...
-info: Entering event queue @ 1726175981500. Starting simulation...
+info: Entering event queue @ 1719044727500. Starting simulation...
+info: Entering event queue @ 1726044720500. Starting simulation...
+info: Entering event queue @ 1726044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1726175986000. Starting simulation...
+info: Entering event queue @ 1726044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1727175986000. Starting simulation...
+info: Entering event queue @ 1727044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1728175986000. Starting simulation...
+info: Entering event queue @ 1728044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1729175986000. Starting simulation...
-info: Entering event queue @ 1736175972000. Starting simulation...
-info: Entering event queue @ 1736175978500. Starting simulation...
+info: Entering event queue @ 1729044727500. Starting simulation...
+info: Entering event queue @ 1736044720500. Starting simulation...
+info: Entering event queue @ 1736044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1736175979000. Starting simulation...
+info: Entering event queue @ 1736044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1737175979000. Starting simulation...
+info: Entering event queue @ 1737044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1738175979000. Starting simulation...
+info: Entering event queue @ 1738044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1739175979000. Starting simulation...
-info: Entering event queue @ 1746175972000. Starting simulation...
-info: Entering event queue @ 1746175978500. Starting simulation...
+info: Entering event queue @ 1739044727500. Starting simulation...
+info: Entering event queue @ 1746044720500. Starting simulation...
+info: Entering event queue @ 1746044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1746175979000. Starting simulation...
+info: Entering event queue @ 1746044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1747175979000. Starting simulation...
+info: Entering event queue @ 1747044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1748175979000. Starting simulation...
+info: Entering event queue @ 1748044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1749175979000. Starting simulation...
-info: Entering event queue @ 1756175972000. Starting simulation...
-info: Entering event queue @ 1756175978500. Starting simulation...
+info: Entering event queue @ 1749044727500. Starting simulation...
+info: Entering event queue @ 1756044720500. Starting simulation...
+info: Entering event queue @ 1756044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1756175979000. Starting simulation...
+info: Entering event queue @ 1756044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1757175979000. Starting simulation...
+info: Entering event queue @ 1757044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1758175979000. Starting simulation...
+info: Entering event queue @ 1758044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1759175979000. Starting simulation...
-info: Entering event queue @ 1766175972000. Starting simulation...
-info: Entering event queue @ 1766175978500. Starting simulation...
+info: Entering event queue @ 1759044727500. Starting simulation...
+info: Entering event queue @ 1766044720500. Starting simulation...
+info: Entering event queue @ 1766044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1766175979000. Starting simulation...
+info: Entering event queue @ 1766044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1767175979000. Starting simulation...
+info: Entering event queue @ 1767044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1768175979000. Starting simulation...
+info: Entering event queue @ 1768044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1769175979000. Starting simulation...
-info: Entering event queue @ 1776175972000. Starting simulation...
-info: Entering event queue @ 1776175979000. Starting simulation...
+info: Entering event queue @ 1769044727500. Starting simulation...
+info: Entering event queue @ 1776044720500. Starting simulation...
+info: Entering event queue @ 1776044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1776175983500. Starting simulation...
+info: Entering event queue @ 1776044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1777175983500. Starting simulation...
+info: Entering event queue @ 1777044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1778175983500. Starting simulation...
+info: Entering event queue @ 1778044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1779175983500. Starting simulation...
-info: Entering event queue @ 1786175972000. Starting simulation...
-info: Entering event queue @ 1786175979000. Starting simulation...
+info: Entering event queue @ 1779044727500. Starting simulation...
+info: Entering event queue @ 1786044720500. Starting simulation...
+info: Entering event queue @ 1786044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1786175983500. Starting simulation...
+info: Entering event queue @ 1786044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1787175983500. Starting simulation...
+info: Entering event queue @ 1787044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1788175983500. Starting simulation...
+info: Entering event queue @ 1788044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1789175983500. Starting simulation...
-info: Entering event queue @ 1796175972000. Starting simulation...
-info: Entering event queue @ 1796175978500. Starting simulation...
+info: Entering event queue @ 1789044727500. Starting simulation...
+info: Entering event queue @ 1796044720500. Starting simulation...
+info: Entering event queue @ 1796044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1796175979000. Starting simulation...
+info: Entering event queue @ 1796044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1797175979000. Starting simulation...
+info: Entering event queue @ 1797044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1798175979000. Starting simulation...
+info: Entering event queue @ 1798044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1799175979000. Starting simulation...
-info: Entering event queue @ 1806175972000. Starting simulation...
-info: Entering event queue @ 1806175978500. Starting simulation...
+info: Entering event queue @ 1799044727500. Starting simulation...
+info: Entering event queue @ 1806044720500. Starting simulation...
+info: Entering event queue @ 1806044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1806175979000. Starting simulation...
+info: Entering event queue @ 1806044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1807175979000. Starting simulation...
+info: Entering event queue @ 1807044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1808175979000. Starting simulation...
+info: Entering event queue @ 1808044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1809175979000. Starting simulation...
-info: Entering event queue @ 1816175972000. Starting simulation...
-info: Entering event queue @ 1816175978500. Starting simulation...
+info: Entering event queue @ 1809044727500. Starting simulation...
+info: Entering event queue @ 1816044720500. Starting simulation...
+info: Entering event queue @ 1816044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1816175979000. Starting simulation...
+info: Entering event queue @ 1816044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1817175979000. Starting simulation...
+info: Entering event queue @ 1817044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1818175979000. Starting simulation...
+info: Entering event queue @ 1818044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1819175979000. Starting simulation...
-info: Entering event queue @ 1826175972000. Starting simulation...
-info: Entering event queue @ 1826175978500. Starting simulation...
+info: Entering event queue @ 1819044727500. Starting simulation...
+info: Entering event queue @ 1826044720500. Starting simulation...
+info: Entering event queue @ 1826044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1826175979000. Starting simulation...
+info: Entering event queue @ 1826044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1827175979000. Starting simulation...
+info: Entering event queue @ 1827044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1828175979000. Starting simulation...
+info: Entering event queue @ 1828044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1829175979000. Starting simulation...
-info: Entering event queue @ 1836175972000. Starting simulation...
-info: Entering event queue @ 1836175979000. Starting simulation...
+info: Entering event queue @ 1829044727500. Starting simulation...
+info: Entering event queue @ 1836044720500. Starting simulation...
+info: Entering event queue @ 1836044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1836175983500. Starting simulation...
+info: Entering event queue @ 1836044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1837175983500. Starting simulation...
+info: Entering event queue @ 1837044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1838175983500. Starting simulation...
+info: Entering event queue @ 1838044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1839175983500. Starting simulation...
-info: Entering event queue @ 1846175972000. Starting simulation...
-info: Entering event queue @ 1846175979000. Starting simulation...
+info: Entering event queue @ 1839044727500. Starting simulation...
+info: Entering event queue @ 1846044720500. Starting simulation...
+info: Entering event queue @ 1846044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1846175983500. Starting simulation...
+info: Entering event queue @ 1846044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1847175983500. Starting simulation...
+info: Entering event queue @ 1847044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1848175983500. Starting simulation...
+info: Entering event queue @ 1848044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1849175983500. Starting simulation...
+info: Entering event queue @ 1849044727500. Starting simulation...
+info: Entering event queue @ 1856044720500. Starting simulation...
+info: Entering event queue @ 1856044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1856175973000. Starting simulation...
+info: Entering event queue @ 1856044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1857175973000. Starting simulation...
+info: Entering event queue @ 1857044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1858175973000. Starting simulation...
+info: Entering event queue @ 1858044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1859175973000. Starting simulation...
+info: Entering event queue @ 1859044727500. Starting simulation...
+info: Entering event queue @ 1866044720500. Starting simulation...
+info: Entering event queue @ 1866044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1866175973000. Starting simulation...
+info: Entering event queue @ 1866044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1867175973000. Starting simulation...
+info: Entering event queue @ 1867044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1868175973000. Starting simulation...
+info: Entering event queue @ 1868044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1869175973000. Starting simulation...
-info: Entering event queue @ 1876175972000. Starting simulation...
-info: Entering event queue @ 1876175979000. Starting simulation...
+info: Entering event queue @ 1869044727500. Starting simulation...
+info: Entering event queue @ 1876044720500. Starting simulation...
+info: Entering event queue @ 1876044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1876175983500. Starting simulation...
+info: Entering event queue @ 1876044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1877175983500. Starting simulation...
+info: Entering event queue @ 1877044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1878175983500. Starting simulation...
+info: Entering event queue @ 1878044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1879175983500. Starting simulation...
-info: Entering event queue @ 1886175973000. Starting simulation...
-info: Entering event queue @ 1886175981500. Starting simulation...
+info: Entering event queue @ 1879044727500. Starting simulation...
+info: Entering event queue @ 1886044720500. Starting simulation...
+info: Entering event queue @ 1886044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1886175986000. Starting simulation...
+info: Entering event queue @ 1886044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1887175986000. Starting simulation...
+info: Entering event queue @ 1887044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1888175986000. Starting simulation...
+info: Entering event queue @ 1888044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1889175986000. Starting simulation...
-info: Entering event queue @ 1896175972000. Starting simulation...
-info: Entering event queue @ 1896175978500. Starting simulation...
+info: Entering event queue @ 1889044727500. Starting simulation...
+info: Entering event queue @ 1896044720500. Starting simulation...
+info: Entering event queue @ 1896044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1896175979000. Starting simulation...
+info: Entering event queue @ 1896044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1897175979000. Starting simulation...
+info: Entering event queue @ 1897044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1898175979000. Starting simulation...
+info: Entering event queue @ 1898044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1899175979000. Starting simulation...
-info: Entering event queue @ 1906175972000. Starting simulation...
-info: Entering event queue @ 1906175978500. Starting simulation...
+info: Entering event queue @ 1899044727500. Starting simulation...
+info: Entering event queue @ 1906044720500. Starting simulation...
+info: Entering event queue @ 1906044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1906175979000. Starting simulation...
+info: Entering event queue @ 1906044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1907175979000. Starting simulation...
+info: Entering event queue @ 1907044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1908175979000. Starting simulation...
+info: Entering event queue @ 1908044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1909175979000. Starting simulation...
-info: Entering event queue @ 1916175972000. Starting simulation...
-info: Entering event queue @ 1916175978500. Starting simulation...
+info: Entering event queue @ 1909044727500. Starting simulation...
+info: Entering event queue @ 1916044720500. Starting simulation...
+info: Entering event queue @ 1916044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1916175979000. Starting simulation...
+info: Entering event queue @ 1916044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1917175979000. Starting simulation...
+info: Entering event queue @ 1917044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1918175979000. Starting simulation...
+info: Entering event queue @ 1918044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1919175979000. Starting simulation...
-info: Entering event queue @ 1926175972000. Starting simulation...
-info: Entering event queue @ 1926175978500. Starting simulation...
+info: Entering event queue @ 1919044727500. Starting simulation...
+info: Entering event queue @ 1926044720500. Starting simulation...
+info: Entering event queue @ 1926044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1926175979000. Starting simulation...
+info: Entering event queue @ 1926044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1927175979000. Starting simulation...
+info: Entering event queue @ 1927044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1928175979000. Starting simulation...
+info: Entering event queue @ 1928044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1929175979000. Starting simulation...
-info: Entering event queue @ 1936175972000. Starting simulation...
-info: Entering event queue @ 1936528480000. Starting simulation...
+info: Entering event queue @ 1929044727500. Starting simulation...
+info: Entering event queue @ 1936044720500. Starting simulation...
+info: Entering event queue @ 1936397407000. Starting simulation...
switching cpus
-info: Entering event queue @ 1936528482000. Starting simulation...
+info: Entering event queue @ 1936397409000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1937528482000. Starting simulation...
+info: Entering event queue @ 1937397409000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1938528482000. Starting simulation...
+info: Entering event queue @ 1938397409000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1939528482000. Starting simulation...
-info: Entering event queue @ 1946175972000. Starting simulation...
-info: Entering event queue @ 1946175979000. Starting simulation...
+info: Entering event queue @ 1939397409000. Starting simulation...
+info: Entering event queue @ 1946044720500. Starting simulation...
+info: Entering event queue @ 1946044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1946175983500. Starting simulation...
+info: Entering event queue @ 1946044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1947175983500. Starting simulation...
+info: Entering event queue @ 1947044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1948175983500. Starting simulation...
+info: Entering event queue @ 1948044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1949175983500. Starting simulation...
-info: Entering event queue @ 1956175972000. Starting simulation...
-info: Entering event queue @ 1956175978500. Starting simulation...
+info: Entering event queue @ 1949044727500. Starting simulation...
+info: Entering event queue @ 1956044720500. Starting simulation...
+info: Entering event queue @ 1956044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1956175979000. Starting simulation...
+info: Entering event queue @ 1956044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1957175979000. Starting simulation...
+info: Entering event queue @ 1957044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1958175979000. Starting simulation...
+info: Entering event queue @ 1958044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1959175979000. Starting simulation...
-info: Entering event queue @ 1966175972000. Starting simulation...
-info: Entering event queue @ 1966175978500. Starting simulation...
+info: Entering event queue @ 1959044727500. Starting simulation...
+info: Entering event queue @ 1966044720500. Starting simulation...
+info: Entering event queue @ 1966044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1966175979000. Starting simulation...
+info: Entering event queue @ 1966044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1967175979000. Starting simulation...
+info: Entering event queue @ 1967044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1968175979000. Starting simulation...
-info: Entering event queue @ 1969264621000. Starting simulation...
+info: Entering event queue @ 1968044727500. Starting simulation...
+info: Entering event queue @ 1969133554000. Starting simulation...
switching cpus
-info: Entering event queue @ 1969264623000. Starting simulation...
+info: Entering event queue @ 1969133556000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1970264623000. Starting simulation...
-info: Entering event queue @ 1976175972000. Starting simulation...
-info: Entering event queue @ 1976175978500. Starting simulation...
+info: Entering event queue @ 1970133556000. Starting simulation...
+info: Entering event queue @ 1976044720500. Starting simulation...
+info: Entering event queue @ 1976044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1976175979000. Starting simulation...
+info: Entering event queue @ 1976044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1977175979000. Starting simulation...
+info: Entering event queue @ 1977044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1978175979000. Starting simulation...
+info: Entering event queue @ 1978044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1979175979000. Starting simulation...
-info: Entering event queue @ 1986175972000. Starting simulation...
-info: Entering event queue @ 1986175978500. Starting simulation...
+info: Entering event queue @ 1979044727500. Starting simulation...
+info: Entering event queue @ 1986044720500. Starting simulation...
+info: Entering event queue @ 1986044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1986175979000. Starting simulation...
+info: Entering event queue @ 1986044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1987175979000. Starting simulation...
+info: Entering event queue @ 1987044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1988175979000. Starting simulation...
+info: Entering event queue @ 1988044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1989175979000. Starting simulation...
-info: Entering event queue @ 1996175972000. Starting simulation...
-info: Entering event queue @ 1996175979000. Starting simulation...
+info: Entering event queue @ 1989044727500. Starting simulation...
+info: Entering event queue @ 1996044720500. Starting simulation...
+info: Entering event queue @ 1996044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 1996175983500. Starting simulation...
+info: Entering event queue @ 1996044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 1997175983500. Starting simulation...
+info: Entering event queue @ 1997044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 1998175983500. Starting simulation...
+info: Entering event queue @ 1998044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1999175983500. Starting simulation...
-info: Entering event queue @ 2006175972000. Starting simulation...
-info: Entering event queue @ 2006175979000. Starting simulation...
+info: Entering event queue @ 1999044727500. Starting simulation...
+info: Entering event queue @ 2006044720500. Starting simulation...
+info: Entering event queue @ 2006044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2006175983500. Starting simulation...
+info: Entering event queue @ 2006044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2007175983500. Starting simulation...
+info: Entering event queue @ 2007044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2008175983500. Starting simulation...
+info: Entering event queue @ 2008044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2009175983500. Starting simulation...
+info: Entering event queue @ 2009044727500. Starting simulation...
+info: Entering event queue @ 2016044720500. Starting simulation...
+info: Entering event queue @ 2016044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2016175973000. Starting simulation...
+info: Entering event queue @ 2016044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2017175973000. Starting simulation...
+info: Entering event queue @ 2017044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2018175973000. Starting simulation...
+info: Entering event queue @ 2018044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2019175973000. Starting simulation...
-info: Entering event queue @ 2026175973000. Starting simulation...
-info: Entering event queue @ 2026175980500. Starting simulation...
+info: Entering event queue @ 2019044727500. Starting simulation...
+info: Entering event queue @ 2026044720500. Starting simulation...
+info: Entering event queue @ 2026044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2026175985000. Starting simulation...
+info: Entering event queue @ 2026044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2027175985000. Starting simulation...
+info: Entering event queue @ 2027044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2028175985000. Starting simulation...
+info: Entering event queue @ 2028044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2029175985000. Starting simulation...
-info: Entering event queue @ 2036175972000. Starting simulation...
-info: Entering event queue @ 2036175979000. Starting simulation...
+info: Entering event queue @ 2029044727500. Starting simulation...
+info: Entering event queue @ 2036044720500. Starting simulation...
+info: Entering event queue @ 2036044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2036175983500. Starting simulation...
+info: Entering event queue @ 2036044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2037175983500. Starting simulation...
+info: Entering event queue @ 2037044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2038175983500. Starting simulation...
+info: Entering event queue @ 2038044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2039175983500. Starting simulation...
-info: Entering event queue @ 2046175973000. Starting simulation...
-info: Entering event queue @ 2046175981500. Starting simulation...
+info: Entering event queue @ 2039044727500. Starting simulation...
+info: Entering event queue @ 2046044720500. Starting simulation...
+info: Entering event queue @ 2046044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2046175986000. Starting simulation...
+info: Entering event queue @ 2046044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2047175986000. Starting simulation...
+info: Entering event queue @ 2047044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2048175986000. Starting simulation...
+info: Entering event queue @ 2048044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2049175986000. Starting simulation...
-info: Entering event queue @ 2056175972000. Starting simulation...
-info: Entering event queue @ 2056175978500. Starting simulation...
+info: Entering event queue @ 2049044727500. Starting simulation...
+info: Entering event queue @ 2056044720500. Starting simulation...
+info: Entering event queue @ 2056044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2056175979000. Starting simulation...
+info: Entering event queue @ 2056044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2057175979000. Starting simulation...
+info: Entering event queue @ 2057044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2058175979000. Starting simulation...
+info: Entering event queue @ 2058044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2059175979000. Starting simulation...
-info: Entering event queue @ 2066175972000. Starting simulation...
-info: Entering event queue @ 2067473656000. Starting simulation...
+info: Entering event queue @ 2059044727500. Starting simulation...
+info: Entering event queue @ 2066044720500. Starting simulation...
+info: Entering event queue @ 2067342280000. Starting simulation...
switching cpus
-info: Entering event queue @ 2067473658000. Starting simulation...
+info: Entering event queue @ 2067342282000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2068473658000. Starting simulation...
+info: Entering event queue @ 2068342282000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2069473658000. Starting simulation...
+info: Entering event queue @ 2069342282000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2070473658000. Starting simulation...
-info: Entering event queue @ 2076175972000. Starting simulation...
-info: Entering event queue @ 2076175978500. Starting simulation...
+info: Entering event queue @ 2070342282000. Starting simulation...
+info: Entering event queue @ 2076044720500. Starting simulation...
+info: Entering event queue @ 2076044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2076175979000. Starting simulation...
+info: Entering event queue @ 2076044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2077175979000. Starting simulation...
+info: Entering event queue @ 2077044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2078175979000. Starting simulation...
+info: Entering event queue @ 2078044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2079175979000. Starting simulation...
-info: Entering event queue @ 2086175972000. Starting simulation...
-info: Entering event queue @ 2086175978500. Starting simulation...
+info: Entering event queue @ 2079044727500. Starting simulation...
+info: Entering event queue @ 2086044720500. Starting simulation...
+info: Entering event queue @ 2086044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2086175979000. Starting simulation...
+info: Entering event queue @ 2086044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2087175979000. Starting simulation...
+info: Entering event queue @ 2087044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2088175979000. Starting simulation...
+info: Entering event queue @ 2088044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2089175979000. Starting simulation...
-info: Entering event queue @ 2096175972000. Starting simulation...
-info: Entering event queue @ 2096175979000. Starting simulation...
+info: Entering event queue @ 2089044727500. Starting simulation...
+info: Entering event queue @ 2096044720500. Starting simulation...
+info: Entering event queue @ 2096044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2096175983500. Starting simulation...
+info: Entering event queue @ 2096044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2097175983500. Starting simulation...
+info: Entering event queue @ 2097044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2098175983500. Starting simulation...
+info: Entering event queue @ 2098044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2099175983500. Starting simulation...
-info: Entering event queue @ 2106175972000. Starting simulation...
-info: Entering event queue @ 2106175979000. Starting simulation...
+info: Entering event queue @ 2099044727500. Starting simulation...
+info: Entering event queue @ 2106044720500. Starting simulation...
+info: Entering event queue @ 2106044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2106175983500. Starting simulation...
+info: Entering event queue @ 2106044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2107175983500. Starting simulation...
+info: Entering event queue @ 2107044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2108175983500. Starting simulation...
+info: Entering event queue @ 2108044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2109175983500. Starting simulation...
-info: Entering event queue @ 2116175972000. Starting simulation...
-info: Entering event queue @ 2116175978500. Starting simulation...
+info: Entering event queue @ 2109044727500. Starting simulation...
+info: Entering event queue @ 2116044720500. Starting simulation...
+info: Entering event queue @ 2116044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2116175979000. Starting simulation...
+info: Entering event queue @ 2116044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2117175979000. Starting simulation...
+info: Entering event queue @ 2117044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2118175979000. Starting simulation...
+info: Entering event queue @ 2118044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2119175979000. Starting simulation...
-info: Entering event queue @ 2126175972000. Starting simulation...
-info: Entering event queue @ 2126175978500. Starting simulation...
+info: Entering event queue @ 2119044727500. Starting simulation...
+info: Entering event queue @ 2126044720500. Starting simulation...
+info: Entering event queue @ 2126044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2126175979000. Starting simulation...
+info: Entering event queue @ 2126044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2127175979000. Starting simulation...
+info: Entering event queue @ 2127044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2128175979000. Starting simulation...
+info: Entering event queue @ 2128044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2129175979000. Starting simulation...
-info: Entering event queue @ 2136175972000. Starting simulation...
-info: Entering event queue @ 2136175978500. Starting simulation...
+info: Entering event queue @ 2129044727500. Starting simulation...
+info: Entering event queue @ 2136044720500. Starting simulation...
+info: Entering event queue @ 2136044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2136175979000. Starting simulation...
+info: Entering event queue @ 2136044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2137175979000. Starting simulation...
+info: Entering event queue @ 2137044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2138175979000. Starting simulation...
+info: Entering event queue @ 2138044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2139175979000. Starting simulation...
-info: Entering event queue @ 2146175972000. Starting simulation...
-info: Entering event queue @ 2146175978500. Starting simulation...
+info: Entering event queue @ 2139044727500. Starting simulation...
+info: Entering event queue @ 2146044720500. Starting simulation...
+info: Entering event queue @ 2146044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2146175979000. Starting simulation...
+info: Entering event queue @ 2146044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2147175979000. Starting simulation...
+info: Entering event queue @ 2147044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2148175979000. Starting simulation...
+info: Entering event queue @ 2148044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2149175979000. Starting simulation...
-info: Entering event queue @ 2156175972000. Starting simulation...
-info: Entering event queue @ 2156175979000. Starting simulation...
+info: Entering event queue @ 2149044727500. Starting simulation...
+info: Entering event queue @ 2156044720500. Starting simulation...
+info: Entering event queue @ 2156044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2156175983500. Starting simulation...
+info: Entering event queue @ 2156044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2157175983500. Starting simulation...
+info: Entering event queue @ 2157044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2158175983500. Starting simulation...
+info: Entering event queue @ 2158044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2159175983500. Starting simulation...
-info: Entering event queue @ 2166175972000. Starting simulation...
-info: Entering event queue @ 2166175979000. Starting simulation...
+info: Entering event queue @ 2159044727500. Starting simulation...
+info: Entering event queue @ 2166044720500. Starting simulation...
+info: Entering event queue @ 2166044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2166175983500. Starting simulation...
+info: Entering event queue @ 2166044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2167175983500. Starting simulation...
+info: Entering event queue @ 2167044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2168175983500. Starting simulation...
+info: Entering event queue @ 2168044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2169175983500. Starting simulation...
-info: Entering event queue @ 2176175972000. Starting simulation...
-info: Entering event queue @ 2176175979000. Starting simulation...
+info: Entering event queue @ 2169044727500. Starting simulation...
+info: Entering event queue @ 2176044720500. Starting simulation...
+info: Entering event queue @ 2176044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2176175983500. Starting simulation...
+info: Entering event queue @ 2176044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2177175983500. Starting simulation...
+info: Entering event queue @ 2177044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2178175983500. Starting simulation...
+info: Entering event queue @ 2178044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2179175983500. Starting simulation...
-info: Entering event queue @ 2186175972000. Starting simulation...
-info: Entering event queue @ 2186175979000. Starting simulation...
+info: Entering event queue @ 2179044727500. Starting simulation...
+info: Entering event queue @ 2186044720500. Starting simulation...
+info: Entering event queue @ 2186044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2186175983500. Starting simulation...
+info: Entering event queue @ 2186044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2187175983500. Starting simulation...
+info: Entering event queue @ 2187044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2188175983500. Starting simulation...
+info: Entering event queue @ 2188044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2189175983500. Starting simulation...
+info: Entering event queue @ 2189044727500. Starting simulation...
+info: Entering event queue @ 2196044720500. Starting simulation...
+info: Entering event queue @ 2196044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2196175973000. Starting simulation...
+info: Entering event queue @ 2196044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2197175973000. Starting simulation...
+info: Entering event queue @ 2197044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2198175973000. Starting simulation...
+info: Entering event queue @ 2198044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2199175973000. Starting simulation...
+info: Entering event queue @ 2199044727500. Starting simulation...
+info: Entering event queue @ 2206044720500. Starting simulation...
+info: Entering event queue @ 2206044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2206175973000. Starting simulation...
+info: Entering event queue @ 2206044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2207175973000. Starting simulation...
+info: Entering event queue @ 2207044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2208175973000. Starting simulation...
+info: Entering event queue @ 2208044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2209175973000. Starting simulation...
-info: Entering event queue @ 2216175972000. Starting simulation...
-info: Entering event queue @ 2216175978500. Starting simulation...
+info: Entering event queue @ 2209044727500. Starting simulation...
+info: Entering event queue @ 2216044720500. Starting simulation...
+info: Entering event queue @ 2216044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2216175979000. Starting simulation...
+info: Entering event queue @ 2216044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2217175979000. Starting simulation...
+info: Entering event queue @ 2217044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2218175979000. Starting simulation...
+info: Entering event queue @ 2218044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2219175979000. Starting simulation...
-info: Entering event queue @ 2226175972000. Starting simulation...
-info: Entering event queue @ 2226175978500. Starting simulation...
+info: Entering event queue @ 2219044727500. Starting simulation...
+info: Entering event queue @ 2226044720500. Starting simulation...
+info: Entering event queue @ 2226044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2226175979000. Starting simulation...
+info: Entering event queue @ 2226044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2227175979000. Starting simulation...
+info: Entering event queue @ 2227044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2228175979000. Starting simulation...
+info: Entering event queue @ 2228044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2229175979000. Starting simulation...
-info: Entering event queue @ 2236175972000. Starting simulation...
-info: Entering event queue @ 2236175978500. Starting simulation...
+info: Entering event queue @ 2229044727500. Starting simulation...
+info: Entering event queue @ 2236044720500. Starting simulation...
+info: Entering event queue @ 2236044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2236175979000. Starting simulation...
+info: Entering event queue @ 2236044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2237175979000. Starting simulation...
+info: Entering event queue @ 2237044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2238175979000. Starting simulation...
+info: Entering event queue @ 2238044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2239175979000. Starting simulation...
-info: Entering event queue @ 2246175972000. Starting simulation...
-info: Entering event queue @ 2246175978500. Starting simulation...
+info: Entering event queue @ 2239044727500. Starting simulation...
+info: Entering event queue @ 2246044720500. Starting simulation...
+info: Entering event queue @ 2246044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2246175979000. Starting simulation...
+info: Entering event queue @ 2246044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2247175979000. Starting simulation...
+info: Entering event queue @ 2247044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2248175979000. Starting simulation...
+info: Entering event queue @ 2248044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2249175979000. Starting simulation...
-info: Entering event queue @ 2256175972000. Starting simulation...
-info: Entering event queue @ 2256175979000. Starting simulation...
+info: Entering event queue @ 2249044727500. Starting simulation...
+info: Entering event queue @ 2256044720500. Starting simulation...
+info: Entering event queue @ 2256044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2256175983500. Starting simulation...
+info: Entering event queue @ 2256044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2257175983500. Starting simulation...
+info: Entering event queue @ 2257044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
switching cpus
-info: Entering event queue @ 2258175983500. Starting simulation...
+info: Entering event queue @ 2258044727500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2259175983500. Starting simulation...
-info: Entering event queue @ 2266175972000. Starting simulation...
-info: Entering event queue @ 2266175979000. Starting simulation...
+info: Entering event queue @ 2259044727500. Starting simulation...
+info: Entering event queue @ 2266044720500. Starting simulation...
+info: Entering event queue @ 2266044727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2266175983500. Starting simulation...
+info: Entering event queue @ 2266044727500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2267175983500. Starting simulation...
+info: Entering event queue @ 2267044727500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2268175983500. Starting simulation...
+info: Entering event queue @ 2268044727500. Starting simulation...
switching cpus
-info: Entering event queue @ 2268175984500. Starting simulation...
+info: Entering event queue @ 2268044728500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2269175984500. Starting simulation...
+info: Entering event queue @ 2269044728500. Starting simulation...
switching cpus
-info: Entering event queue @ 2269176099000. Starting simulation...
+info: Entering event queue @ 2269044739000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2270176099000. Starting simulation...
switching cpus
-info: Entering event queue @ 2270176101000. Starting simulation...
+info: Entering event queue @ 2270044739000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2271176101000. Starting simulation...
+info: Entering event queue @ 2271044739000. Starting simulation...
switching cpus
-info: Entering event queue @ 2271176134000. Starting simulation...
+info: Entering event queue @ 2271044767000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2272176134000. Starting simulation...
+info: Entering event queue @ 2272044767000. Starting simulation...
switching cpus
-info: Entering event queue @ 2272176298000. Starting simulation...
+info: Entering event queue @ 2272044790000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2273176298000. Starting simulation...
+info: Entering event queue @ 2273044790000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2274176298000. Starting simulation...
+info: Entering event queue @ 2274044790000. Starting simulation...
switching cpus
-info: Entering event queue @ 2274176358000. Starting simulation...
+info: Entering event queue @ 2274044828000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2275176358000. Starting simulation...
+info: Entering event queue @ 2275044828000. Starting simulation...
switching cpus
-info: Entering event queue @ 2275176444000. Starting simulation...
+info: Entering event queue @ 2275044925000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2276176444000. Starting simulation...
+info: Entering event queue @ 2276044925000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2277176444000. Starting simulation...
+info: Entering event queue @ 2277044925000. Starting simulation...
switching cpus
-info: Entering event queue @ 2277176548000. Starting simulation...
+info: Entering event queue @ 2277045053000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2278176548000. Starting simulation...
+info: Entering event queue @ 2278045053000. Starting simulation...
switching cpus
-info: Entering event queue @ 2278176623000. Starting simulation...
+info: Entering event queue @ 2278045122000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2279176623000. Starting simulation...
+info: Entering event queue @ 2279045122000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2280176623000. Starting simulation...
+info: Entering event queue @ 2280045122000. Starting simulation...
switching cpus
-info: Entering event queue @ 2280176733000. Starting simulation...
+info: Entering event queue @ 2280045138000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2281176733000. Starting simulation...
+info: Entering event queue @ 2281045138000. Starting simulation...
switching cpus
-info: Entering event queue @ 2281177431000. Starting simulation...
+info: Entering event queue @ 2281045900000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2282177431000. Starting simulation...
+info: Entering event queue @ 2282045900000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2283177431000. Starting simulation...
+info: Entering event queue @ 2283045900000. Starting simulation...
switching cpus
-info: Entering event queue @ 2283177432000. Starting simulation...
+info: Entering event queue @ 2283045901000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2284177432000. Starting simulation...
+info: Entering event queue @ 2284045901000. Starting simulation...
switching cpus
-info: Entering event queue @ 2284177537000. Starting simulation...
+info: Entering event queue @ 2284045960000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2285177537000. Starting simulation...
+info: Entering event queue @ 2285045960000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2286177537000. Starting simulation...
+info: Entering event queue @ 2286045960000. Starting simulation...
switching cpus
-info: Entering event queue @ 2286177620000. Starting simulation...
+info: Entering event queue @ 2286045982000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2287177620000. Starting simulation...
+info: Entering event queue @ 2287045982000. Starting simulation...
switching cpus
-info: Entering event queue @ 2287177681000. Starting simulation...
+info: Entering event queue @ 2287045989000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2288177681000. Starting simulation...
+info: Entering event queue @ 2288045989000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2289177681000. Starting simulation...
+info: Entering event queue @ 2289045989000. Starting simulation...
switching cpus
-info: Entering event queue @ 2289177796000. Starting simulation...
+info: Entering event queue @ 2289046000000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2290177796000. Starting simulation...
+info: Entering event queue @ 2290046000000. Starting simulation...
switching cpus
-info: Entering event queue @ 2290177891000. Starting simulation...
+info: Entering event queue @ 2290046070000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2291177891000. Starting simulation...
+info: Entering event queue @ 2291046070000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2292177891000. Starting simulation...
+info: Entering event queue @ 2292046070000. Starting simulation...
switching cpus
-info: Entering event queue @ 2292177955000. Starting simulation...
+info: Entering event queue @ 2292046106000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2293177955000. Starting simulation...
+info: Entering event queue @ 2293046106000. Starting simulation...
switching cpus
-info: Entering event queue @ 2293178118500. Starting simulation...
+info: Entering event queue @ 2293046137000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2294178118500. Starting simulation...
+info: Entering event queue @ 2294046137000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2295178118500. Starting simulation...
-info: Entering event queue @ 2296627561000. Starting simulation...
+info: Entering event queue @ 2295046137000. Starting simulation...
+info: Entering event queue @ 2296496182000. Starting simulation...
switching cpus
-info: Entering event queue @ 2296627563000. Starting simulation...
+info: Entering event queue @ 2296496184000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2297627563000. Starting simulation...
+info: Entering event queue @ 2297496184000. Starting simulation...
switching cpus
-info: Entering event queue @ 2297627577000. Starting simulation...
+info: Entering event queue @ 2297496268000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2298627577000. Starting simulation...
+info: Entering event queue @ 2298496268000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2299627577000. Starting simulation...
+info: Entering event queue @ 2299496268000. Starting simulation...
switching cpus
-info: Entering event queue @ 2299627643000. Starting simulation...
+info: Entering event queue @ 2299496348000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2300627643000. Starting simulation...
+info: Entering event queue @ 2300496348000. Starting simulation...
switching cpus
-info: Entering event queue @ 2300627767000. Starting simulation...
+info: Entering event queue @ 2300496430000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2301627767000. Starting simulation...
+info: Entering event queue @ 2301496430000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2302627767000. Starting simulation...
+info: Entering event queue @ 2302496430000. Starting simulation...
switching cpus
-info: Entering event queue @ 2302627826000. Starting simulation...
+info: Entering event queue @ 2302496531000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2303627826000. Starting simulation...
+info: Entering event queue @ 2303496531000. Starting simulation...
switching cpus
-info: Entering event queue @ 2303627914000. Starting simulation...
+info: Entering event queue @ 2303496584000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2304627914000. Starting simulation...
+info: Entering event queue @ 2304496584000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2305627914000. Starting simulation...
+info: Entering event queue @ 2305496584000. Starting simulation...
switching cpus
-info: Entering event queue @ 2305628068000. Starting simulation...
+info: Entering event queue @ 2305496661000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2306628068000. Starting simulation...
+info: Entering event queue @ 2306496661000. Starting simulation...
switching cpus
-info: Entering event queue @ 2306628219000. Starting simulation...
+info: Entering event queue @ 2306496732000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2307628219000. Starting simulation...
+info: Entering event queue @ 2307496732000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2308628219000. Starting simulation...
+info: Entering event queue @ 2308496732000. Starting simulation...
switching cpus
-info: Entering event queue @ 2308628231000. Starting simulation...
+info: Entering event queue @ 2308496815000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2309628231000. Starting simulation...
+info: Entering event queue @ 2309496815000. Starting simulation...
switching cpus
-info: Entering event queue @ 2309628374500. Starting simulation...
+info: Entering event queue @ 2309496944500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2310628374500. Starting simulation...
+info: Entering event queue @ 2310496944500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2311628374500. Starting simulation...
+info: Entering event queue @ 2311496944500. Starting simulation...
switching cpus
-info: Entering event queue @ 2311628440000. Starting simulation...
+info: Entering event queue @ 2311496968000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2312628440000. Starting simulation...
+info: Entering event queue @ 2312496968000. Starting simulation...
switching cpus
-info: Entering event queue @ 2312628571000. Starting simulation...
+info: Entering event queue @ 2312497014000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2313628571000. Starting simulation...
+info: Entering event queue @ 2313497014000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2314628571000. Starting simulation...
+info: Entering event queue @ 2314497014000. Starting simulation...
switching cpus
-info: Entering event queue @ 2314628586000. Starting simulation...
+info: Entering event queue @ 2314497034000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2315628586000. Starting simulation...
+info: Entering event queue @ 2315497034000. Starting simulation...
switching cpus
-info: Entering event queue @ 2315628609000. Starting simulation...
+info: Entering event queue @ 2315497085000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2316628609000. Starting simulation...
+info: Entering event queue @ 2316497085000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2317628609000. Starting simulation...
+info: Entering event queue @ 2317497085000. Starting simulation...
switching cpus
-info: Entering event queue @ 2317628760000. Starting simulation...
+info: Entering event queue @ 2317497141000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2318628760000. Starting simulation...
+info: Entering event queue @ 2318497141000. Starting simulation...
switching cpus
-info: Entering event queue @ 2318628871500. Starting simulation...
+info: Entering event queue @ 2318497292000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2319628871500. Starting simulation...
+info: Entering event queue @ 2319497292000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2320628871500. Starting simulation...
+info: Entering event queue @ 2320497292000. Starting simulation...
switching cpus
-info: Entering event queue @ 2320628950000. Starting simulation...
+info: Entering event queue @ 2320497349000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2321628950000. Starting simulation...
+info: Entering event queue @ 2321497349000. Starting simulation...
switching cpus
-info: Entering event queue @ 2321628957000. Starting simulation...
+info: Entering event queue @ 2321497426000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2322628957000. Starting simulation...
+info: Entering event queue @ 2322497426000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2323628957000. Starting simulation...
+info: Entering event queue @ 2323497426000. Starting simulation...
switching cpus
-info: Entering event queue @ 2323629079000. Starting simulation...
+info: Entering event queue @ 2323497512000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2324629079000. Starting simulation...
+info: Entering event queue @ 2324497512000. Starting simulation...
switching cpus
-info: Entering event queue @ 2324629126000. Starting simulation...
+info: Entering event queue @ 2324497588000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2325629126000. Starting simulation...
+info: Entering event queue @ 2325497588000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2326629126000. Starting simulation...
+info: Entering event queue @ 2326497588000. Starting simulation...
switching cpus
-info: Entering event queue @ 2326629176000. Starting simulation...
+info: Entering event queue @ 2326497667000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2327629176000. Starting simulation...
+info: Entering event queue @ 2327497667000. Starting simulation...
switching cpus
-info: Entering event queue @ 2327629301000. Starting simulation...
+info: Entering event queue @ 2327497830500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2328629301000. Starting simulation...
+info: Entering event queue @ 2328497830500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2329629301000. Starting simulation...
+info: Entering event queue @ 2329497830500. Starting simulation...
switching cpus
-info: Entering event queue @ 2329629399000. Starting simulation...
+info: Entering event queue @ 2329497980000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2330629399000. Starting simulation...
+info: Entering event queue @ 2330497980000. Starting simulation...
switching cpus
-info: Entering event queue @ 2330629558000. Starting simulation...
+info: Entering event queue @ 2330498019000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2331629558000. Starting simulation...
+info: Entering event queue @ 2331498019000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2332629558000. Starting simulation...
+info: Entering event queue @ 2332498019000. Starting simulation...
switching cpus
-info: Entering event queue @ 2332629573000. Starting simulation...
+info: Entering event queue @ 2332498021000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2333629573000. Starting simulation...
+info: Entering event queue @ 2333498021000. Starting simulation...
switching cpus
-info: Entering event queue @ 2333629640000. Starting simulation...
+info: Entering event queue @ 2333498144000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2334629640000. Starting simulation...
+info: Entering event queue @ 2334498144000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2335629640000. Starting simulation...
+info: Entering event queue @ 2335498144000. Starting simulation...
switching cpus
-info: Entering event queue @ 2335629779000. Starting simulation...
+info: Entering event queue @ 2335498177000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2336629779000. Starting simulation...
+info: Entering event queue @ 2336498177000. Starting simulation...
switching cpus
-info: Entering event queue @ 2336629888500. Starting simulation...
+info: Entering event queue @ 2336498207000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2337629888500. Starting simulation...
+info: Entering event queue @ 2337498207000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2338629888500. Starting simulation...
+info: Entering event queue @ 2338498207000. Starting simulation...
switching cpus
-info: Entering event queue @ 2338630042000. Starting simulation...
+info: Entering event queue @ 2338498322500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2339630042000. Starting simulation...
+info: Entering event queue @ 2339498322500. Starting simulation...
switching cpus
-info: Entering event queue @ 2339630075000. Starting simulation...
+info: Entering event queue @ 2339498342500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2340630075000. Starting simulation...
+info: Entering event queue @ 2340498342500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2341630075000. Starting simulation...
+info: Entering event queue @ 2341498342500. Starting simulation...
switching cpus
-info: Entering event queue @ 2341630098000. Starting simulation...
+info: Entering event queue @ 2341498465000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2342630098000. Starting simulation...
+info: Entering event queue @ 2342498465000. Starting simulation...
switching cpus
-info: Entering event queue @ 2342630224500. Starting simulation...
+info: Entering event queue @ 2342498545000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2343630224500. Starting simulation...
+info: Entering event queue @ 2343498545000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2344630224500. Starting simulation...
+info: Entering event queue @ 2344498545000. Starting simulation...
switching cpus
-info: Entering event queue @ 2344630308000. Starting simulation...
+info: Entering event queue @ 2344498670000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2345630308000. Starting simulation...
+info: Entering event queue @ 2345498670000. Starting simulation...
switching cpus
-info: Entering event queue @ 2345630440000. Starting simulation...
+info: Entering event queue @ 2345498729000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2346630440000. Starting simulation...
+info: Entering event queue @ 2346498729000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2347630440000. Starting simulation...
+info: Entering event queue @ 2347498729000. Starting simulation...
switching cpus
-info: Entering event queue @ 2347630481000. Starting simulation...
+info: Entering event queue @ 2347498836000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2348630481000. Starting simulation...
+info: Entering event queue @ 2348498836000. Starting simulation...
switching cpus
-info: Entering event queue @ 2348630538000. Starting simulation...
+info: Entering event queue @ 2348498903500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2349630538000. Starting simulation...
+info: Entering event queue @ 2349498903500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2350630538000. Starting simulation...
+info: Entering event queue @ 2350498903500. Starting simulation...
switching cpus
-info: Entering event queue @ 2350630623000. Starting simulation...
+info: Entering event queue @ 2350499004000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2351630623000. Starting simulation...
+info: Entering event queue @ 2351499004000. Starting simulation...
switching cpus
-info: Entering event queue @ 2351630640000. Starting simulation...
+info: Entering event queue @ 2351499092000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2352630640000. Starting simulation...
+info: Entering event queue @ 2352499092000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2353630640000. Starting simulation...
+info: Entering event queue @ 2353499092000. Starting simulation...
switching cpus
-info: Entering event queue @ 2353630748000. Starting simulation...
+info: Entering event queue @ 2353499228000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2354630748000. Starting simulation...
+info: Entering event queue @ 2354499228000. Starting simulation...
switching cpus
-info: Entering event queue @ 2354630878000. Starting simulation...
+info: Entering event queue @ 2354499241000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2355630878000. Starting simulation...
+info: Entering event queue @ 2355499241000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2356630878000. Starting simulation...
+info: Entering event queue @ 2356499241000. Starting simulation...
switching cpus
-info: Entering event queue @ 2356630895000. Starting simulation...
+info: Entering event queue @ 2356499328000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2357630895000. Starting simulation...
+info: Entering event queue @ 2357499328000. Starting simulation...
switching cpus
-info: Entering event queue @ 2357630943000. Starting simulation...
+info: Entering event queue @ 2357499348000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2358630943000. Starting simulation...
+info: Entering event queue @ 2358499348000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2359630943000. Starting simulation...
+info: Entering event queue @ 2359499348000. Starting simulation...
switching cpus
-info: Entering event queue @ 2359630963000. Starting simulation...
+info: Entering event queue @ 2359499378000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2360630963000. Starting simulation...
-info: Entering event queue @ 2362100305000. Starting simulation...
+info: Entering event queue @ 2360499378000. Starting simulation...
+info: Entering event queue @ 2361968926000. Starting simulation...
switching cpus
-info: Entering event queue @ 2362100307000. Starting simulation...
+info: Entering event queue @ 2361968928000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2363100307000. Starting simulation...
+info: Entering event queue @ 2362968928000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2364100307000. Starting simulation...
+info: Entering event queue @ 2363968928000. Starting simulation...
switching cpus
-info: Entering event queue @ 2364100364000. Starting simulation...
+info: Entering event queue @ 2363969050000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2365100364000. Starting simulation...
+info: Entering event queue @ 2364969050000. Starting simulation...
switching cpus
-info: Entering event queue @ 2365100522000. Starting simulation...
+info: Entering event queue @ 2364969072000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2366100522000. Starting simulation...
+info: Entering event queue @ 2365969072000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2367100522000. Starting simulation...
-info: Entering event queue @ 2367100525000. Starting simulation...
+info: Entering event queue @ 2366969072000. Starting simulation...
switching cpus
-info: Entering event queue @ 2367100527500. Starting simulation...
+info: Entering event queue @ 2366969074000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2368100527500. Starting simulation...
+info: Entering event queue @ 2367969074000. Starting simulation...
switching cpus
-info: Entering event queue @ 2368100529500. Starting simulation...
+info: Entering event queue @ 2367969092500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2369100529500. Starting simulation...
+info: Entering event queue @ 2368969092500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2370100529500. Starting simulation...
+info: Entering event queue @ 2369969092500. Starting simulation...
switching cpus
-info: Entering event queue @ 2370100533000. Starting simulation...
+info: Entering event queue @ 2369969184000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2371100533000. Starting simulation...
+info: Entering event queue @ 2370969184000. Starting simulation...
switching cpus
-info: Entering event queue @ 2371100682500. Starting simulation...
+info: Entering event queue @ 2370969281000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2372100682500. Starting simulation...
+info: Entering event queue @ 2371969281000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2373100682500. Starting simulation...
+info: Entering event queue @ 2372969281000. Starting simulation...
switching cpus
-info: Entering event queue @ 2373100683500. Starting simulation...
+info: Entering event queue @ 2372969283000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2374100683500. Starting simulation...
+info: Entering event queue @ 2373969283000. Starting simulation...
switching cpus
-info: Entering event queue @ 2374102804500. Starting simulation...
+info: Entering event queue @ 2373969828500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2375102804500. Starting simulation...
+info: Entering event queue @ 2374969828500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2376102804500. Starting simulation...
+info: Entering event queue @ 2375969828500. Starting simulation...
switching cpus
-info: Entering event queue @ 2376102808000. Starting simulation...
+info: Entering event queue @ 2375969851000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2377102808000. Starting simulation...
+info: Entering event queue @ 2376969851000. Starting simulation...
switching cpus
-info: Entering event queue @ 2377102891000. Starting simulation...
+info: Entering event queue @ 2376969901000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2378102891000. Starting simulation...
+info: Entering event queue @ 2377969901000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2379102891000. Starting simulation...
+info: Entering event queue @ 2378969901000. Starting simulation...
switching cpus
-info: Entering event queue @ 2379102993000. Starting simulation...
+info: Entering event queue @ 2378969954000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2380102993000. Starting simulation...
+info: Entering event queue @ 2379969954000. Starting simulation...
switching cpus
-info: Entering event queue @ 2380103021000. Starting simulation...
+info: Entering event queue @ 2379970086500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2381103021000. Starting simulation...
+info: Entering event queue @ 2380970086500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2382103021000. Starting simulation...
+info: Entering event queue @ 2381970086500. Starting simulation...
switching cpus
-info: Entering event queue @ 2382103048000. Starting simulation...
+info: Entering event queue @ 2381970242000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2383103048000. Starting simulation...
+info: Entering event queue @ 2382970242000. Starting simulation...
switching cpus
-info: Entering event queue @ 2383112179000. Starting simulation...
+info: Entering event queue @ 2382978620000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2384112179000. Starting simulation...
+info: Entering event queue @ 2383978620000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2385112179000. Starting simulation...
+info: Entering event queue @ 2384978620000. Starting simulation...
switching cpus
-info: Entering event queue @ 2385112305000. Starting simulation...
+info: Entering event queue @ 2384978773000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2386112305000. Starting simulation...
+info: Entering event queue @ 2385978773000. Starting simulation...
switching cpus
-info: Entering event queue @ 2386112310500. Starting simulation...
+info: Entering event queue @ 2385978776000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2387112310500. Starting simulation...
switching cpus
-info: Entering event queue @ 2387112312500. Starting simulation...
+info: Entering event queue @ 2386978776000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2388112312500. Starting simulation...
+info: Entering event queue @ 2387978776000. Starting simulation...
switching cpus
-info: Entering event queue @ 2388112314500. Starting simulation...
+info: Entering event queue @ 2387978777500. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2389112314500. Starting simulation...
+info: Entering event queue @ 2388978777500. Starting simulation...
switching cpus
-info: Entering event queue @ 2389112333500. Starting simulation...
+info: Entering event queue @ 2388978785000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2390112333500. Starting simulation...
+info: Entering event queue @ 2389978785000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2391112333500. Starting simulation...
+info: Entering event queue @ 2390978785000. Starting simulation...
switching cpus
-info: Entering event queue @ 2391112334500. Starting simulation...
+info: Entering event queue @ 2390978786000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2392112334500. Starting simulation...
+info: Entering event queue @ 2391978786000. Starting simulation...
+info: Entering event queue @ 2391978831000. Starting simulation...
+info: Entering event queue @ 2391978840500. Starting simulation...
+info: Entering event queue @ 2391978845000. Starting simulation...
switching cpus
-info: Entering event queue @ 2392112630500. Starting simulation...
+info: Entering event queue @ 2391978846000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2393112630500. Starting simulation...
switching cpus
-info: Entering event queue @ 2393112631000. Starting simulation...
+info: Entering event queue @ 2392978846000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2394112631000. Starting simulation...
-info: Entering event queue @ 2394836596000. Starting simulation...
+info: Entering event queue @ 2393978846000. Starting simulation...
+info: Entering event queue @ 2394705526000. Starting simulation...
switching cpus
-info: Entering event queue @ 2394836598000. Starting simulation...
+info: Entering event queue @ 2394705528000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2395836598000. Starting simulation...
+info: Entering event queue @ 2395705528000. Starting simulation...
switching cpus
-info: Entering event queue @ 2395839042500. Starting simulation...
+info: Entering event queue @ 2395708224000. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
switching cpus
-info: Entering event queue @ 2396839042500. Starting simulation...
+info: Entering event queue @ 2396708224000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2397839042500. Starting simulation...
+info: Entering event queue @ 2397708224000. Starting simulation...
switching cpus
-info: Entering event queue @ 2397839043500. Starting simulation...
+info: Entering event queue @ 2397708236000. Starting simulation...
Switching CPUs...
Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2398839043500. Starting simulation...
+info: Entering event queue @ 2398708236000. Starting simulation...
switching cpus
-info: Entering event queue @ 2398839190000. Starting simulation...
+info: Entering event queue @ 2398708269500. Starting simulation...
Switching CPUs...
Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2399839190000. Starting simulation...
switching cpus
-info: Entering event queue @ 2399839190500. Starting simulation...
+info: Entering event queue @ 2399708269500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2400839190500. Starting simulation...
-info: Entering event queue @ 2400839197500. Starting simulation...
+info: Entering event queue @ 2400708269500. Starting simulation...
switching cpus
-info: Entering event queue @ 2400839201000. Starting simulation...
+info: Entering event queue @ 2400708271500. Starting simulation...
sim_ticks 2401290348000 # Number of ticks simulated
final_tick 2401290348000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 196762 # Simulator instruction rate (inst/s)
-host_op_rate 252717 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 7831753482 # Simulator tick rate (ticks/s)
-host_mem_usage 401668 # Number of bytes of host memory used
-host_seconds 306.61 # Real time elapsed on the host
+host_inst_rate 145439 # Simulator instruction rate (inst/s)
+host_op_rate 186799 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5788935854 # Simulator tick rate (ticks/s)
+host_mem_usage 444568 # Number of bytes of host memory used
+host_seconds 414.81 # Real time elapsed on the host
sim_insts 60329082 # Number of instructions simulated
sim_ops 77485321 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
system.cpu1.idle_fraction -0.049701 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.cpu2.branchPred.lookups 4714679 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 3830081 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 228509 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 3129435 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 2502665 # Number of BTB hits
+system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu2.branchPred.BTBHitPct 79.971784 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 416919 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 22256 # Number of incorrect RAS predictions.
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
system.cpu2.dtb.read_hits 11094758 # DTB read hits
system.cpu2.numCycles 88220053 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.BPredUnit.lookups 4714679 # Number of BP lookups
-system.cpu2.BPredUnit.condPredicted 3830081 # Number of conditional branches predicted
-system.cpu2.BPredUnit.condIncorrect 228509 # Number of conditional branches incorrect
-system.cpu2.BPredUnit.BTBLookups 3129435 # Number of BTB lookups
-system.cpu2.BPredUnit.BTBHits 2502665 # Number of BTB hits
-system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.BPredUnit.usedRAS 416919 # Number of times the RAS was used to get a target.
-system.cpu2.BPredUnit.RASInCorrect 22256 # Number of incorrect RAS predictions.
system.cpu2.fetch.icacheStallCycles 9444272 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 32171210 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 4714679 # Number of branches that fetch encountered
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/gem5/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu0.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu0.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu0.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
+[system.cpu0.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu0.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
[system.cpu1]
type=DerivO3CPU
-children=dtb fuPool interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dtb fuPool interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu1.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu1.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu1.interrupts
isa=system.cpu1.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu1.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
wbWidth=8
workload=
+[system.cpu1.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu1.dtb]
type=ArmTLB
children=walker
warn: LCD dual screen mode not supported
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 5 2013 02:15:48
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 22:10:12
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
info: Entering event queue @ 4000031000. Starting simulation...
switching cpus
-info: Entering event queue @ 4000036000. Starting simulation...
+info: Entering event queue @ 4000247000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 5000036000. Starting simulation...
+info: Entering event queue @ 5000247000. Starting simulation...
switching cpus
-info: Entering event queue @ 5000042500. Starting simulation...
+info: Entering event queue @ 5000410000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 6000042500. Starting simulation...
+info: Entering event queue @ 6000410000. Starting simulation...
+info: Entering event queue @ 6000457500. Starting simulation...
+info: Entering event queue @ 6000493000. Starting simulation...
switching cpus
-info: Entering event queue @ 6000066500. Starting simulation...
+info: Entering event queue @ 6000497500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 7000066500. Starting simulation...
+info: Entering event queue @ 7000497500. Starting simulation...
+info: Entering event queue @ 7000507000. Starting simulation...
switching cpus
-info: Entering event queue @ 7000292500. Starting simulation...
+info: Entering event queue @ 7000511500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 8000292500. Starting simulation...
+info: Entering event queue @ 8000511500. Starting simulation...
switching cpus
-info: Entering event queue @ 8000305000. Starting simulation...
+info: Entering event queue @ 8000635000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 9000305000. Starting simulation...
-info: Entering event queue @ 9000308500. Starting simulation...
+info: Entering event queue @ 9000635000. Starting simulation...
switching cpus
-info: Entering event queue @ 9000313000. Starting simulation...
+info: Entering event queue @ 9000641000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 10000313000. Starting simulation...
-info: Entering event queue @ 10000329500. Starting simulation...
-info: Entering event queue @ 10000335000. Starting simulation...
+info: Entering event queue @ 10000641000. Starting simulation...
switching cpus
-info: Entering event queue @ 10000339500. Starting simulation...
+info: Entering event queue @ 10000646500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 11000339500. Starting simulation...
-info: Entering event queue @ 11000385500. Starting simulation...
-info: Entering event queue @ 11000485000. Starting simulation...
+info: Entering event queue @ 11000646500. Starting simulation...
switching cpus
-info: Entering event queue @ 11000489500. Starting simulation...
+info: Entering event queue @ 11000922500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 12000489500. Starting simulation...
+info: Entering event queue @ 12000922500. Starting simulation...
+info: Entering event queue @ 12000932500. Starting simulation...
switching cpus
-info: Entering event queue @ 12000495500. Starting simulation...
+info: Entering event queue @ 12000937000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 13000495500. Starting simulation...
-info: Entering event queue @ 13000512500. Starting simulation...
-info: Entering event queue @ 13000518500. Starting simulation...
+info: Entering event queue @ 13000937000. Starting simulation...
+info: Entering event queue @ 13000946500. Starting simulation...
switching cpus
-info: Entering event queue @ 13000523000. Starting simulation...
+info: Entering event queue @ 13000951000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 14000523000. Starting simulation...
+info: Entering event queue @ 14000951000. Starting simulation...
switching cpus
-info: Entering event queue @ 14000526000. Starting simulation...
+info: Entering event queue @ 14000960000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 15000526000. Starting simulation...
+info: Entering event queue @ 15000960000. Starting simulation...
+info: Entering event queue @ 15000966000. Starting simulation...
switching cpus
-info: Entering event queue @ 15000544500. Starting simulation...
+info: Entering event queue @ 15000970500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 16000544500. Starting simulation...
-info: Entering event queue @ 16000649000. Starting simulation...
+info: Entering event queue @ 16000970500. Starting simulation...
switching cpus
-info: Entering event queue @ 16000650000. Starting simulation...
+info: Entering event queue @ 16001125000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 17000650000. Starting simulation...
+info: Entering event queue @ 17001125000. Starting simulation...
switching cpus
-info: Entering event queue @ 17000658500. Starting simulation...
+info: Entering event queue @ 25966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 18000658500. Starting simulation...
+info: Entering event queue @ 26966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 26268191000. Starting simulation...
+info: Entering event queue @ 35966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 27268191000. Starting simulation...
+info: Entering event queue @ 36966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 36268191000. Starting simulation...
+info: Entering event queue @ 45966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 37268191000. Starting simulation...
+info: Entering event queue @ 46966288000. Starting simulation...
+info: Entering event queue @ 48430354000. Starting simulation...
switching cpus
-info: Entering event queue @ 46268191000. Starting simulation...
+info: Entering event queue @ 48430356000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 47268191000. Starting simulation...
-info: Entering event queue @ 48732715000. Starting simulation...
+info: Entering event queue @ 49430356000. Starting simulation...
switching cpus
-info: Entering event queue @ 48732717000. Starting simulation...
+info: Entering event queue @ 49430481500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 49732717000. Starting simulation...
+info: Entering event queue @ 50430481500. Starting simulation...
switching cpus
-info: Entering event queue @ 49732757500. Starting simulation...
+info: Entering event queue @ 50430618000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 50732757500. Starting simulation...
+info: Entering event queue @ 51430618000. Starting simulation...
switching cpus
-info: Entering event queue @ 50732909500. Starting simulation...
+info: Entering event queue @ 51430627000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 51732909500. Starting simulation...
+info: Entering event queue @ 52430627000. Starting simulation...
+info: Entering event queue @ 52430630500. Starting simulation...
switching cpus
-info: Entering event queue @ 51732927500. Starting simulation...
+info: Entering event queue @ 52430635000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 52732927500. Starting simulation...
+info: Entering event queue @ 53430635000. Starting simulation...
switching cpus
-info: Entering event queue @ 52732945000. Starting simulation...
+info: Entering event queue @ 53430641000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 53732945000. Starting simulation...
-info: Entering event queue @ 53732954000. Starting simulation...
-info: Entering event queue @ 53732958500. Starting simulation...
+info: Entering event queue @ 54430641000. Starting simulation...
+info: Entering event queue @ 54430651500. Starting simulation...
switching cpus
-info: Entering event queue @ 53732963000. Starting simulation...
+info: Entering event queue @ 54430656000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 54732963000. Starting simulation...
-info: Entering event queue @ 54732970000. Starting simulation...
-info: Entering event queue @ 54732980500. Starting simulation...
-info: Entering event queue @ 54732985000. Starting simulation...
+info: Entering event queue @ 55430656000. Starting simulation...
+info: Entering event queue @ 55430664500. Starting simulation...
switching cpus
-info: Entering event queue @ 54732986000. Starting simulation...
+info: Entering event queue @ 55430669000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 55732986000. Starting simulation...
-info: Entering event queue @ 55732994000. Starting simulation...
+info: Entering event queue @ 56430669000. Starting simulation...
switching cpus
-info: Entering event queue @ 55732998500. Starting simulation...
+info: Entering event queue @ 56430965500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 56732998500. Starting simulation...
-info: Entering event queue @ 56733008500. Starting simulation...
+info: Entering event queue @ 57430965500. Starting simulation...
switching cpus
-info: Entering event queue @ 56733013000. Starting simulation...
+info: Entering event queue @ 65966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 57733013000. Starting simulation...
+info: Entering event queue @ 66966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 66268191000. Starting simulation...
+info: Entering event queue @ 75966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 67268191000. Starting simulation...
+info: Entering event queue @ 76966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 76268191000. Starting simulation...
+info: Entering event queue @ 85966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 77268191000. Starting simulation...
+info: Entering event queue @ 86966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 86268191000. Starting simulation...
+info: Entering event queue @ 95966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 87268191000. Starting simulation...
+info: Entering event queue @ 96966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 96268191000. Starting simulation...
+info: Entering event queue @ 105966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 97268191000. Starting simulation...
+info: Entering event queue @ 106966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 106268191000. Starting simulation...
+info: Entering event queue @ 115966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 107268191000. Starting simulation...
+info: Entering event queue @ 116966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 116268191000. Starting simulation...
+info: Entering event queue @ 125966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 117268191000. Starting simulation...
+info: Entering event queue @ 126966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 126268191000. Starting simulation...
+info: Entering event queue @ 135966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 127268191000. Starting simulation...
+info: Entering event queue @ 136966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 136268191000. Starting simulation...
+info: Entering event queue @ 145966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 137268191000. Starting simulation...
+info: Entering event queue @ 146966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 146268191000. Starting simulation...
+info: Entering event queue @ 155966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 147268191000. Starting simulation...
+info: Entering event queue @ 156966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 156268191000. Starting simulation...
+info: Entering event queue @ 165966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 157268191000. Starting simulation...
+info: Entering event queue @ 166966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 166268191000. Starting simulation...
+info: Entering event queue @ 175966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 167268191000. Starting simulation...
+info: Entering event queue @ 176966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 176268191000. Starting simulation...
+info: Entering event queue @ 185966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 177268191000. Starting simulation...
+info: Entering event queue @ 186966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 186268191000. Starting simulation...
+info: Entering event queue @ 195966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 187268191000. Starting simulation...
+info: Entering event queue @ 196966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 196268191000. Starting simulation...
+info: Entering event queue @ 205966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 197268191000. Starting simulation...
+info: Entering event queue @ 206966288000. Starting simulation...
+info: Entering event queue @ 206966298000. Starting simulation...
+info: Entering event queue @ 206966304500. Starting simulation...
switching cpus
-info: Entering event queue @ 206268191000. Starting simulation...
+info: Entering event queue @ 206966309000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 207268191000. Starting simulation...
+info: Entering event queue @ 207966309000. Starting simulation...
switching cpus
-info: Entering event queue @ 207268194000. Starting simulation...
+info: Entering event queue @ 215966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 208268194000. Starting simulation...
+info: Entering event queue @ 216966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 216268191000. Starting simulation...
+info: Entering event queue @ 225966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 217268191000. Starting simulation...
+info: Entering event queue @ 226966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 226268191000. Starting simulation...
+info: Entering event queue @ 235966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 227268191000. Starting simulation...
+info: Entering event queue @ 236966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 236268191000. Starting simulation...
+info: Entering event queue @ 245966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 237268191000. Starting simulation...
+info: Entering event queue @ 246966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 246268191000. Starting simulation...
+info: Entering event queue @ 255966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 247268191000. Starting simulation...
+info: Entering event queue @ 256966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 256268191000. Starting simulation...
+info: Entering event queue @ 265966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 257268191000. Starting simulation...
+info: Entering event queue @ 266966288000. Starting simulation...
+info: Entering event queue @ 275966288000. Starting simulation...
+info: Entering event queue @ 276772747000. Starting simulation...
switching cpus
-info: Entering event queue @ 266268191000. Starting simulation...
+info: Entering event queue @ 276772749000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 267268191000. Starting simulation...
-info: Entering event queue @ 276268191000. Starting simulation...
-info: Entering event queue @ 277074505000. Starting simulation...
+info: Entering event queue @ 277772749000. Starting simulation...
switching cpus
-info: Entering event queue @ 277074507000. Starting simulation...
+info: Entering event queue @ 285966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 278074507000. Starting simulation...
+info: Entering event queue @ 286966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 286268191000. Starting simulation...
+info: Entering event queue @ 295966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 287268191000. Starting simulation...
+info: Entering event queue @ 296966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 296268191000. Starting simulation...
+info: Entering event queue @ 305966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 297268191000. Starting simulation...
+info: Entering event queue @ 306966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 306268191000. Starting simulation...
+info: Entering event queue @ 315966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 307268191000. Starting simulation...
+info: Entering event queue @ 316966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 316268191000. Starting simulation...
+info: Entering event queue @ 325966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 317268191000. Starting simulation...
+info: Entering event queue @ 326966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 326268191000. Starting simulation...
+info: Entering event queue @ 335966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 327268191000. Starting simulation...
+info: Entering event queue @ 336966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 336268191000. Starting simulation...
+info: Entering event queue @ 345966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 337268191000. Starting simulation...
+info: Entering event queue @ 346966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 346268191000. Starting simulation...
+info: Entering event queue @ 355966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 347268191000. Starting simulation...
+info: Entering event queue @ 356966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 356268191000. Starting simulation...
+info: Entering event queue @ 365966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 357268191000. Starting simulation...
+info: Entering event queue @ 366966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 366268191000. Starting simulation...
+info: Entering event queue @ 375966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 367268191000. Starting simulation...
+info: Entering event queue @ 376966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 376268191000. Starting simulation...
+info: Entering event queue @ 385966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 377268191000. Starting simulation...
+info: Entering event queue @ 386966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 386268191000. Starting simulation...
+info: Entering event queue @ 395966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 387268191000. Starting simulation...
+info: Entering event queue @ 396966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 396268191000. Starting simulation...
+info: Entering event queue @ 405966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 397268191000. Starting simulation...
+info: Entering event queue @ 406966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 406268191000. Starting simulation...
+info: Entering event queue @ 415966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 407268191000. Starting simulation...
+info: Entering event queue @ 416966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 416268191000. Starting simulation...
+info: Entering event queue @ 425966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 417268191000. Starting simulation...
+info: Entering event queue @ 426966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 426268191000. Starting simulation...
+info: Entering event queue @ 435966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 427268191000. Starting simulation...
+info: Entering event queue @ 436966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 436268191000. Starting simulation...
+info: Entering event queue @ 445966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 437268191000. Starting simulation...
+info: Entering event queue @ 446966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 446268191000. Starting simulation...
+info: Entering event queue @ 455966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 447268191000. Starting simulation...
+info: Entering event queue @ 456966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 456268191000. Starting simulation...
+info: Entering event queue @ 465966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 457268191000. Starting simulation...
+info: Entering event queue @ 466966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 466268191000. Starting simulation...
+info: Entering event queue @ 475966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 467268191000. Starting simulation...
+info: Entering event queue @ 476966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 476268191000. Starting simulation...
+info: Entering event queue @ 485966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 477268191000. Starting simulation...
+info: Entering event queue @ 486966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 486268191000. Starting simulation...
+info: Entering event queue @ 495966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 487268191000. Starting simulation...
+info: Entering event queue @ 496966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 496268191000. Starting simulation...
+info: Entering event queue @ 505966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 497268191000. Starting simulation...
+info: Entering event queue @ 506966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 506268191000. Starting simulation...
+info: Entering event queue @ 515966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 507268191000. Starting simulation...
+info: Entering event queue @ 516966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 516268191000. Starting simulation...
+info: Entering event queue @ 525966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 517268191000. Starting simulation...
+info: Entering event queue @ 526966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 526268191000. Starting simulation...
+info: Entering event queue @ 535966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 527268191000. Starting simulation...
+info: Entering event queue @ 536966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 536268191000. Starting simulation...
+info: Entering event queue @ 545966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 537268191000. Starting simulation...
+info: Entering event queue @ 546966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 546268191000. Starting simulation...
+info: Entering event queue @ 555966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 547268191000. Starting simulation...
+info: Entering event queue @ 556966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 556268191000. Starting simulation...
+info: Entering event queue @ 565966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 557268191000. Starting simulation...
+info: Entering event queue @ 566966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 566268191000. Starting simulation...
+info: Entering event queue @ 575966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 567268191000. Starting simulation...
+info: Entering event queue @ 576966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 576268191000. Starting simulation...
+info: Entering event queue @ 585966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 577268191000. Starting simulation...
+info: Entering event queue @ 586966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 586268191000. Starting simulation...
+info: Entering event queue @ 595966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 587268191000. Starting simulation...
+info: Entering event queue @ 596966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 596268191000. Starting simulation...
+info: Entering event queue @ 605966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 597268191000. Starting simulation...
+info: Entering event queue @ 606966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 606268191000. Starting simulation...
+info: Entering event queue @ 615966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 607268191000. Starting simulation...
+info: Entering event queue @ 616966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 616268191000. Starting simulation...
+info: Entering event queue @ 625966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 617268191000. Starting simulation...
+info: Entering event queue @ 626966288000. Starting simulation...
+info: Entering event queue @ 635966288000. Starting simulation...
+info: Entering event queue @ 636871372000. Starting simulation...
switching cpus
-info: Entering event queue @ 626268191000. Starting simulation...
+info: Entering event queue @ 636871374000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 627268191000. Starting simulation...
-info: Entering event queue @ 636268191000. Starting simulation...
-info: Entering event queue @ 637173280000. Starting simulation...
+info: Entering event queue @ 637871374000. Starting simulation...
switching cpus
-info: Entering event queue @ 637173282000. Starting simulation...
+info: Entering event queue @ 645966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 638173282000. Starting simulation...
+info: Entering event queue @ 646966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 646268191000. Starting simulation...
+info: Entering event queue @ 655966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 647268191000. Starting simulation...
+info: Entering event queue @ 656966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 656268191000. Starting simulation...
+info: Entering event queue @ 665966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 657268191000. Starting simulation...
+info: Entering event queue @ 666966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 666268191000. Starting simulation...
+info: Entering event queue @ 675966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 667268191000. Starting simulation...
+info: Entering event queue @ 676966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 676268191000. Starting simulation...
+info: Entering event queue @ 685966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 677268191000. Starting simulation...
+info: Entering event queue @ 686966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 686268191000. Starting simulation...
+info: Entering event queue @ 695966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 687268191000. Starting simulation...
+info: Entering event queue @ 696966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 696268191000. Starting simulation...
+info: Entering event queue @ 705966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 697268191000. Starting simulation...
+info: Entering event queue @ 706966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 706268191000. Starting simulation...
+info: Entering event queue @ 715966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 707268191000. Starting simulation...
+info: Entering event queue @ 716966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 716268191000. Starting simulation...
+info: Entering event queue @ 725966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 717268191000. Starting simulation...
+info: Entering event queue @ 726966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 726268191000. Starting simulation...
+info: Entering event queue @ 735966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 727268191000. Starting simulation...
+info: Entering event queue @ 736966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 736268191000. Starting simulation...
+info: Entering event queue @ 745966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 737268191000. Starting simulation...
+info: Entering event queue @ 746966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 746268191000. Starting simulation...
+info: Entering event queue @ 755966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 747268191000. Starting simulation...
+info: Entering event queue @ 756966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 756268191000. Starting simulation...
+info: Entering event queue @ 765966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 757268191000. Starting simulation...
+info: Entering event queue @ 766966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 766268191000. Starting simulation...
+info: Entering event queue @ 775966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 767268191000. Starting simulation...
+info: Entering event queue @ 776966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 776268191000. Starting simulation...
+info: Entering event queue @ 785966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 777268191000. Starting simulation...
+info: Entering event queue @ 786966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 786268191000. Starting simulation...
+info: Entering event queue @ 795966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 787268191000. Starting simulation...
+info: Entering event queue @ 796966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 796268191000. Starting simulation...
+info: Entering event queue @ 805966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 797268191000. Starting simulation...
+info: Entering event queue @ 806966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 806268191000. Starting simulation...
+info: Entering event queue @ 815966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 807268191000. Starting simulation...
+info: Entering event queue @ 816966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 816268191000. Starting simulation...
+info: Entering event queue @ 825966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 817268191000. Starting simulation...
+info: Entering event queue @ 826966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 826268191000. Starting simulation...
+info: Entering event queue @ 835966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 827268191000. Starting simulation...
+info: Entering event queue @ 836966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 836268191000. Starting simulation...
+info: Entering event queue @ 845966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 837268191000. Starting simulation...
+info: Entering event queue @ 846966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 846268191000. Starting simulation...
+info: Entering event queue @ 855966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 847268191000. Starting simulation...
+info: Entering event queue @ 856966288000. Starting simulation...
+info: Entering event queue @ 865966288000. Starting simulation...
+info: Entering event queue @ 866025280000. Starting simulation...
switching cpus
-info: Entering event queue @ 856268191000. Starting simulation...
+info: Entering event queue @ 866025282000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 857268191000. Starting simulation...
-info: Entering event queue @ 866268191000. Starting simulation...
-info: Entering event queue @ 866327182000. Starting simulation...
+info: Entering event queue @ 867025282000. Starting simulation...
switching cpus
-info: Entering event queue @ 866327184000. Starting simulation...
+info: Entering event queue @ 875966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 867327184000. Starting simulation...
+info: Entering event queue @ 876966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 876268191000. Starting simulation...
+info: Entering event queue @ 885966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 877268191000. Starting simulation...
+info: Entering event queue @ 886966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 886268191000. Starting simulation...
+info: Entering event queue @ 895966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 887268191000. Starting simulation...
+info: Entering event queue @ 896966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 896268191000. Starting simulation...
+info: Entering event queue @ 905966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 897268191000. Starting simulation...
+info: Entering event queue @ 906966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 906268191000. Starting simulation...
+info: Entering event queue @ 915966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 907268191000. Starting simulation...
+info: Entering event queue @ 916966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 916268191000. Starting simulation...
+info: Entering event queue @ 925966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 917268191000. Starting simulation...
+info: Entering event queue @ 926966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 926268191000. Starting simulation...
+info: Entering event queue @ 935966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 927268191000. Starting simulation...
+info: Entering event queue @ 936966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 936268191000. Starting simulation...
+info: Entering event queue @ 945966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 937268191000. Starting simulation...
+info: Entering event queue @ 946966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 946268191000. Starting simulation...
+info: Entering event queue @ 955966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 947268191000. Starting simulation...
+info: Entering event queue @ 956966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 956268191000. Starting simulation...
+info: Entering event queue @ 965966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 957268191000. Starting simulation...
+info: Entering event queue @ 966966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 966268191000. Starting simulation...
+info: Entering event queue @ 975966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 967268191000. Starting simulation...
+info: Entering event queue @ 976966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 976268191000. Starting simulation...
+info: Entering event queue @ 985966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 977268191000. Starting simulation...
+info: Entering event queue @ 986966288000. Starting simulation...
+info: Entering event queue @ 995966288000. Starting simulation...
+info: Entering event queue @ 996970147000. Starting simulation...
switching cpus
-info: Entering event queue @ 986268191000. Starting simulation...
+info: Entering event queue @ 996970149000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 987268191000. Starting simulation...
-info: Entering event queue @ 996268191000. Starting simulation...
-info: Entering event queue @ 997271905000. Starting simulation...
+info: Entering event queue @ 997970149000. Starting simulation...
switching cpus
-info: Entering event queue @ 997271907000. Starting simulation...
+info: Entering event queue @ 1005966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 998271907000. Starting simulation...
+info: Entering event queue @ 1006966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1006268191000. Starting simulation...
+info: Entering event queue @ 1015966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1007268191000. Starting simulation...
+info: Entering event queue @ 1016966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1016268191000. Starting simulation...
+info: Entering event queue @ 1025966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1017268191000. Starting simulation...
+info: Entering event queue @ 1026966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1026268191000. Starting simulation...
+info: Entering event queue @ 1035966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1027268191000. Starting simulation...
+info: Entering event queue @ 1036966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1036268191000. Starting simulation...
+info: Entering event queue @ 1045966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1037268191000. Starting simulation...
+info: Entering event queue @ 1046966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1046268191000. Starting simulation...
+info: Entering event queue @ 1055966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1047268191000. Starting simulation...
+info: Entering event queue @ 1056966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1056268191000. Starting simulation...
+info: Entering event queue @ 1065966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1057268191000. Starting simulation...
+info: Entering event queue @ 1066966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1066268191000. Starting simulation...
+info: Entering event queue @ 1075966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1067268191000. Starting simulation...
+info: Entering event queue @ 1076966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1076268191000. Starting simulation...
+info: Entering event queue @ 1085966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1077268191000. Starting simulation...
+info: Entering event queue @ 1086966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1086268191000. Starting simulation...
+info: Entering event queue @ 1095966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1087268191000. Starting simulation...
+info: Entering event queue @ 1096966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1096268191000. Starting simulation...
+info: Entering event queue @ 1105966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1097268191000. Starting simulation...
+info: Entering event queue @ 1106966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1106268191000. Starting simulation...
+info: Entering event queue @ 1115966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1107268191000. Starting simulation...
+info: Entering event queue @ 1116966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1116268191000. Starting simulation...
+info: Entering event queue @ 1125966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1117268191000. Starting simulation...
+info: Entering event queue @ 1126966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1126268191000. Starting simulation...
+info: Entering event queue @ 1135966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1127268191000. Starting simulation...
+info: Entering event queue @ 1136966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1136268191000. Starting simulation...
+info: Entering event queue @ 1145966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1137268191000. Starting simulation...
+info: Entering event queue @ 1146966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1146268191000. Starting simulation...
+info: Entering event queue @ 1155966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1147268191000. Starting simulation...
+info: Entering event queue @ 1156966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1156268191000. Starting simulation...
+info: Entering event queue @ 1165966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1157268191000. Starting simulation...
+info: Entering event queue @ 1166966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1166268191000. Starting simulation...
+info: Entering event queue @ 1175966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1167268191000. Starting simulation...
+info: Entering event queue @ 1176966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1176268191000. Starting simulation...
+info: Entering event queue @ 1185966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1177268191000. Starting simulation...
+info: Entering event queue @ 1186966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1186268191000. Starting simulation...
+info: Entering event queue @ 1195966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1187268191000. Starting simulation...
+info: Entering event queue @ 1196966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1196268191000. Starting simulation...
+info: Entering event queue @ 1205966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1197268191000. Starting simulation...
+info: Entering event queue @ 1206966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1206268191000. Starting simulation...
+info: Entering event queue @ 1215966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1207268191000. Starting simulation...
+info: Entering event queue @ 1216966288000. Starting simulation...
+info: Entering event queue @ 1225966288000. Starting simulation...
+info: Entering event queue @ 1226123905000. Starting simulation...
switching cpus
-info: Entering event queue @ 1216268191000. Starting simulation...
+info: Entering event queue @ 1226123907000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1217268191000. Starting simulation...
-info: Entering event queue @ 1226268191000. Starting simulation...
-info: Entering event queue @ 1226426263000. Starting simulation...
+info: Entering event queue @ 1227123907000. Starting simulation...
switching cpus
-info: Entering event queue @ 1226426265000. Starting simulation...
+info: Entering event queue @ 1235966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1227426265000. Starting simulation...
+info: Entering event queue @ 1236966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1236268191000. Starting simulation...
+info: Entering event queue @ 1245966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1237268191000. Starting simulation...
+info: Entering event queue @ 1246966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1246268191000. Starting simulation...
+info: Entering event queue @ 1255966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1247268191000. Starting simulation...
+info: Entering event queue @ 1256966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1256268191000. Starting simulation...
+info: Entering event queue @ 1265966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1257268191000. Starting simulation...
+info: Entering event queue @ 1266966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1266268191000. Starting simulation...
+info: Entering event queue @ 1275966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1267268191000. Starting simulation...
+info: Entering event queue @ 1276966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1276268191000. Starting simulation...
+info: Entering event queue @ 1285966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1277268191000. Starting simulation...
+info: Entering event queue @ 1286966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1286268191000. Starting simulation...
+info: Entering event queue @ 1295966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1287268191000. Starting simulation...
+info: Entering event queue @ 1296966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1296268191000. Starting simulation...
+info: Entering event queue @ 1305966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1297268191000. Starting simulation...
+info: Entering event queue @ 1306966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1306268191000. Starting simulation...
+info: Entering event queue @ 1315966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1307268191000. Starting simulation...
+info: Entering event queue @ 1316966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1316268191000. Starting simulation...
+info: Entering event queue @ 1325966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1317268191000. Starting simulation...
+info: Entering event queue @ 1326966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1326268191000. Starting simulation...
+info: Entering event queue @ 1335966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1327268191000. Starting simulation...
+info: Entering event queue @ 1336966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1336268191000. Starting simulation...
+info: Entering event queue @ 1345966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1337268191000. Starting simulation...
+info: Entering event queue @ 1346966288000. Starting simulation...
+info: Entering event queue @ 1355966288000. Starting simulation...
+info: Entering event queue @ 1357069231000. Starting simulation...
switching cpus
-info: Entering event queue @ 1346268191000. Starting simulation...
+info: Entering event queue @ 1357069233000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1347268191000. Starting simulation...
-info: Entering event queue @ 1356268191000. Starting simulation...
-info: Entering event queue @ 1357370989000. Starting simulation...
+info: Entering event queue @ 1358069233000. Starting simulation...
switching cpus
-info: Entering event queue @ 1357370991000. Starting simulation...
+info: Entering event queue @ 1365966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1358370991000. Starting simulation...
+info: Entering event queue @ 1366966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1366268191000. Starting simulation...
+info: Entering event queue @ 1375966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1367268191000. Starting simulation...
+info: Entering event queue @ 1376966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1376268191000. Starting simulation...
+info: Entering event queue @ 1385966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1377268191000. Starting simulation...
+info: Entering event queue @ 1386966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1386268191000. Starting simulation...
+info: Entering event queue @ 1395966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1387268191000. Starting simulation...
+info: Entering event queue @ 1396966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1396268191000. Starting simulation...
+info: Entering event queue @ 1405966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1397268191000. Starting simulation...
+info: Entering event queue @ 1406966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1406268191000. Starting simulation...
+info: Entering event queue @ 1415966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1407268191000. Starting simulation...
+info: Entering event queue @ 1416966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1416268191000. Starting simulation...
+info: Entering event queue @ 1425966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1417268191000. Starting simulation...
+info: Entering event queue @ 1426966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1426268191000. Starting simulation...
+info: Entering event queue @ 1435966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1427268191000. Starting simulation...
+info: Entering event queue @ 1436966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1436268191000. Starting simulation...
+info: Entering event queue @ 1445966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1437268191000. Starting simulation...
+info: Entering event queue @ 1446966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1446268191000. Starting simulation...
+info: Entering event queue @ 1455966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1447268191000. Starting simulation...
+info: Entering event queue @ 1456966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1456268191000. Starting simulation...
+info: Entering event queue @ 1465966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1457268191000. Starting simulation...
+info: Entering event queue @ 1466966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1466268191000. Starting simulation...
+info: Entering event queue @ 1475966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1467268191000. Starting simulation...
+info: Entering event queue @ 1476966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1476268191000. Starting simulation...
+info: Entering event queue @ 1485966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1477268191000. Starting simulation...
+info: Entering event queue @ 1486966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1486268191000. Starting simulation...
+info: Entering event queue @ 1495966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1487268191000. Starting simulation...
+info: Entering event queue @ 1496966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1496268191000. Starting simulation...
+info: Entering event queue @ 1505966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1497268191000. Starting simulation...
+info: Entering event queue @ 1506966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1506268191000. Starting simulation...
+info: Entering event queue @ 1515966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1507268191000. Starting simulation...
+info: Entering event queue @ 1516966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1516268191000. Starting simulation...
+info: Entering event queue @ 1525966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1517268191000. Starting simulation...
+info: Entering event queue @ 1526966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1526268191000. Starting simulation...
+info: Entering event queue @ 1535966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1527268191000. Starting simulation...
+info: Entering event queue @ 1536966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1536268191000. Starting simulation...
+info: Entering event queue @ 1545966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1537268191000. Starting simulation...
+info: Entering event queue @ 1546966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1546268191000. Starting simulation...
+info: Entering event queue @ 1555966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1547268191000. Starting simulation...
+info: Entering event queue @ 1556966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1556268191000. Starting simulation...
+info: Entering event queue @ 1565966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1557268191000. Starting simulation...
+info: Entering event queue @ 1566966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1566268191000. Starting simulation...
+info: Entering event queue @ 1575966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1567268191000. Starting simulation...
+info: Entering event queue @ 1576966288000. Starting simulation...
+info: Entering event queue @ 1585966288000. Starting simulation...
+info: Entering event queue @ 1586222989000. Starting simulation...
switching cpus
-info: Entering event queue @ 1576268191000. Starting simulation...
+info: Entering event queue @ 1586222991000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1577268191000. Starting simulation...
-info: Entering event queue @ 1586268191000. Starting simulation...
-info: Entering event queue @ 1586524891000. Starting simulation...
+info: Entering event queue @ 1587222991000. Starting simulation...
switching cpus
-info: Entering event queue @ 1586524893000. Starting simulation...
+info: Entering event queue @ 1595966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1587524893000. Starting simulation...
+info: Entering event queue @ 1596966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1596268191000. Starting simulation...
+info: Entering event queue @ 1605966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1597268191000. Starting simulation...
+info: Entering event queue @ 1606966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1606268191000. Starting simulation...
+info: Entering event queue @ 1615966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1607268191000. Starting simulation...
+info: Entering event queue @ 1616966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1616268191000. Starting simulation...
+info: Entering event queue @ 1625966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1617268191000. Starting simulation...
+info: Entering event queue @ 1626966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1626268191000. Starting simulation...
+info: Entering event queue @ 1635966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1627268191000. Starting simulation...
+info: Entering event queue @ 1636966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1636268191000. Starting simulation...
+info: Entering event queue @ 1645966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1637268191000. Starting simulation...
+info: Entering event queue @ 1646966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1646268191000. Starting simulation...
+info: Entering event queue @ 1655966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1647268191000. Starting simulation...
+info: Entering event queue @ 1656966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1656268191000. Starting simulation...
+info: Entering event queue @ 1665966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1657268191000. Starting simulation...
+info: Entering event queue @ 1666966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1666268191000. Starting simulation...
+info: Entering event queue @ 1675966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1667268191000. Starting simulation...
+info: Entering event queue @ 1676966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1676268191000. Starting simulation...
+info: Entering event queue @ 1685966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1677268191000. Starting simulation...
+info: Entering event queue @ 1686966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1686268191000. Starting simulation...
+info: Entering event queue @ 1695966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1687268191000. Starting simulation...
+info: Entering event queue @ 1696966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1696268191000. Starting simulation...
+info: Entering event queue @ 1705966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1697268191000. Starting simulation...
+info: Entering event queue @ 1706966288000. Starting simulation...
+info: Entering event queue @ 1715966288000. Starting simulation...
+info: Entering event queue @ 1717167856000. Starting simulation...
switching cpus
-info: Entering event queue @ 1706268191000. Starting simulation...
+info: Entering event queue @ 1717167858000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1707268191000. Starting simulation...
-info: Entering event queue @ 1716268191000. Starting simulation...
-info: Entering event queue @ 1717470073000. Starting simulation...
+info: Entering event queue @ 1718167858000. Starting simulation...
switching cpus
-info: Entering event queue @ 1717470075000. Starting simulation...
+info: Entering event queue @ 1725966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1718470075000. Starting simulation...
+info: Entering event queue @ 1726966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1726268191000. Starting simulation...
+info: Entering event queue @ 1735966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1727268191000. Starting simulation...
+info: Entering event queue @ 1736966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1736268191000. Starting simulation...
+info: Entering event queue @ 1745966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1737268191000. Starting simulation...
+info: Entering event queue @ 1746966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1746268191000. Starting simulation...
+info: Entering event queue @ 1755966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1747268191000. Starting simulation...
+info: Entering event queue @ 1756966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1756268191000. Starting simulation...
+info: Entering event queue @ 1765966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1757268191000. Starting simulation...
+info: Entering event queue @ 1766966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1766268191000. Starting simulation...
+info: Entering event queue @ 1775966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1767268191000. Starting simulation...
+info: Entering event queue @ 1776966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1776268191000. Starting simulation...
+info: Entering event queue @ 1785966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1777268191000. Starting simulation...
+info: Entering event queue @ 1786966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1786268191000. Starting simulation...
+info: Entering event queue @ 1795966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1787268191000. Starting simulation...
+info: Entering event queue @ 1796966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1796268191000. Starting simulation...
+info: Entering event queue @ 1805966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1797268191000. Starting simulation...
+info: Entering event queue @ 1806966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1806268191000. Starting simulation...
+info: Entering event queue @ 1815966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1807268191000. Starting simulation...
+info: Entering event queue @ 1816966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1816268191000. Starting simulation...
+info: Entering event queue @ 1825966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1817268191000. Starting simulation...
+info: Entering event queue @ 1826966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1826268191000. Starting simulation...
+info: Entering event queue @ 1835966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1827268191000. Starting simulation...
+info: Entering event queue @ 1836966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1836268191000. Starting simulation...
+info: Entering event queue @ 1845966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1837268191000. Starting simulation...
+info: Entering event queue @ 1846966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1846268191000. Starting simulation...
+info: Entering event queue @ 1855966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1847268191000. Starting simulation...
+info: Entering event queue @ 1856966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1856268191000. Starting simulation...
+info: Entering event queue @ 1865966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1857268191000. Starting simulation...
+info: Entering event queue @ 1866966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1866268191000. Starting simulation...
+info: Entering event queue @ 1875966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1867268191000. Starting simulation...
+info: Entering event queue @ 1876966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1876268191000. Starting simulation...
+info: Entering event queue @ 1885966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1877268191000. Starting simulation...
+info: Entering event queue @ 1886966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1886268191000. Starting simulation...
+info: Entering event queue @ 1895966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1887268191000. Starting simulation...
+info: Entering event queue @ 1896966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1896268191000. Starting simulation...
+info: Entering event queue @ 1905966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1897268191000. Starting simulation...
+info: Entering event queue @ 1906966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1906268191000. Starting simulation...
+info: Entering event queue @ 1915966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1907268191000. Starting simulation...
+info: Entering event queue @ 1916966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1916268191000. Starting simulation...
+info: Entering event queue @ 1925966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1917268191000. Starting simulation...
+info: Entering event queue @ 1926966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1926268191000. Starting simulation...
+info: Entering event queue @ 1935966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1927268191000. Starting simulation...
+info: Entering event queue @ 1936966288000. Starting simulation...
+info: Entering event queue @ 1945966288000. Starting simulation...
+info: Entering event queue @ 1946321761000. Starting simulation...
switching cpus
-info: Entering event queue @ 1936268191000. Starting simulation...
+info: Entering event queue @ 1946321763000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1937268191000. Starting simulation...
-info: Entering event queue @ 1946268191000. Starting simulation...
-info: Entering event queue @ 1946623663000. Starting simulation...
+info: Entering event queue @ 1947321763000. Starting simulation...
switching cpus
-info: Entering event queue @ 1946623665000. Starting simulation...
+info: Entering event queue @ 1955966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1947623665000. Starting simulation...
+info: Entering event queue @ 1956966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1956268191000. Starting simulation...
+info: Entering event queue @ 1965966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1957268191000. Starting simulation...
+info: Entering event queue @ 1966966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1966268191000. Starting simulation...
+info: Entering event queue @ 1975966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1967268191000. Starting simulation...
+info: Entering event queue @ 1976966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1976268191000. Starting simulation...
+info: Entering event queue @ 1985966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1977268191000. Starting simulation...
+info: Entering event queue @ 1986966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1986268191000. Starting simulation...
+info: Entering event queue @ 1995966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1987268191000. Starting simulation...
+info: Entering event queue @ 1996966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 1996268191000. Starting simulation...
+info: Entering event queue @ 2005966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 1997268191000. Starting simulation...
+info: Entering event queue @ 2006966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2006268191000. Starting simulation...
+info: Entering event queue @ 2015966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2007268191000. Starting simulation...
+info: Entering event queue @ 2016966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2016268191000. Starting simulation...
+info: Entering event queue @ 2025966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2017268191000. Starting simulation...
+info: Entering event queue @ 2026966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2026268191000. Starting simulation...
+info: Entering event queue @ 2035966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2027268191000. Starting simulation...
+info: Entering event queue @ 2036966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2036268191000. Starting simulation...
+info: Entering event queue @ 2045966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2037268191000. Starting simulation...
+info: Entering event queue @ 2046966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2046268191000. Starting simulation...
+info: Entering event queue @ 2055966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2047268191000. Starting simulation...
+info: Entering event queue @ 2056966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2056268191000. Starting simulation...
+info: Entering event queue @ 2065966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2057268191000. Starting simulation...
+info: Entering event queue @ 2066966288000. Starting simulation...
+info: Entering event queue @ 2075966288000. Starting simulation...
+info: Entering event queue @ 2077266937000. Starting simulation...
switching cpus
-info: Entering event queue @ 2066268191000. Starting simulation...
+info: Entering event queue @ 2077266939000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2067268191000. Starting simulation...
-info: Entering event queue @ 2076268191000. Starting simulation...
-info: Entering event queue @ 2077568845000. Starting simulation...
+info: Entering event queue @ 2078266939000. Starting simulation...
switching cpus
-info: Entering event queue @ 2077568847000. Starting simulation...
+info: Entering event queue @ 2085966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2078568847000. Starting simulation...
+info: Entering event queue @ 2086966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2086268191000. Starting simulation...
+info: Entering event queue @ 2095966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2087268191000. Starting simulation...
+info: Entering event queue @ 2096966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2096268191000. Starting simulation...
+info: Entering event queue @ 2105966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2097268191000. Starting simulation...
+info: Entering event queue @ 2106966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2106268191000. Starting simulation...
+info: Entering event queue @ 2115966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2107268191000. Starting simulation...
+info: Entering event queue @ 2116966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2116268191000. Starting simulation...
+info: Entering event queue @ 2125966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2117268191000. Starting simulation...
+info: Entering event queue @ 2126966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2126268191000. Starting simulation...
+info: Entering event queue @ 2135966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2127268191000. Starting simulation...
+info: Entering event queue @ 2136966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2136268191000. Starting simulation...
+info: Entering event queue @ 2145966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2137268191000. Starting simulation...
+info: Entering event queue @ 2146966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2146268191000. Starting simulation...
+info: Entering event queue @ 2155966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2147268191000. Starting simulation...
+info: Entering event queue @ 2156966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2156268191000. Starting simulation...
+info: Entering event queue @ 2165966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2157268191000. Starting simulation...
+info: Entering event queue @ 2166966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2166268191000. Starting simulation...
+info: Entering event queue @ 2175966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2167268191000. Starting simulation...
+info: Entering event queue @ 2176966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2176268191000. Starting simulation...
+info: Entering event queue @ 2185966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2177268191000. Starting simulation...
+info: Entering event queue @ 2186966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2186268191000. Starting simulation...
+info: Entering event queue @ 2195966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2187268191000. Starting simulation...
+info: Entering event queue @ 2196966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2196268191000. Starting simulation...
+info: Entering event queue @ 2205966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2197268191000. Starting simulation...
+info: Entering event queue @ 2206966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2206268191000. Starting simulation...
+info: Entering event queue @ 2215966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2207268191000. Starting simulation...
+info: Entering event queue @ 2216966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2216268191000. Starting simulation...
+info: Entering event queue @ 2225966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2217268191000. Starting simulation...
+info: Entering event queue @ 2226966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2226268191000. Starting simulation...
+info: Entering event queue @ 2235966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2227268191000. Starting simulation...
+info: Entering event queue @ 2236966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2236268191000. Starting simulation...
+info: Entering event queue @ 2245966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2237268191000. Starting simulation...
+info: Entering event queue @ 2246966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2246268191000. Starting simulation...
+info: Entering event queue @ 2255966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2247268191000. Starting simulation...
+info: Entering event queue @ 2256966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2256268191000. Starting simulation...
+info: Entering event queue @ 2265966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2257268191000. Starting simulation...
+info: Entering event queue @ 2266966288000. Starting simulation...
switching cpus
-info: Entering event queue @ 2266268191000. Starting simulation...
+info: Entering event queue @ 2275966288000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2267268191000. Starting simulation...
+info: Entering event queue @ 2276966288000. Starting simulation...
+info: Entering event queue @ 2276966296500. Starting simulation...
+info: Entering event queue @ 2276966301000. Starting simulation...
switching cpus
-info: Entering event queue @ 2276268191000. Starting simulation...
+info: Entering event queue @ 2276966305500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2277268191000. Starting simulation...
-info: Entering event queue @ 2277268954000. Starting simulation...
-info: Entering event queue @ 2277268962000. Starting simulation...
+info: Entering event queue @ 2277966305500. Starting simulation...
+info: Entering event queue @ 2277966669500. Starting simulation...
+info: Entering event queue @ 2277966675000. Starting simulation...
switching cpus
-info: Entering event queue @ 2277268966500. Starting simulation...
+info: Entering event queue @ 2277966679500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2278268966500. Starting simulation...
+info: Entering event queue @ 2278966679500. Starting simulation...
switching cpus
-info: Entering event queue @ 2278269523500. Starting simulation...
+info: Entering event queue @ 2278966727000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2279269523500. Starting simulation...
+info: Entering event queue @ 2279966727000. Starting simulation...
switching cpus
-info: Entering event queue @ 2279269645000. Starting simulation...
+info: Entering event queue @ 2279966892500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2280269645000. Starting simulation...
+info: Entering event queue @ 2280966892500. Starting simulation...
switching cpus
-info: Entering event queue @ 2280269727000. Starting simulation...
+info: Entering event queue @ 2280967718000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2281269727000. Starting simulation...
+info: Entering event queue @ 2281967718000. Starting simulation...
switching cpus
-info: Entering event queue @ 2281270778500. Starting simulation...
+info: Entering event queue @ 2281967767000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2282270778500. Starting simulation...
+info: Entering event queue @ 2282967767000. Starting simulation...
switching cpus
-info: Entering event queue @ 2282270863000. Starting simulation...
+info: Entering event queue @ 2282971689500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2283270863000. Starting simulation...
+info: Entering event queue @ 2283971689500. Starting simulation...
switching cpus
-info: Entering event queue @ 2283277136500. Starting simulation...
+info: Entering event queue @ 2283971806000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2284277136500. Starting simulation...
+info: Entering event queue @ 2284971806000. Starting simulation...
switching cpus
-info: Entering event queue @ 2284277182000. Starting simulation...
+info: Entering event queue @ 2284971880000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2285277182000. Starting simulation...
+info: Entering event queue @ 2285971880000. Starting simulation...
switching cpus
-info: Entering event queue @ 2285277195500. Starting simulation...
+info: Entering event queue @ 2285971904500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2286277195500. Starting simulation...
+info: Entering event queue @ 2286971904500. Starting simulation...
switching cpus
-info: Entering event queue @ 2286277219000. Starting simulation...
+info: Entering event queue @ 2286972050000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2287277219000. Starting simulation...
+info: Entering event queue @ 2287972050000. Starting simulation...
switching cpus
-info: Entering event queue @ 2287277304000. Starting simulation...
+info: Entering event queue @ 2287972064000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2288277304000. Starting simulation...
+info: Entering event queue @ 2288972064000. Starting simulation...
switching cpus
-info: Entering event queue @ 2288277373000. Starting simulation...
+info: Entering event queue @ 2288972091500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2289277373000. Starting simulation...
+info: Entering event queue @ 2289972091500. Starting simulation...
switching cpus
-info: Entering event queue @ 2289277451000. Starting simulation...
+info: Entering event queue @ 2289980099000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2290277451000. Starting simulation...
+info: Entering event queue @ 2290980099000. Starting simulation...
switching cpus
-info: Entering event queue @ 2290285946000. Starting simulation...
+info: Entering event queue @ 2290980164000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2291285946000. Starting simulation...
+info: Entering event queue @ 2291980164000. Starting simulation...
switching cpus
-info: Entering event queue @ 2291286099000. Starting simulation...
+info: Entering event queue @ 2291980173000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2292286099000. Starting simulation...
+info: Entering event queue @ 2292980173000. Starting simulation...
switching cpus
-info: Entering event queue @ 2292286189000. Starting simulation...
+info: Entering event queue @ 2292980190000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2293286189000. Starting simulation...
+info: Entering event queue @ 2293980190000. Starting simulation...
switching cpus
-info: Entering event queue @ 2293286279000. Starting simulation...
+info: Entering event queue @ 2293980313000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2294286279000. Starting simulation...
+info: Entering event queue @ 2294980313000. Starting simulation...
switching cpus
-info: Entering event queue @ 2294286408000. Starting simulation...
+info: Entering event queue @ 2294980366000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2295286408000. Starting simulation...
+info: Entering event queue @ 2295980366000. Starting simulation...
switching cpus
-info: Entering event queue @ 2295286461000. Starting simulation...
+info: Entering event queue @ 2295980491500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2296286461000. Starting simulation...
+info: Entering event queue @ 2296980491500. Starting simulation...
switching cpus
-info: Entering event queue @ 2296286464000. Starting simulation...
+info: Entering event queue @ 2296980655000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2297286464000. Starting simulation...
+info: Entering event queue @ 2297980655000. Starting simulation...
+info: Entering event queue @ 2297980854500. Starting simulation...
switching cpus
-info: Entering event queue @ 2297286553000. Starting simulation...
+info: Entering event queue @ 2297980855500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2298286553000. Starting simulation...
+info: Entering event queue @ 2298980855500. Starting simulation...
switching cpus
-info: Entering event queue @ 2298286587000. Starting simulation...
+info: Entering event queue @ 2298980896000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2299286587000. Starting simulation...
+info: Entering event queue @ 2299980896000. Starting simulation...
+info: Entering event queue @ 2299988769500. Starting simulation...
+info: Entering event queue @ 2299988774500. Starting simulation...
switching cpus
-info: Entering event queue @ 2299286735000. Starting simulation...
+info: Entering event queue @ 2299988779000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2300286735000. Starting simulation...
-info: Entering event queue @ 2300294447000. Starting simulation...
-info: Entering event queue @ 2300294452000. Starting simulation...
+info: Entering event queue @ 2300988779000. Starting simulation...
switching cpus
-info: Entering event queue @ 2300294456500. Starting simulation...
+info: Entering event queue @ 2300988932000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2301294456500. Starting simulation...
+info: Entering event queue @ 2301988932000. Starting simulation...
switching cpus
-info: Entering event queue @ 2301294551000. Starting simulation...
+info: Entering event queue @ 2301988991000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2302294551000. Starting simulation...
+info: Entering event queue @ 2302988991000. Starting simulation...
switching cpus
-info: Entering event queue @ 2302294592000. Starting simulation...
+info: Entering event queue @ 2302998893000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2303294592000. Starting simulation...
+info: Entering event queue @ 2303998893000. Starting simulation...
switching cpus
-info: Entering event queue @ 2303304358000. Starting simulation...
+info: Entering event queue @ 2303999033000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2304304358000. Starting simulation...
+info: Entering event queue @ 2304999033000. Starting simulation...
+info: Entering event queue @ 2306420845000. Starting simulation...
switching cpus
-info: Entering event queue @ 2304304509000. Starting simulation...
+info: Entering event queue @ 2306420847000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2305304509000. Starting simulation...
-info: Entering event queue @ 2306722747000. Starting simulation...
+info: Entering event queue @ 2307420847000. Starting simulation...
switching cpus
-info: Entering event queue @ 2306722749000. Starting simulation...
+info: Entering event queue @ 2307429463000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2307722749000. Starting simulation...
+info: Entering event queue @ 2308429463000. Starting simulation...
switching cpus
-info: Entering event queue @ 2307731302000. Starting simulation...
+info: Entering event queue @ 2308429518000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2308731302000. Starting simulation...
+info: Entering event queue @ 2309429518000. Starting simulation...
switching cpus
-info: Entering event queue @ 2308731447000. Starting simulation...
+info: Entering event queue @ 2309436929000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2309731447000. Starting simulation...
+info: Entering event queue @ 2310436929000. Starting simulation...
+info: Entering event queue @ 2310445490500. Starting simulation...
+info: Entering event queue @ 2310445497000. Starting simulation...
switching cpus
-info: Entering event queue @ 2309739461000. Starting simulation...
+info: Entering event queue @ 2310445501500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2310739461000. Starting simulation...
-info: Entering event queue @ 2310747899500. Starting simulation...
-info: Entering event queue @ 2310747906000. Starting simulation...
+info: Entering event queue @ 2311445501500. Starting simulation...
switching cpus
-info: Entering event queue @ 2310747910500. Starting simulation...
+info: Entering event queue @ 2311445524000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2311747910500. Starting simulation...
+info: Entering event queue @ 2312445524000. Starting simulation...
switching cpus
-info: Entering event queue @ 2311748072000. Starting simulation...
+info: Entering event queue @ 2312445649000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2312748072000. Starting simulation...
+info: Entering event queue @ 2313445649000. Starting simulation...
switching cpus
-info: Entering event queue @ 2312748081000. Starting simulation...
+info: Entering event queue @ 2313445802000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2313748081000. Starting simulation...
+info: Entering event queue @ 2314445802000. Starting simulation...
switching cpus
-info: Entering event queue @ 2313748138000. Starting simulation...
+info: Entering event queue @ 2314445861000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2314748138000. Starting simulation...
+info: Entering event queue @ 2315445861000. Starting simulation...
switching cpus
-info: Entering event queue @ 2314748214000. Starting simulation...
+info: Entering event queue @ 2315445973000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2315748214000. Starting simulation...
+info: Entering event queue @ 2316445973000. Starting simulation...
switching cpus
-info: Entering event queue @ 2315748327000. Starting simulation...
+info: Entering event queue @ 2316446034000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2316748327000. Starting simulation...
+info: Entering event queue @ 2317446034000. Starting simulation...
switching cpus
-info: Entering event queue @ 2316748378500. Starting simulation...
+info: Entering event queue @ 2317446194500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2317748378500. Starting simulation...
+info: Entering event queue @ 2318446194500. Starting simulation...
switching cpus
-info: Entering event queue @ 2317748526000. Starting simulation...
+info: Entering event queue @ 2318446348000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2318748526000. Starting simulation...
+info: Entering event queue @ 2319446348000. Starting simulation...
switching cpus
-info: Entering event queue @ 2318748667500. Starting simulation...
+info: Entering event queue @ 2319446393000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2319748667500. Starting simulation...
+info: Entering event queue @ 2320446393000. Starting simulation...
+info: Entering event queue @ 2320446744000. Starting simulation...
switching cpus
-info: Entering event queue @ 2319748721000. Starting simulation...
+info: Entering event queue @ 2320446745000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2320748721000. Starting simulation...
-info: Entering event queue @ 2320749014500. Starting simulation...
+info: Entering event queue @ 2321446745000. Starting simulation...
switching cpus
-info: Entering event queue @ 2320749016000. Starting simulation...
+info: Entering event queue @ 2321446843000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2321749016000. Starting simulation...
+info: Entering event queue @ 2322446843000. Starting simulation...
switching cpus
-info: Entering event queue @ 2321749158000. Starting simulation...
+info: Entering event queue @ 2322446904000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2322749158000. Starting simulation...
+info: Entering event queue @ 2323446904000. Starting simulation...
switching cpus
-info: Entering event queue @ 2322749269000. Starting simulation...
+info: Entering event queue @ 2323456659000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2323749269000. Starting simulation...
+info: Entering event queue @ 2324456659000. Starting simulation...
switching cpus
-info: Entering event queue @ 2323749354500. Starting simulation...
+info: Entering event queue @ 2324456757000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2324749354500. Starting simulation...
+info: Entering event queue @ 2325456757000. Starting simulation...
switching cpus
-info: Entering event queue @ 2324749511000. Starting simulation...
+info: Entering event queue @ 2325456829500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2325749511000. Starting simulation...
+info: Entering event queue @ 2326456829500. Starting simulation...
switching cpus
-info: Entering event queue @ 2325749616000. Starting simulation...
+info: Entering event queue @ 2326458375000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2326749616000. Starting simulation...
+info: Entering event queue @ 2327458375000. Starting simulation...
switching cpus
-info: Entering event queue @ 2326749741000. Starting simulation...
+info: Entering event queue @ 2327458422000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2327749741000. Starting simulation...
+info: Entering event queue @ 2328458422000. Starting simulation...
switching cpus
-info: Entering event queue @ 2327749847000. Starting simulation...
+info: Entering event queue @ 2328458566500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2328749847000. Starting simulation...
+info: Entering event queue @ 2329458566500. Starting simulation...
switching cpus
-info: Entering event queue @ 2328749874000. Starting simulation...
+info: Entering event queue @ 2329458584500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2329749874000. Starting simulation...
+info: Entering event queue @ 2330458584500. Starting simulation...
switching cpus
-info: Entering event queue @ 2329759222000. Starting simulation...
+info: Entering event queue @ 2330458701000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2330759222000. Starting simulation...
+info: Entering event queue @ 2331458701000. Starting simulation...
switching cpus
-info: Entering event queue @ 2330759348000. Starting simulation...
+info: Entering event queue @ 2331458728000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2331759348000. Starting simulation...
+info: Entering event queue @ 2332458728000. Starting simulation...
switching cpus
-info: Entering event queue @ 2331759465500. Starting simulation...
+info: Entering event queue @ 2332458887000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2332759465500. Starting simulation...
+info: Entering event queue @ 2333458887000. Starting simulation...
switching cpus
-info: Entering event queue @ 2332759584500. Starting simulation...
+info: Entering event queue @ 2333458927000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2333759584500. Starting simulation...
+info: Entering event queue @ 2334458927000. Starting simulation...
switching cpus
-info: Entering event queue @ 2333759608000. Starting simulation...
+info: Entering event queue @ 2334458930500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2334759608000. Starting simulation...
+info: Entering event queue @ 2335458930500. Starting simulation...
switching cpus
-info: Entering event queue @ 2334759610500. Starting simulation...
+info: Entering event queue @ 2335458946000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2335759610500. Starting simulation...
+info: Entering event queue @ 2336458946000. Starting simulation...
switching cpus
-info: Entering event queue @ 2335759640000. Starting simulation...
+info: Entering event queue @ 2336460942000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2336759640000. Starting simulation...
+info: Entering event queue @ 2337460942000. Starting simulation...
switching cpus
-info: Entering event queue @ 2336765515000. Starting simulation...
+info: Entering event queue @ 2337461094000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2337765515000. Starting simulation...
+info: Entering event queue @ 2338461094000. Starting simulation...
+info: Entering event queue @ 2339157445000. Starting simulation...
switching cpus
-info: Entering event queue @ 2337765651000. Starting simulation...
+info: Entering event queue @ 2339157447000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2338765651000. Starting simulation...
-info: Entering event queue @ 2339460421000. Starting simulation...
+info: Entering event queue @ 2340157447000. Starting simulation...
switching cpus
-info: Entering event queue @ 2339460423000. Starting simulation...
+info: Entering event queue @ 2340161367000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2340460423000. Starting simulation...
+info: Entering event queue @ 2341161367000. Starting simulation...
switching cpus
-info: Entering event queue @ 2340464476000. Starting simulation...
+info: Entering event queue @ 2341161393000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2341464476000. Starting simulation...
+info: Entering event queue @ 2342161393000. Starting simulation...
switching cpus
-info: Entering event queue @ 2341464590000. Starting simulation...
+info: Entering event queue @ 2342161440000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2342464590000. Starting simulation...
+info: Entering event queue @ 2343161440000. Starting simulation...
switching cpus
-info: Entering event queue @ 2342464662000. Starting simulation...
+info: Entering event queue @ 2343161538000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2343464662000. Starting simulation...
+info: Entering event queue @ 2344161538000. Starting simulation...
switching cpus
-info: Entering event queue @ 2343464764000. Starting simulation...
+info: Entering event queue @ 2344161625000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2344464764000. Starting simulation...
+info: Entering event queue @ 2345161625000. Starting simulation...
switching cpus
-info: Entering event queue @ 2344464828000. Starting simulation...
+info: Entering event queue @ 2345161713500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2345464828000. Starting simulation...
+info: Entering event queue @ 2346161713500. Starting simulation...
switching cpus
-info: Entering event queue @ 2345464841000. Starting simulation...
+info: Entering event queue @ 2346161788500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2346464841000. Starting simulation...
+info: Entering event queue @ 2347161788500. Starting simulation...
switching cpus
-info: Entering event queue @ 2346464923000. Starting simulation...
+info: Entering event queue @ 2347161936000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2347464923000. Starting simulation...
+info: Entering event queue @ 2348161936000. Starting simulation...
switching cpus
-info: Entering event queue @ 2347464976500. Starting simulation...
+info: Entering event queue @ 2348162002000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2348464976500. Starting simulation...
+info: Entering event queue @ 2349162002000. Starting simulation...
switching cpus
-info: Entering event queue @ 2348465079000. Starting simulation...
+info: Entering event queue @ 2349162065000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2349465079000. Starting simulation...
+info: Entering event queue @ 2350162065000. Starting simulation...
switching cpus
-info: Entering event queue @ 2349465120000. Starting simulation...
+info: Entering event queue @ 2350162134000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2350465120000. Starting simulation...
+info: Entering event queue @ 2351162134000. Starting simulation...
switching cpus
-info: Entering event queue @ 2350465140000. Starting simulation...
+info: Entering event queue @ 2351162263000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2351465140000. Starting simulation...
+info: Entering event queue @ 2352162263000. Starting simulation...
switching cpus
-info: Entering event queue @ 2351465243000. Starting simulation...
+info: Entering event queue @ 2352162285000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2352465243000. Starting simulation...
+info: Entering event queue @ 2353162285000. Starting simulation...
switching cpus
-info: Entering event queue @ 2352465352000. Starting simulation...
+info: Entering event queue @ 2353170607000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2353465352000. Starting simulation...
+info: Entering event queue @ 2354170607000. Starting simulation...
switching cpus
-info: Entering event queue @ 2353474826000. Starting simulation...
+info: Entering event queue @ 2354170736000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2354474826000. Starting simulation...
+info: Entering event queue @ 2355170736000. Starting simulation...
switching cpus
-info: Entering event queue @ 2354474888000. Starting simulation...
+info: Entering event queue @ 2355170892500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2355474888000. Starting simulation...
+info: Entering event queue @ 2356170892500. Starting simulation...
switching cpus
-info: Entering event queue @ 2355474996000. Starting simulation...
+info: Entering event queue @ 2356172531000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2356474996000. Starting simulation...
+info: Entering event queue @ 2357172531000. Starting simulation...
switching cpus
-info: Entering event queue @ 2356477220000. Starting simulation...
+info: Entering event queue @ 2357172559000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2357477220000. Starting simulation...
+info: Entering event queue @ 2358172559000. Starting simulation...
switching cpus
-info: Entering event queue @ 2357477294000. Starting simulation...
+info: Entering event queue @ 2358172614000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2358477294000. Starting simulation...
+info: Entering event queue @ 2359172614000. Starting simulation...
switching cpus
-info: Entering event queue @ 2358477324000. Starting simulation...
+info: Entering event queue @ 2359172646000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2359477324000. Starting simulation...
+info: Entering event queue @ 2360172646000. Starting simulation...
switching cpus
-info: Entering event queue @ 2359477395000. Starting simulation...
+info: Entering event queue @ 2360172678000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2360477395000. Starting simulation...
+info: Entering event queue @ 2361172678000. Starting simulation...
switching cpus
-info: Entering event queue @ 2360477426000. Starting simulation...
+info: Entering event queue @ 2361172808000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2361477426000. Starting simulation...
+info: Entering event queue @ 2362172808000. Starting simulation...
switching cpus
-info: Entering event queue @ 2361477471000. Starting simulation...
+info: Entering event queue @ 2362172960000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2362477471000. Starting simulation...
+info: Entering event queue @ 2363172960000. Starting simulation...
switching cpus
-info: Entering event queue @ 2362477622000. Starting simulation...
+info: Entering event queue @ 2363178221000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2363477622000. Starting simulation...
+info: Entering event queue @ 2364178221000. Starting simulation...
switching cpus
-info: Entering event queue @ 2363483382000. Starting simulation...
+info: Entering event queue @ 2364178280000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2364483382000. Starting simulation...
+info: Entering event queue @ 2365178280000. Starting simulation...
switching cpus
-info: Entering event queue @ 2364483394000. Starting simulation...
+info: Entering event queue @ 2365178287500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2365483394000. Starting simulation...
+info: Entering event queue @ 2366178287500. Starting simulation...
switching cpus
-info: Entering event queue @ 2365483556500. Starting simulation...
+info: Entering event queue @ 2366178360000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2366483556500. Starting simulation...
+info: Entering event queue @ 2367178360000. Starting simulation...
switching cpus
-info: Entering event queue @ 2366483582500. Starting simulation...
+info: Entering event queue @ 2367178437000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2367483582500. Starting simulation...
+info: Entering event queue @ 2368178437000. Starting simulation...
switching cpus
-info: Entering event queue @ 2367483684000. Starting simulation...
+info: Entering event queue @ 2368178488000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2368483684000. Starting simulation...
+info: Entering event queue @ 2369178488000. Starting simulation...
switching cpus
-info: Entering event queue @ 2368483745000. Starting simulation...
+info: Entering event queue @ 2369178596000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2369483745000. Starting simulation...
+info: Entering event queue @ 2370178596000. Starting simulation...
switching cpus
-info: Entering event queue @ 2369483898000. Starting simulation...
+info: Entering event queue @ 2370178656000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2370483898000. Starting simulation...
+info: Entering event queue @ 2371178656000. Starting simulation...
+info: Entering event queue @ 2371894045000. Starting simulation...
switching cpus
-info: Entering event queue @ 2370483923000. Starting simulation...
+info: Entering event queue @ 2371894047000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2371483923000. Starting simulation...
-info: Entering event queue @ 2372195491000. Starting simulation...
+info: Entering event queue @ 2372894047000. Starting simulation...
switching cpus
-info: Entering event queue @ 2372195493000. Starting simulation...
+info: Entering event queue @ 2372894102500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2373195493000. Starting simulation...
+info: Entering event queue @ 2373894102500. Starting simulation...
switching cpus
-info: Entering event queue @ 2373195650000. Starting simulation...
+info: Entering event queue @ 2373894137500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2374195650000. Starting simulation...
+info: Entering event queue @ 2374894137500. Starting simulation...
switching cpus
-info: Entering event queue @ 2374195738000. Starting simulation...
+info: Entering event queue @ 2374894259000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2375195738000. Starting simulation...
+info: Entering event queue @ 2375894259000. Starting simulation...
switching cpus
-info: Entering event queue @ 2375195783500. Starting simulation...
+info: Entering event queue @ 2375894306000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2376195783500. Starting simulation...
+info: Entering event queue @ 2376894306000. Starting simulation...
switching cpus
-info: Entering event queue @ 2376195897000. Starting simulation...
+info: Entering event queue @ 2376900398000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2377195897000. Starting simulation...
+info: Entering event queue @ 2377900398000. Starting simulation...
switching cpus
-info: Entering event queue @ 2377202280000. Starting simulation...
+info: Entering event queue @ 2377900421000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2378202280000. Starting simulation...
+info: Entering event queue @ 2378900421000. Starting simulation...
switching cpus
-info: Entering event queue @ 2378202290000. Starting simulation...
+info: Entering event queue @ 2378900488500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2379202290000. Starting simulation...
+info: Entering event queue @ 2379900488500. Starting simulation...
switching cpus
-info: Entering event queue @ 2379202375500. Starting simulation...
+info: Entering event queue @ 2379900521000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2380202375500. Starting simulation...
+info: Entering event queue @ 2380900521000. Starting simulation...
switching cpus
-info: Entering event queue @ 2380202449000. Starting simulation...
+info: Entering event queue @ 2380900624000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2381202449000. Starting simulation...
+info: Entering event queue @ 2381900624000. Starting simulation...
switching cpus
-info: Entering event queue @ 2381202571000. Starting simulation...
+info: Entering event queue @ 2381900718000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2382202571000. Starting simulation...
+info: Entering event queue @ 2382900718000. Starting simulation...
switching cpus
-info: Entering event queue @ 2382202731000. Starting simulation...
+info: Entering event queue @ 2382900790000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2383202731000. Starting simulation...
+info: Entering event queue @ 2383900790000. Starting simulation...
switching cpus
-info: Entering event queue @ 2383202780000. Starting simulation...
+info: Entering event queue @ 2383900839000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2384202780000. Starting simulation...
+info: Entering event queue @ 2384900839000. Starting simulation...
switching cpus
-info: Entering event queue @ 2384202932000. Starting simulation...
+info: Entering event queue @ 2384910381000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2385202932000. Starting simulation...
+info: Entering event queue @ 2385910381000. Starting simulation...
switching cpus
-info: Entering event queue @ 2385212508000. Starting simulation...
+info: Entering event queue @ 2385910485000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2386212508000. Starting simulation...
+info: Entering event queue @ 2386910485000. Starting simulation...
switching cpus
-info: Entering event queue @ 2386212623000. Starting simulation...
+info: Entering event queue @ 2386910628000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2387212623000. Starting simulation...
+info: Entering event queue @ 2387910628000. Starting simulation...
switching cpus
-info: Entering event queue @ 2387212742000. Starting simulation...
+info: Entering event queue @ 2387911152000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2388212742000. Starting simulation...
+info: Entering event queue @ 2388911152000. Starting simulation...
switching cpus
-info: Entering event queue @ 2388213348000. Starting simulation...
+info: Entering event queue @ 2388914114000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2389213348000. Starting simulation...
+info: Entering event queue @ 2389914114000. Starting simulation...
switching cpus
-info: Entering event queue @ 2389215992000. Starting simulation...
+info: Entering event queue @ 2389914243000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2390215992000. Starting simulation...
+info: Entering event queue @ 2390914243000. Starting simulation...
switching cpus
-info: Entering event queue @ 2390216041000. Starting simulation...
+info: Entering event queue @ 2390914368000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2391216041000. Starting simulation...
+info: Entering event queue @ 2391914368000. Starting simulation...
switching cpus
-info: Entering event queue @ 2391216125000. Starting simulation...
+info: Entering event queue @ 2391914402000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2392216125000. Starting simulation...
+info: Entering event queue @ 2392914402000. Starting simulation...
switching cpus
-info: Entering event queue @ 2392216251000. Starting simulation...
+info: Entering event queue @ 2392914536000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2393216251000. Starting simulation...
+info: Entering event queue @ 2393914536000. Starting simulation...
switching cpus
-info: Entering event queue @ 2393216329000. Starting simulation...
+info: Entering event queue @ 2393914563000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2394216329000. Starting simulation...
+info: Entering event queue @ 2394914563000. Starting simulation...
switching cpus
-info: Entering event queue @ 2394216356000. Starting simulation...
+info: Entering event queue @ 2394914712000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2395216356000. Starting simulation...
+info: Entering event queue @ 2395914712000. Starting simulation...
switching cpus
-info: Entering event queue @ 2395216502000. Starting simulation...
+info: Entering event queue @ 2395914740000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2396216502000. Starting simulation...
+info: Entering event queue @ 2396914740000. Starting simulation...
switching cpus
-info: Entering event queue @ 2396216531000. Starting simulation...
+info: Entering event queue @ 2396914806500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2397216531000. Starting simulation...
+info: Entering event queue @ 2397914806500. Starting simulation...
switching cpus
-info: Entering event queue @ 2397216596500. Starting simulation...
+info: Entering event queue @ 2397914904000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2398216596500. Starting simulation...
+info: Entering event queue @ 2398914904000. Starting simulation...
switching cpus
-info: Entering event queue @ 2398216687000. Starting simulation...
+info: Entering event queue @ 2398914957000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2399216687000. Starting simulation...
+info: Entering event queue @ 2399914957000. Starting simulation...
switching cpus
-info: Entering event queue @ 2399216754000. Starting simulation...
+info: Entering event queue @ 2399915059000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2400216754000. Starting simulation...
+info: Entering event queue @ 2400915059000. Starting simulation...
switching cpus
-info: Entering event queue @ 2400216856000. Starting simulation...
+info: Entering event queue @ 2400915130000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2401216856000. Starting simulation...
+info: Entering event queue @ 2401915130000. Starting simulation...
+info: Entering event queue @ 2401915136500. Starting simulation...
switching cpus
-info: Entering event queue @ 2401216927000. Starting simulation...
+info: Entering event queue @ 2401915141000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2402216927000. Starting simulation...
-info: Entering event queue @ 2402216935500. Starting simulation...
+info: Entering event queue @ 2402915141000. Starting simulation...
switching cpus
-info: Entering event queue @ 2402216940000. Starting simulation...
+info: Entering event queue @ 2402915191000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2403216940000. Starting simulation...
+info: Entering event queue @ 2403915191000. Starting simulation...
+info: Entering event queue @ 2404629421000. Starting simulation...
switching cpus
-info: Entering event queue @ 2403216956000. Starting simulation...
+info: Entering event queue @ 2404629423000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2404216956000. Starting simulation...
-info: Entering event queue @ 2404931326000. Starting simulation...
+info: Entering event queue @ 2405629423000. Starting simulation...
switching cpus
-info: Entering event queue @ 2404931328000. Starting simulation...
+info: Entering event queue @ 2405629508000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2405931328000. Starting simulation...
+info: Entering event queue @ 2406629508000. Starting simulation...
switching cpus
-info: Entering event queue @ 2405931413000. Starting simulation...
+info: Entering event queue @ 2406632022000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2406931413000. Starting simulation...
+info: Entering event queue @ 2407632022000. Starting simulation...
switching cpus
-info: Entering event queue @ 2406934152000. Starting simulation...
+info: Entering event queue @ 2407632051000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2407934152000. Starting simulation...
+info: Entering event queue @ 2408632051000. Starting simulation...
switching cpus
-info: Entering event queue @ 2407934227000. Starting simulation...
+info: Entering event queue @ 2408632082000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2408934227000. Starting simulation...
+info: Entering event queue @ 2409632082000. Starting simulation...
switching cpus
-info: Entering event queue @ 2408934375000. Starting simulation...
+info: Entering event queue @ 2409632155000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2409934375000. Starting simulation...
+info: Entering event queue @ 2410632155000. Starting simulation...
switching cpus
-info: Entering event queue @ 2409934451000. Starting simulation...
+info: Entering event queue @ 2410632268000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2410934451000. Starting simulation...
+info: Entering event queue @ 2411632268000. Starting simulation...
switching cpus
-info: Entering event queue @ 2410934593000. Starting simulation...
+info: Entering event queue @ 2411632347000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2411934593000. Starting simulation...
+info: Entering event queue @ 2412632347000. Starting simulation...
switching cpus
-info: Entering event queue @ 2411934698000. Starting simulation...
+info: Entering event queue @ 2412632398000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2412934698000. Starting simulation...
+info: Entering event queue @ 2413632398000. Starting simulation...
switching cpus
-info: Entering event queue @ 2412934765000. Starting simulation...
+info: Entering event queue @ 2413632529000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2413934765000. Starting simulation...
+info: Entering event queue @ 2414632529000. Starting simulation...
switching cpus
-info: Entering event queue @ 2413934897000. Starting simulation...
+info: Entering event queue @ 2414632639500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2414934897000. Starting simulation...
+info: Entering event queue @ 2415632639500. Starting simulation...
switching cpus
-info: Entering event queue @ 2414934979500. Starting simulation...
+info: Entering event queue @ 2415632664000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2415934979500. Starting simulation...
+info: Entering event queue @ 2416632664000. Starting simulation...
switching cpus
-info: Entering event queue @ 2415935114000. Starting simulation...
+info: Entering event queue @ 2416632740000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2416935114000. Starting simulation...
+info: Entering event queue @ 2417632740000. Starting simulation...
switching cpus
-info: Entering event queue @ 2416935271000. Starting simulation...
+info: Entering event queue @ 2417632859000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2417935271000. Starting simulation...
+info: Entering event queue @ 2418632859000. Starting simulation...
switching cpus
-info: Entering event queue @ 2417935390000. Starting simulation...
+info: Entering event queue @ 2418633034000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2418935390000. Starting simulation...
+info: Entering event queue @ 2419633034000. Starting simulation...
switching cpus
-info: Entering event queue @ 2418935494000. Starting simulation...
+info: Entering event queue @ 2419633059000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2419935494000. Starting simulation...
+info: Entering event queue @ 2420633059000. Starting simulation...
switching cpus
-info: Entering event queue @ 2419935577000. Starting simulation...
+info: Entering event queue @ 2420633160000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2420935577000. Starting simulation...
+info: Entering event queue @ 2421633160000. Starting simulation...
switching cpus
-info: Entering event queue @ 2420935690500. Starting simulation...
+info: Entering event queue @ 2421633208000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2421935690500. Starting simulation...
+info: Entering event queue @ 2422633208000. Starting simulation...
switching cpus
-info: Entering event queue @ 2421935710000. Starting simulation...
+info: Entering event queue @ 2422633239000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2422935710000. Starting simulation...
+info: Entering event queue @ 2423633239000. Starting simulation...
switching cpus
-info: Entering event queue @ 2422935747000. Starting simulation...
+info: Entering event queue @ 2423633384000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2423935747000. Starting simulation...
+info: Entering event queue @ 2424633384000. Starting simulation...
switching cpus
-info: Entering event queue @ 2423935877000. Starting simulation...
+info: Entering event queue @ 2424633545000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2424935877000. Starting simulation...
+info: Entering event queue @ 2425633545000. Starting simulation...
switching cpus
-info: Entering event queue @ 2424936037000. Starting simulation...
+info: Entering event queue @ 2425633690000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2425936037000. Starting simulation...
+info: Entering event queue @ 2426633690000. Starting simulation...
switching cpus
-info: Entering event queue @ 2425936052000. Starting simulation...
+info: Entering event queue @ 2426641613000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2426936052000. Starting simulation...
+info: Entering event queue @ 2427641613000. Starting simulation...
switching cpus
-info: Entering event queue @ 2426943516000. Starting simulation...
+info: Entering event queue @ 2427641770000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2427943516000. Starting simulation...
+info: Entering event queue @ 2428641770000. Starting simulation...
switching cpus
-info: Entering event queue @ 2427943592000. Starting simulation...
+info: Entering event queue @ 2428641908500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2428943592000. Starting simulation...
+info: Entering event queue @ 2429641908500. Starting simulation...
switching cpus
-info: Entering event queue @ 2428943627000. Starting simulation...
+info: Entering event queue @ 2429641980500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2429943627000. Starting simulation...
+info: Entering event queue @ 2430641980500. Starting simulation...
switching cpus
-info: Entering event queue @ 2429943654000. Starting simulation...
+info: Entering event queue @ 2430642039000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2430943654000. Starting simulation...
+info: Entering event queue @ 2431642039000. Starting simulation...
switching cpus
-info: Entering event queue @ 2430943734000. Starting simulation...
+info: Entering event queue @ 2431645440000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2431943734000. Starting simulation...
+info: Entering event queue @ 2432645440000. Starting simulation...
switching cpus
-info: Entering event queue @ 2431947743000. Starting simulation...
+info: Entering event queue @ 2432645529000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2432947743000. Starting simulation...
+info: Entering event queue @ 2433645529000. Starting simulation...
switching cpus
-info: Entering event queue @ 2432947810000. Starting simulation...
+info: Entering event queue @ 2433645687500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2433947810000. Starting simulation...
+info: Entering event queue @ 2434645687500. Starting simulation...
switching cpus
-info: Entering event queue @ 2433947832500. Starting simulation...
+info: Entering event queue @ 2434645756000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2434947832500. Starting simulation...
+info: Entering event queue @ 2435645756000. Starting simulation...
switching cpus
-info: Entering event queue @ 2434947916000. Starting simulation...
+info: Entering event queue @ 2435645838500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2435947916000. Starting simulation...
+info: Entering event queue @ 2436645838500. Starting simulation...
+info: Entering event queue @ 2437366021000. Starting simulation...
switching cpus
-info: Entering event queue @ 2435948003500. Starting simulation...
+info: Entering event queue @ 2437366023000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2436948003500. Starting simulation...
-info: Entering event queue @ 2437668382000. Starting simulation...
+info: Entering event queue @ 2438366023000. Starting simulation...
switching cpus
-info: Entering event queue @ 2437668384000. Starting simulation...
+info: Entering event queue @ 2438371168000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2438668384000. Starting simulation...
+info: Entering event queue @ 2439371168000. Starting simulation...
switching cpus
-info: Entering event queue @ 2438673856000. Starting simulation...
+info: Entering event queue @ 2439371194000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2439673856000. Starting simulation...
+info: Entering event queue @ 2440371194000. Starting simulation...
switching cpus
-info: Entering event queue @ 2439673903000. Starting simulation...
+info: Entering event queue @ 2440371226000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2440673903000. Starting simulation...
+info: Entering event queue @ 2441371226000. Starting simulation...
switching cpus
-info: Entering event queue @ 2440673981000. Starting simulation...
+info: Entering event queue @ 2441371358000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2441673981000. Starting simulation...
+info: Entering event queue @ 2442371358000. Starting simulation...
switching cpus
-info: Entering event queue @ 2441674104000. Starting simulation...
+info: Entering event queue @ 2442371517000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2442674104000. Starting simulation...
+info: Entering event queue @ 2443371517000. Starting simulation...
switching cpus
-info: Entering event queue @ 2442674129000. Starting simulation...
+info: Entering event queue @ 2443380978000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2443674129000. Starting simulation...
+info: Entering event queue @ 2444380978000. Starting simulation...
switching cpus
-info: Entering event queue @ 2443683664000. Starting simulation...
+info: Entering event queue @ 2444381084000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2444683664000. Starting simulation...
+info: Entering event queue @ 2445381084000. Starting simulation...
switching cpus
-info: Entering event queue @ 2444683754000. Starting simulation...
+info: Entering event queue @ 2445381144000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2445683754000. Starting simulation...
+info: Entering event queue @ 2446381144000. Starting simulation...
switching cpus
-info: Entering event queue @ 2445683860000. Starting simulation...
+info: Entering event queue @ 2446383015000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2446683860000. Starting simulation...
+info: Entering event queue @ 2447383015000. Starting simulation...
switching cpus
-info: Entering event queue @ 2446685588000. Starting simulation...
+info: Entering event queue @ 2447383090000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2447685588000. Starting simulation...
+info: Entering event queue @ 2448383090000. Starting simulation...
switching cpus
-info: Entering event queue @ 2447685601000. Starting simulation...
+info: Entering event queue @ 2448383163000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2448685601000. Starting simulation...
+info: Entering event queue @ 2449383163000. Starting simulation...
switching cpus
-info: Entering event queue @ 2448685693000. Starting simulation...
+info: Entering event queue @ 2449383307000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2449685693000. Starting simulation...
+info: Entering event queue @ 2450383307000. Starting simulation...
switching cpus
-info: Entering event queue @ 2449685842000. Starting simulation...
+info: Entering event queue @ 2450383397000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2450685842000. Starting simulation...
+info: Entering event queue @ 2451383397000. Starting simulation...
switching cpus
-info: Entering event queue @ 2450685955000. Starting simulation...
+info: Entering event queue @ 2451383538000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2451685955000. Starting simulation...
+info: Entering event queue @ 2452383538000. Starting simulation...
switching cpus
-info: Entering event queue @ 2451686091000. Starting simulation...
+info: Entering event queue @ 2452383697000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2452686091000. Starting simulation...
+info: Entering event queue @ 2453383697000. Starting simulation...
switching cpus
-info: Entering event queue @ 2452686250000. Starting simulation...
+info: Entering event queue @ 2453383787000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2453686250000. Starting simulation...
+info: Entering event queue @ 2454383787000. Starting simulation...
switching cpus
-info: Entering event queue @ 2453686372000. Starting simulation...
+info: Entering event queue @ 2454383902500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2454686372000. Starting simulation...
+info: Entering event queue @ 2455383902500. Starting simulation...
switching cpus
-info: Entering event queue @ 2454686459500. Starting simulation...
+info: Entering event queue @ 2455384008500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2455686459500. Starting simulation...
+info: Entering event queue @ 2456384008500. Starting simulation...
switching cpus
-info: Entering event queue @ 2455686603500. Starting simulation...
+info: Entering event queue @ 2456384150000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2456686603500. Starting simulation...
+info: Entering event queue @ 2457384150000. Starting simulation...
switching cpus
-info: Entering event queue @ 2456686628000. Starting simulation...
+info: Entering event queue @ 2457384245000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2457686628000. Starting simulation...
+info: Entering event queue @ 2458384245000. Starting simulation...
switching cpus
-info: Entering event queue @ 2457686754000. Starting simulation...
+info: Entering event queue @ 2458384323500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2458686754000. Starting simulation...
+info: Entering event queue @ 2459384323500. Starting simulation...
switching cpus
-info: Entering event queue @ 2458686874000. Starting simulation...
+info: Entering event queue @ 2459384411000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2459686874000. Starting simulation...
+info: Entering event queue @ 2460384411000. Starting simulation...
switching cpus
-info: Entering event queue @ 2459686985000. Starting simulation...
+info: Entering event queue @ 2460393475000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2460686985000. Starting simulation...
+info: Entering event queue @ 2461393475000. Starting simulation...
switching cpus
-info: Entering event queue @ 2460696452000. Starting simulation...
+info: Entering event queue @ 2461393549000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2461696452000. Starting simulation...
+info: Entering event queue @ 2462393549000. Starting simulation...
switching cpus
-info: Entering event queue @ 2461696525000. Starting simulation...
+info: Entering event queue @ 2462393584000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2462696525000. Starting simulation...
+info: Entering event queue @ 2463393584000. Starting simulation...
switching cpus
-info: Entering event queue @ 2462696666000. Starting simulation...
+info: Entering event queue @ 2463393618000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2463696666000. Starting simulation...
+info: Entering event queue @ 2464393618000. Starting simulation...
switching cpus
-info: Entering event queue @ 2463696803000. Starting simulation...
+info: Entering event queue @ 2464393740000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2464696803000. Starting simulation...
+info: Entering event queue @ 2465393740000. Starting simulation...
switching cpus
-info: Entering event queue @ 2464696917000. Starting simulation...
+info: Entering event queue @ 2465393843000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2465696917000. Starting simulation...
+info: Entering event queue @ 2466393843000. Starting simulation...
switching cpus
-info: Entering event queue @ 2465696991000. Starting simulation...
+info: Entering event queue @ 2466393993000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2466696991000. Starting simulation...
+info: Entering event queue @ 2467393993000. Starting simulation...
switching cpus
-info: Entering event queue @ 2466697129000. Starting simulation...
+info: Entering event queue @ 2467394007000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2467697129000. Starting simulation...
+info: Entering event queue @ 2468394007000. Starting simulation...
switching cpus
-info: Entering event queue @ 2467697268000. Starting simulation...
+info: Entering event queue @ 2468394131000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2468697268000. Starting simulation...
+info: Entering event queue @ 2469394131000. Starting simulation...
+info: Entering event queue @ 2470103845000. Starting simulation...
switching cpus
-info: Entering event queue @ 2468697299000. Starting simulation...
+info: Entering event queue @ 2470103847000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2469697299000. Starting simulation...
-info: Entering event queue @ 2470404073000. Starting simulation...
+info: Entering event queue @ 2471103847000. Starting simulation...
switching cpus
-info: Entering event queue @ 2470404075000. Starting simulation...
+info: Entering event queue @ 2471103944000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2471404075000. Starting simulation...
+info: Entering event queue @ 2472103944000. Starting simulation...
switching cpus
-info: Entering event queue @ 2471404234000. Starting simulation...
+info: Entering event queue @ 2472103960000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2472404234000. Starting simulation...
+info: Entering event queue @ 2473103960000. Starting simulation...
switching cpus
-info: Entering event queue @ 2472404348000. Starting simulation...
+info: Entering event queue @ 2473104036500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2473404348000. Starting simulation...
+info: Entering event queue @ 2474104036500. Starting simulation...
switching cpus
-info: Entering event queue @ 2473404470000. Starting simulation...
+info: Entering event queue @ 2474104223500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2474404470000. Starting simulation...
+info: Entering event queue @ 2475104223500. Starting simulation...
switching cpus
-info: Entering event queue @ 2474404541000. Starting simulation...
+info: Entering event queue @ 2475104380000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2475404541000. Starting simulation...
+info: Entering event queue @ 2476104380000. Starting simulation...
switching cpus
-info: Entering event queue @ 2475404619000. Starting simulation...
+info: Entering event queue @ 2476104409500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2476404619000. Starting simulation...
+info: Entering event queue @ 2477104409500. Starting simulation...
+info: Entering event queue @ 2477104413500. Starting simulation...
+info: Entering event queue @ 2477104421500. Starting simulation...
switching cpus
-info: Entering event queue @ 2476404761000. Starting simulation...
+info: Entering event queue @ 2477104426000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2477404761000. Starting simulation...
-info: Entering event queue @ 2477404786000. Starting simulation...
+info: Entering event queue @ 2478104426000. Starting simulation...
switching cpus
-info: Entering event queue @ 2477404817001. Starting simulation...
+info: Entering event queue @ 2478104963000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2478404817001. Starting simulation...
+info: Entering event queue @ 2479104963000. Starting simulation...
switching cpus
-info: Entering event queue @ 2478413072000. Starting simulation...
+info: Entering event queue @ 2479105061000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2479413072000. Starting simulation...
+info: Entering event queue @ 2480105061000. Starting simulation...
switching cpus
-info: Entering event queue @ 2479413078500. Starting simulation...
+info: Entering event queue @ 2480105119000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2480413078500. Starting simulation...
+info: Entering event queue @ 2481105119000. Starting simulation...
switching cpus
-info: Entering event queue @ 2480413215000. Starting simulation...
+info: Entering event queue @ 2481105221000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2481413215000. Starting simulation...
+info: Entering event queue @ 2482105221000. Starting simulation...
switching cpus
-info: Entering event queue @ 2481413366000. Starting simulation...
+info: Entering event queue @ 2482105269000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2482413366000. Starting simulation...
+info: Entering event queue @ 2483105269000. Starting simulation...
switching cpus
-info: Entering event queue @ 2482413479000. Starting simulation...
+info: Entering event queue @ 2483105409000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2483413479000. Starting simulation...
+info: Entering event queue @ 2484105409000. Starting simulation...
switching cpus
-info: Entering event queue @ 2483413611000. Starting simulation...
+info: Entering event queue @ 2484105474000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2484413611000. Starting simulation...
+info: Entering event queue @ 2485105474000. Starting simulation...
switching cpus
-info: Entering event queue @ 2484413694000. Starting simulation...
+info: Entering event queue @ 2485105631000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2485413694000. Starting simulation...
+info: Entering event queue @ 2486105631000. Starting simulation...
switching cpus
-info: Entering event queue @ 2485413825000. Starting simulation...
+info: Entering event queue @ 2486105717000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2486413825000. Starting simulation...
+info: Entering event queue @ 2487105717000. Starting simulation...
switching cpus
-info: Entering event queue @ 2486413864000. Starting simulation...
+info: Entering event queue @ 2487105777000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2487413864000. Starting simulation...
+info: Entering event queue @ 2488105777000. Starting simulation...
+info: Entering event queue @ 2488109208500. Starting simulation...
+info: Entering event queue @ 2488109213500. Starting simulation...
switching cpus
-info: Entering event queue @ 2487413989500. Starting simulation...
+info: Entering event queue @ 2488109218000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2488413989500. Starting simulation...
-info: Entering event queue @ 2488416129000. Starting simulation...
-info: Entering event queue @ 2488416134000. Starting simulation...
+info: Entering event queue @ 2489109218000. Starting simulation...
switching cpus
-info: Entering event queue @ 2488416138500. Starting simulation...
+info: Entering event queue @ 2489113875500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2489416138500. Starting simulation...
+info: Entering event queue @ 2490113875500. Starting simulation...
switching cpus
-info: Entering event queue @ 2489419771500. Starting simulation...
+info: Entering event queue @ 2490113878000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2490419771500. Starting simulation...
+info: Entering event queue @ 2491113878000. Starting simulation...
switching cpus
-info: Entering event queue @ 2490419777000. Starting simulation...
+info: Entering event queue @ 2491116979000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2491419777000. Starting simulation...
+info: Entering event queue @ 2492116979000. Starting simulation...
switching cpus
-info: Entering event queue @ 2491419813500. Starting simulation...
+info: Entering event queue @ 2492117002000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2492419813500. Starting simulation...
+info: Entering event queue @ 2493117002000. Starting simulation...
switching cpus
-info: Entering event queue @ 2492419840500. Starting simulation...
+info: Entering event queue @ 2493117162000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2493419840500. Starting simulation...
+info: Entering event queue @ 2494117162000. Starting simulation...
switching cpus
-info: Entering event queue @ 2493419949500. Starting simulation...
+info: Entering event queue @ 2494117254000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2494419949500. Starting simulation...
+info: Entering event queue @ 2495117254000. Starting simulation...
switching cpus
-info: Entering event queue @ 2494419968000. Starting simulation...
+info: Entering event queue @ 2495117340000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2495419968000. Starting simulation...
+info: Entering event queue @ 2496117340000. Starting simulation...
switching cpus
-info: Entering event queue @ 2495420066000. Starting simulation...
+info: Entering event queue @ 2496126635000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2496420066000. Starting simulation...
+info: Entering event queue @ 2497126635000. Starting simulation...
switching cpus
-info: Entering event queue @ 2496428599000. Starting simulation...
+info: Entering event queue @ 2497126690000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2497428599000. Starting simulation...
+info: Entering event queue @ 2498126690000. Starting simulation...
switching cpus
-info: Entering event queue @ 2497428730000. Starting simulation...
+info: Entering event queue @ 2498126787000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2498428730000. Starting simulation...
+info: Entering event queue @ 2499126787000. Starting simulation...
switching cpus
-info: Entering event queue @ 2498428793000. Starting simulation...
+info: Entering event queue @ 2499126938000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2499428793000. Starting simulation...
+info: Entering event queue @ 2500126938000. Starting simulation...
switching cpus
-info: Entering event queue @ 2499428883000. Starting simulation...
+info: Entering event queue @ 2500126982000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2500428883000. Starting simulation...
+info: Entering event queue @ 2501126982000. Starting simulation...
switching cpus
-info: Entering event queue @ 2500428926000. Starting simulation...
+info: Entering event queue @ 2501127036000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2501428926000. Starting simulation...
+info: Entering event queue @ 2502127036000. Starting simulation...
+info: Entering event queue @ 2502839680000. Starting simulation...
switching cpus
-info: Entering event queue @ 2501428958500. Starting simulation...
+info: Entering event queue @ 2502839682000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2502428958500. Starting simulation...
-info: Entering event queue @ 2503141891000. Starting simulation...
+info: Entering event queue @ 2503839682000. Starting simulation...
switching cpus
-info: Entering event queue @ 2503141893000. Starting simulation...
+info: Entering event queue @ 2503839688500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2504141893000. Starting simulation...
+info: Entering event queue @ 2504839688500. Starting simulation...
switching cpus
-info: Entering event queue @ 2504141911000. Starting simulation...
+info: Entering event queue @ 2504839737000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2505141911000. Starting simulation...
+info: Entering event queue @ 2505839737000. Starting simulation...
switching cpus
-info: Entering event queue @ 2505141987000. Starting simulation...
+info: Entering event queue @ 2505839779500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2506141987000. Starting simulation...
+info: Entering event queue @ 2506839779500. Starting simulation...
switching cpus
-info: Entering event queue @ 2506142106000. Starting simulation...
+info: Entering event queue @ 2506839943000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2507142106000. Starting simulation...
+info: Entering event queue @ 2507839943000. Starting simulation...
switching cpus
-info: Entering event queue @ 2507150640000. Starting simulation...
+info: Entering event queue @ 2507840084000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2508150640000. Starting simulation...
+info: Entering event queue @ 2508840084000. Starting simulation...
switching cpus
-info: Entering event queue @ 2508150650000. Starting simulation...
+info: Entering event queue @ 2508844290000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2509150650000. Starting simulation...
+info: Entering event queue @ 2509844290000. Starting simulation...
switching cpus
-info: Entering event queue @ 2509159425000. Starting simulation...
+info: Entering event queue @ 2509844368000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2510159425000. Starting simulation...
+info: Entering event queue @ 2510844368000. Starting simulation...
switching cpus
-info: Entering event queue @ 2510159522000. Starting simulation...
+info: Entering event queue @ 2510844455000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2511159522000. Starting simulation...
+info: Entering event queue @ 2511844455000. Starting simulation...
switching cpus
-info: Entering event queue @ 2511159638000. Starting simulation...
+info: Entering event queue @ 2511844611000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2512159638000. Starting simulation...
+info: Entering event queue @ 2512844611000. Starting simulation...
switching cpus
-info: Entering event queue @ 2512159774000. Starting simulation...
+info: Entering event queue @ 2512844690000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2513159774000. Starting simulation...
+info: Entering event queue @ 2513844690000. Starting simulation...
switching cpus
-info: Entering event queue @ 2513159867000. Starting simulation...
+info: Entering event queue @ 2513853962000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2514159867000. Starting simulation...
+info: Entering event queue @ 2514853962000. Starting simulation...
switching cpus
-info: Entering event queue @ 2514169302000. Starting simulation...
+info: Entering event queue @ 2514854068000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2515169302000. Starting simulation...
+info: Entering event queue @ 2515854068000. Starting simulation...
switching cpus
-info: Entering event queue @ 2515169394000. Starting simulation...
+info: Entering event queue @ 2515854102000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2516169394000. Starting simulation...
+info: Entering event queue @ 2516854102000. Starting simulation...
switching cpus
-info: Entering event queue @ 2516169545000. Starting simulation...
+info: Entering event queue @ 2516855790000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2517169545000. Starting simulation...
+info: Entering event queue @ 2517855790000. Starting simulation...
switching cpus
-info: Entering event queue @ 2517178449000. Starting simulation...
+info: Entering event queue @ 2517855884500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2518178449000. Starting simulation...
+info: Entering event queue @ 2518855884500. Starting simulation...
+info: Entering event queue @ 2518859439500. Starting simulation...
+info: Entering event queue @ 2518859449000. Starting simulation...
+info: Entering event queue @ 2518859453500. Starting simulation...
switching cpus
-info: Entering event queue @ 2518178548000. Starting simulation...
+info: Entering event queue @ 2518859454500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2519178548000. Starting simulation...
-info: Entering event queue @ 2519180509500. Starting simulation...
-info: Entering event queue @ 2519180519000. Starting simulation...
-info: Entering event queue @ 2519180523500. Starting simulation...
+info: Entering event queue @ 2519859454500. Starting simulation...
switching cpus
-info: Entering event queue @ 2519180524500. Starting simulation...
+info: Entering event queue @ 2519859612000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2520180524500. Starting simulation...
+info: Entering event queue @ 2520859612000. Starting simulation...
switching cpus
-info: Entering event queue @ 2520180668000. Starting simulation...
+info: Entering event queue @ 2520859743000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2521180668000. Starting simulation...
+info: Entering event queue @ 2521859743000. Starting simulation...
switching cpus
-info: Entering event queue @ 2521180817000. Starting simulation...
+info: Entering event queue @ 2521859796000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2522180817000. Starting simulation...
+info: Entering event queue @ 2522859796000. Starting simulation...
switching cpus
-info: Entering event queue @ 2522180935500. Starting simulation...
+info: Entering event queue @ 2522859820000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2523180935500. Starting simulation...
+info: Entering event queue @ 2523859820000. Starting simulation...
switching cpus
-info: Entering event queue @ 2523180954000. Starting simulation...
+info: Entering event queue @ 2523859876000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2524180954000. Starting simulation...
+info: Entering event queue @ 2524859876000. Starting simulation...
switching cpus
-info: Entering event queue @ 2524181013000. Starting simulation...
+info: Entering event queue @ 2524859972500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2525181013000. Starting simulation...
+info: Entering event queue @ 2525859972500. Starting simulation...
switching cpus
-info: Entering event queue @ 2525181146000. Starting simulation...
+info: Entering event queue @ 2525859990000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2526181146000. Starting simulation...
-info: Entering event queue @ 2526181160000. Starting simulation...
+info: Entering event queue @ 2526859990000. Starting simulation...
switching cpus
-info: Entering event queue @ 2526181162500. Starting simulation...
+info: Entering event queue @ 2526860000500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2527181162500. Starting simulation...
-info: Entering event queue @ 2527181171500. Starting simulation...
+info: Entering event queue @ 2527860000500. Starting simulation...
switching cpus
-info: Entering event queue @ 2527181177000. Starting simulation...
+info: Entering event queue @ 2527860004000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2528181177000. Starting simulation...
+info: Entering event queue @ 2528860004000. Starting simulation...
switching cpus
-info: Entering event queue @ 2528181181000. Starting simulation...
+info: Entering event queue @ 2528860008500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2529181181000. Starting simulation...
+info: Entering event queue @ 2529860008500. Starting simulation...
switching cpus
-info: Entering event queue @ 2529181185500. Starting simulation...
+info: Entering event queue @ 2529860052000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2530181185500. Starting simulation...
+info: Entering event queue @ 2530860052000. Starting simulation...
switching cpus
-info: Entering event queue @ 2530181301000. Starting simulation...
+info: Entering event queue @ 2530860057000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2531181301000. Starting simulation...
+info: Entering event queue @ 2531860057000. Starting simulation...
switching cpus
-info: Entering event queue @ 2531181304500. Starting simulation...
+info: Entering event queue @ 2531860059000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2532181304500. Starting simulation...
+info: Entering event queue @ 2532860059000. Starting simulation...
switching cpus
-info: Entering event queue @ 2532181308000. Starting simulation...
+info: Entering event queue @ 2532860067500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2533181308000. Starting simulation...
-info: Entering event queue @ 2533181317000. Starting simulation...
-info: Entering event queue @ 2533181327000. Starting simulation...
-info: Entering event queue @ 2533181337500. Starting simulation...
+info: Entering event queue @ 2533860067500. Starting simulation...
switching cpus
-info: Entering event queue @ 2533181338000. Starting simulation...
+info: Entering event queue @ 2533860795000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2534181338000. Starting simulation...
+info: Entering event queue @ 2534860795000. Starting simulation...
+info: Entering event queue @ 2535576589000. Starting simulation...
switching cpus
-info: Entering event queue @ 2534181592000. Starting simulation...
+info: Entering event queue @ 2535576591000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2535181592000. Starting simulation...
-info: Entering event queue @ 2535877726000. Starting simulation...
+info: Entering event queue @ 2536576591000. Starting simulation...
switching cpus
-info: Entering event queue @ 2535877728000. Starting simulation...
+info: Entering event queue @ 2536576653000. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2536877728000. Starting simulation...
+info: Entering event queue @ 2537576653000. Starting simulation...
switching cpus
-info: Entering event queue @ 2536877880500. Starting simulation...
+info: Entering event queue @ 2537576734500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2537877880500. Starting simulation...
+info: Entering event queue @ 2538576734500. Starting simulation...
+info: Entering event queue @ 2538576753000. Starting simulation...
switching cpus
-info: Entering event queue @ 2537877967000. Starting simulation...
+info: Entering event queue @ 2538576817500. Starting simulation...
Switching CPUs...
Next CPU: DerivO3CPU
-info: Entering event queue @ 2538877967000. Starting simulation...
+info: Entering event queue @ 2539576817500. Starting simulation...
+info: Entering event queue @ 2539576829500. Starting simulation...
switching cpus
-info: Entering event queue @ 2538877971000. Starting simulation...
-Switching CPUs...
-Next CPU: DerivO3CPU
-info: Entering event queue @ 2539877971000. Starting simulation...
-info: Entering event queue @ 2539877977500. Starting simulation...
-switching cpus
-info: Entering event queue @ 2539877982000. Starting simulation...
+info: Entering event queue @ 2539576834000. Starting simulation...
sim_ticks 2540275734000 # Number of ticks simulated
final_tick 2540275734000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 63914 # Simulator instruction rate (inst/s)
-host_op_rate 82240 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2691970222 # Simulator tick rate (ticks/s)
-host_mem_usage 413060 # Number of bytes of host memory used
-host_seconds 943.65 # Real time elapsed on the host
+host_inst_rate 50621 # Simulator instruction rate (inst/s)
+host_op_rate 65136 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2132095179 # Simulator tick rate (ticks/s)
+host_mem_usage 455960 # Number of bytes of host memory used
+host_seconds 1191.45 # Real time elapsed on the host
sim_insts 60312498 # Number of instructions simulated
sim_ops 77605759 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
+system.cpu0.branchPred.lookups 6894641 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 5490275 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 340467 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 4496048 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 3641169 # Number of BTB hits
+system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.branchPred.BTBHitPct 80.985990 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 672237 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 35025 # Number of incorrect RAS predictions.
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 25321176 # DTB read hits
system.cpu0.numCycles 232916834 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 6894641 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 5490275 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 340467 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 4496048 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 3641169 # Number of BTB hits
-system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 672237 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 35025 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 14144008 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 42774388 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 6894641 # Number of branches that fetch encountered
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.branchPred.lookups 7461261 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 5924878 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 387688 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 4864845 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 3916001 # Number of BTB hits
+system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.branchPred.BTBHitPct 80.495905 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 732677 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 39651 # Number of incorrect RAS predictions.
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 25842433 # DTB read hits
system.cpu1.numCycles 238328292 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 7461261 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 5924878 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 387688 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 4864845 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 3916001 # Number of BTB hits
-system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 732677 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 39651 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 15658024 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 45723743 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 7461261 # Number of branches that fetch encountered
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
-panic_on_oops=true
-panic_on_panic=true
readfile=tests/halt.sh
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
-image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
[system.cpu1]
type=TimingSimpleCPU
children=dtb interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 11 2012 16:28:23
-gem5 started Dec 11 2012 16:28:35
-gem5 executing on e103721-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 22:22:22
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Switching CPUs...
sim_ticks 2609476867000 # Number of ticks simulated
final_tick 2609476867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 293996 # Simulator instruction rate (inst/s)
-host_op_rate 374108 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 12742678359 # Simulator tick rate (ticks/s)
-host_mem_usage 397908 # Number of bytes of host memory used
-host_seconds 204.78 # Real time elapsed on the host
+host_inst_rate 397155 # Simulator instruction rate (inst/s)
+host_op_rate 505377 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17213891867 # Simulator tick rate (ticks/s)
+host_mem_usage 448796 # Number of bytes of host memory used
+host_seconds 151.59 # Real time elapsed on the host
sim_insts 60205243 # Number of instructions simulated
sim_ops 76610733 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
mem_ranges=0:134217727
[system.cpu]
type=DerivO3CPU
-children=dcache dtb dtb_walker_cache fuPool icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb dtb_walker_cache fuPool icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
+Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:20:54
-gem5 started Jan 4 2013 23:13:25
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 19:14:30
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5136797077000 because m5_exit instruction encountered
+Exiting @ tick 5136817990000 because m5_exit instruction encountered
sim_ticks 5136817990000 # Number of ticks simulated
final_tick 5136817990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 178524 # Simulator instruction rate (inst/s)
-host_op_rate 352888 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2247974016 # Simulator tick rate (ticks/s)
-host_mem_usage 798352 # Number of bytes of host memory used
-host_seconds 2285.09 # Real time elapsed on the host
+host_inst_rate 121455 # Simulator instruction rate (inst/s)
+host_op_rate 240079 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1529355788 # Simulator tick rate (ticks/s)
+host_mem_usage 804152 # Number of bytes of host memory used
+host_seconds 3358.81 # Real time elapsed on the host
sim_insts 407944006 # Number of instructions simulated
sim_ops 806380994 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2472512 # Number of bytes read from this memory
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
+system.cpu.branchPred.lookups 86252881 # Number of BP lookups
+system.cpu.branchPred.condPredicted 86252881 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1115345 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 81384938 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 79240101 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 97.364577 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.numCycles 447901761 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 86252881 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 86252881 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1115345 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 81384938 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 79240101 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 27570299 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 426189548 # Number of instructions fetch has processed
system.cpu.fetch.Branches 86252881 # Number of branches that fetch encountered
Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1\r
Initializing CPU#0\r
PID hash table entries: 512 (order: 9, 4096 bytes)\r
-time.c: Detected 2000.001 MHz processor.\r
+time.c: Detected 2000.008 MHz processor.\r
Console: colour dummy device 80x25\r
console handover: boot [earlyser0] -> real [ttyS0]\r
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)\r
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]\r
ACPI: Unable to load the System Description Tables\r
Using local APIC timer interrupts.\r
-result 7812531\r
+result 7812557\r
Detected 7.812 MHz APIC timer.\r
NET: Registered protocol family 16\r
PCI: Using configuration type 1\r
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 11:21:21
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:19:12
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 269661304500 # Number of ticks simulated
final_tick 269661304500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 125304 # Simulator instruction rate (inst/s)
-host_op_rate 125304 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 56142087 # Simulator tick rate (ticks/s)
-host_mem_usage 214336 # Number of bytes of host memory used
-host_seconds 4803.19 # Real time elapsed on the host
+host_inst_rate 98682 # Simulator instruction rate (inst/s)
+host_op_rate 98682 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44214559 # Simulator tick rate (ticks/s)
+host_mem_usage 273520 # Number of bytes of host memory used
+host_seconds 6098.93 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 53824 # Number of bytes read from this memory
system.physmem.readRowHitRate 66.23 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 5.03 # Row buffer hit rate for writes
system.physmem.avgGap 9874807.84 # Average gap between requests
+system.cpu.branchPred.lookups 86405274 # Number of BP lookups
+system.cpu.branchPred.condPredicted 81476244 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 36343014 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 44773910 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 34660000 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 77.411153 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1197609 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 539322610 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 86405274 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 81476244 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 36343014 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 44773910 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 34660000 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 1197609 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 77.411153 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 37224652 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 49180622 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 541063714 # Number of Reads from Int. Register File
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 11:21:56
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:43:44
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 133778696500 # Number of ticks simulated
final_tick 133778696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 208111 # Simulator instruction rate (inst/s)
-host_op_rate 208111 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 49227708 # Simulator tick rate (ticks/s)
-host_mem_usage 215496 # Number of bytes of host memory used
-host_seconds 2717.55 # Real time elapsed on the host
+host_inst_rate 160169 # Simulator instruction rate (inst/s)
+host_op_rate 160169 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37887208 # Simulator tick rate (ticks/s)
+host_mem_usage 273648 # Number of bytes of host memory used
+host_seconds 3530.97 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
sim_ops 565552443 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 60864 # Number of bytes read from this memory
system.physmem.readRowHitRate 68.08 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 5.06 # Row buffer hit rate for writes
system.physmem.avgGap 4852854.06 # Average gap between requests
+system.cpu.branchPred.lookups 76440222 # Number of BP lookups
+system.cpu.branchPred.condPredicted 70864810 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2706098 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 43060392 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 41933015 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 97.381870 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1604413 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 267557394 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 76440222 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 70864810 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 2706098 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 43060392 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 41933015 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1604413 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 67119409 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 699052842 # Number of instructions fetch has processed
system.cpu.fetch.Branches 76440222 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 14:03:38
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:29:25
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 300930958000 # Number of ticks simulated
final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3871430 # Simulator instruction rate (inst/s)
-host_op_rate 3871429 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1935730316 # Simulator tick rate (ticks/s)
-host_mem_usage 206040 # Number of bytes of host memory used
-host_seconds 155.46 # Real time elapsed on the host
+host_inst_rate 2641824 # Simulator instruction rate (inst/s)
+host_op_rate 2641824 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1320922836 # Simulator tick rate (ticks/s)
+host_mem_usage 264040 # Number of bytes of host memory used
+host_seconds 227.82 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2407447588 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:30:56
-gem5 started Jul 2 2012 09:11:02
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:50:54
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 764109115000 because target called exit()
+Exiting @ tick 762403375000 because target called exit()
sim_ticks 762403375000 # Number of ticks simulated
final_tick 762403375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2059312 # Simulator instruction rate (inst/s)
-host_op_rate 2059312 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2608636387 # Simulator tick rate (ticks/s)
-host_mem_usage 217100 # Number of bytes of host memory used
-host_seconds 292.26 # Real time elapsed on the host
+host_inst_rate 1151537 # Simulator instruction rate (inst/s)
+host_op_rate 1151537 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1458711281 # Simulator tick rate (ticks/s)
+host_mem_usage 272496 # Number of bytes of host memory used
+host_seconds 522.66 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52367.295597 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52367.295597 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 451299 # number of replacements
-system.cpu.dcache.tagsinuse 4094.203488 # Cycle average of tags in use
-system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 563363000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4094.203488 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999561 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999561 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 39197158 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 153509968 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 153509968 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 153509968 # number of overall hits
-system.cpu.dcache.overall_hits::total 153509968 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 201232 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 201232 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 254163 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 254163 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 455395 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses
-system.cpu.dcache.overall_misses::total 455395 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789356000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 2789356000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4199727000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4199727000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 6989083000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 6989083000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 6989083000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 6989083000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.001757 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.006442 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13861.393814 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13861.393814 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16523.754441 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 16523.754441 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15347.298499 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15347.298499 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
-system.cpu.dcache.writebacks::total 436887 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386892000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386892000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3691401000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3691401000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078293000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6078293000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078293000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6078293000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11861.393814 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11861.393814 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14523.754441 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14523.754441 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1028 # number of replacements
system.cpu.l2cache.tagsinuse 22854.086849 # Cycle average of tags in use
system.cpu.l2cache.total_refs 531883 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.235747 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.266829 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 451299 # number of replacements
+system.cpu.dcache.tagsinuse 4094.203488 # Cycle average of tags in use
+system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 563363000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4094.203488 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999561 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999561 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 114312810 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 114312810 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 39197158 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 39197158 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 153509968 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 153509968 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 153509968 # number of overall hits
+system.cpu.dcache.overall_hits::total 153509968 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 201232 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 201232 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 254163 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 254163 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 455395 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 455395 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 455395 # number of overall misses
+system.cpu.dcache.overall_misses::total 455395 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 2789356000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 2789356000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4199727000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4199727000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 6989083000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 6989083000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 6989083000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 6989083000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 114514042 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 114514042 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 39451321 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 39451321 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 153965363 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 153965363 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 153965363 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 153965363 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001757 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.001757 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006442 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.006442 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002958 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002958 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13861.393814 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13861.393814 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16523.754441 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 16523.754441 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15347.298499 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15347.298499 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15347.298499 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 436887 # number of writebacks
+system.cpu.dcache.writebacks::total 436887 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 201232 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 201232 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 254163 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 254163 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 455395 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 455395 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 455395 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 455395 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2386892000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2386892000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3691401000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3691401000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6078293000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6078293000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6078293000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6078293000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001757 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001757 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006442 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11861.393814 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11861.393814 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14523.754441 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14523.754441 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13347.298499 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13347.298499 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/arm/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 4 2013 23:34:09
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:48:55
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 164568389500 because target called exit()
+Exiting @ tick 164543008000 because target called exit()
sim_ticks 164543008000 # Number of ticks simulated
final_tick 164543008000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 153982 # Simulator instruction rate (inst/s)
-host_op_rate 162709 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44446364 # Simulator tick rate (ticks/s)
-host_mem_usage 244392 # Number of bytes of host memory used
-host_seconds 3702.06 # Real time elapsed on the host
+host_inst_rate 116480 # Simulator instruction rate (inst/s)
+host_op_rate 123082 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33621508 # Simulator tick rate (ticks/s)
+host_mem_usage 289348 # Number of bytes of host memory used
+host_seconds 4893.98 # Real time elapsed on the host
sim_insts 570051585 # Number of instructions simulated
sim_ops 602359791 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46912 # Number of bytes read from this memory
system.physmem.readRowHitRate 64.99 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 43.15 # Row buffer hit rate for writes
system.physmem.avgGap 5511958.73 # Average gap between requests
+system.cpu.branchPred.lookups 85130885 # Number of BP lookups
+system.cpu.branchPred.condPredicted 79914937 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2339051 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 47115734 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 46860934 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 99.459204 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1427305 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 879 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.numCycles 329086017 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 85130885 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 79914937 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 2339051 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 47115734 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 46860934 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1427305 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 879 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 68482650 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 666733796 # Number of instructions fetch has processed
system.cpu.fetch.Branches 85130885 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:41:05
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:49:37
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 301191365000 # Number of ticks simulated
final_tick 301191365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2514683 # Simulator instruction rate (inst/s)
-host_op_rate 2657205 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1328652667 # Simulator tick rate (ticks/s)
-host_mem_usage 218896 # Number of bytes of host memory used
-host_seconds 226.69 # Real time elapsed on the host
+host_inst_rate 1714897 # Simulator instruction rate (inst/s)
+host_op_rate 1812090 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 906079333 # Simulator tick rate (ticks/s)
+host_mem_usage 278712 # Number of bytes of host memory used
+host_seconds 332.41 # Real time elapsed on the host
sim_insts 570051636 # Number of instructions simulated
sim_ops 602359842 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2280298100 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:37:42
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:54:17
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 795270546000 because target called exit()
+Exiting @ tick 793670137000 because target called exit()
sim_ticks 793670137000 # Number of ticks simulated
final_tick 793670137000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 897110 # Simulator instruction rate (inst/s)
-host_op_rate 947381 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1252348386 # Simulator tick rate (ticks/s)
-host_mem_usage 231392 # Number of bytes of host memory used
-host_seconds 633.75 # Real time elapsed on the host
+host_inst_rate 904187 # Simulator instruction rate (inst/s)
+host_op_rate 954854 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1262227313 # Simulator tick rate (ticks/s)
+host_mem_usage 287296 # Number of bytes of host memory used
+host_seconds 628.79 # Real time elapsed on the host
sim_insts 568539335 # Number of instructions simulated
sim_ops 600398272 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 38592 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50387.247278 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50387.247278 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 433468 # number of replacements
-system.cpu.dcache.tagsinuse 4094.241219 # Cycle average of tags in use
-system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 529622000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4094.241219 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 216771818 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 216771818 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 216771818 # number of overall hits
-system.cpu.dcache.overall_hits::total 216771818 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
-system.cpu.dcache.overall_misses::total 437564 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 2650304000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 2650304000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4137794000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4137794000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 6788098000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 6788098000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 6788098000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 6788098000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 217209382 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 217209382 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 217209382 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 217209382 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13962.489990 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13962.489990 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16701.624231 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 16701.624231 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15513.383185 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15513.383185 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 418626 # number of writebacks
-system.cpu.dcache.writebacks::total 418626 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2270672000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2270672000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3642298000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3642298000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5912970000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 5912970000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5912970000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 5912970000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11962.489990 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11962.489990 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14701.624231 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14701.624231 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2512 # number of replacements
system.cpu.l2cache.tagsinuse 22024.775302 # Cycle average of tags in use
system.cpu.l2cache.total_refs 506990 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40019.103656 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40018.673439 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 433468 # number of replacements
+system.cpu.dcache.tagsinuse 4094.241219 # Cycle average of tags in use
+system.cpu.dcache.total_refs 216774472 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 495.412036 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 529622000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4094.241219 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999571 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999571 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 147602035 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 147602035 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 69169783 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 69169783 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 1327 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 1327 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 1327 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 1327 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 216771818 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 216771818 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 216771818 # number of overall hits
+system.cpu.dcache.overall_hits::total 216771818 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 189816 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 189816 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 247748 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 247748 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 437564 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 437564 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 437564 # number of overall misses
+system.cpu.dcache.overall_misses::total 437564 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 2650304000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 2650304000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4137794000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4137794000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 6788098000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 6788098000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 6788098000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 6788098000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 147791851 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 147791851 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 69417531 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 69417531 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1327 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 1327 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 1327 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 1327 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 217209382 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 217209382 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 217209382 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 217209382 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001284 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.001284 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003569 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.003569 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002014 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.002014 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002014 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.002014 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13962.489990 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13962.489990 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16701.624231 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 16701.624231 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15513.383185 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15513.383185 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15513.383185 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 418626 # number of writebacks
+system.cpu.dcache.writebacks::total 418626 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 189816 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 189816 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 247748 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 247748 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 437564 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 437564 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2270672000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2270672000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3642298000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3642298000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5912970000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 5912970000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5912970000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 5912970000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001284 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003569 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002014 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002014 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11962.489990 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11962.489990 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14701.624231 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14701.624231 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13513.383185 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13513.383185 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/sparc/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:16:54
-gem5 started Jan 4 2013 22:00:02
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 15:52:06
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 387279743500 # Number of ticks simulated
final_tick 387279743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 70741 # Simulator instruction rate (inst/s)
-host_op_rate 70964 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 19552386 # Simulator tick rate (ticks/s)
-host_mem_usage 225936 # Number of bytes of host memory used
-host_seconds 19807.29 # Real time elapsed on the host
+host_inst_rate 131929 # Simulator instruction rate (inst/s)
+host_op_rate 132344 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 36464205 # Simulator tick rate (ticks/s)
+host_mem_usage 283820 # Number of bytes of host memory used
+host_seconds 10620.82 # Real time elapsed on the host
sim_insts 1401188945 # Number of instructions simulated
sim_ops 1405604139 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 76416 # Number of bytes read from this memory
system.physmem.readRowHitRate 66.83 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 43.35 # Row buffer hit rate for writes
system.physmem.avgGap 12929580.19 # Average gap between requests
+system.cpu.branchPred.lookups 97757265 # Number of BP lookups
+system.cpu.branchPred.condPredicted 88048400 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 3615880 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 65812942 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 65493412 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 99.514488 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1346 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 219 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 49 # Number of system calls
system.cpu.numCycles 774559488 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 97757265 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 88048400 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 3615880 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 65812942 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 65493412 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1346 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 219 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 164857001 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1642241879 # Number of instructions fetch has processed
system.cpu.fetch.Branches 97757265 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:13:47
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:12:25
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 744764112500 # Number of ticks simulated
final_tick 744764112500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3155762 # Simulator instruction rate (inst/s)
-host_op_rate 3165144 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1582576951 # Simulator tick rate (ticks/s)
-host_mem_usage 222108 # Number of bytes of host memory used
-host_seconds 470.60 # Real time elapsed on the host
+host_inst_rate 2243211 # Simulator instruction rate (inst/s)
+host_op_rate 2249879 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1124943447 # Simulator tick rate (ticks/s)
+host_mem_usage 273192 # Number of bytes of host memory used
+host_seconds 662.05 # Real time elapsed on the host
sim_insts 1485108088 # Number of instructions simulated
sim_ops 1489523282 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 5940451992 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:13:49
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 15:49:34
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2063177737000 because target called exit()
+Exiting @ tick 2061066313000 because target called exit()
sim_ticks 2061066313000 # Number of ticks simulated
final_tick 2061066313000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 632829 # Simulator instruction rate (inst/s)
-host_op_rate 634711 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 878254717 # Simulator tick rate (ticks/s)
-host_mem_usage 225052 # Number of bytes of host memory used
-host_seconds 2346.78 # Real time elapsed on the host
+host_inst_rate 1083437 # Simulator instruction rate (inst/s)
+host_op_rate 1086658 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1503618533 # Simulator tick rate (ticks/s)
+host_mem_usage 281644 # Number of bytes of host memory used
+host_seconds 1370.74 # Real time elapsed on the host
sim_insts 1485108088 # Number of instructions simulated
sim_ops 1489523282 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49670.280036 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 49670.280036 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 449125 # number of replacements
-system.cpu.dcache.tagsinuse 4095.236014 # Cycle average of tags in use
-system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 559340000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4095.236014 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999813 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999813 # Average percentage of cache occupancy
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-system.cpu.dcache.ReadReq_hits::total 402319357 # number of ReadReq hits
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-system.cpu.dcache.WriteReq_hits::total 166587088 # number of WriteReq hits
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-system.cpu.dcache.SwapReq_hits::total 1319 # number of SwapReq hits
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-system.cpu.dcache.overall_hits::total 568906445 # number of overall hits
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-system.cpu.dcache.ReadReq_misses::total 193486 # number of ReadReq misses
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-system.cpu.dcache.overall_misses::total 453214 # number of overall misses
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-system.cpu.dcache.overall_miss_latency::total 6989326000 # number of overall miss cycles
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-system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 13927.757047 # average ReadReq miss latency
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.605433 # average WriteReq miss latency
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-system.cpu.dcache.SwapReq_avg_miss_latency::total 19000 # average SwapReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 15421.690416 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15421.690416 # average overall miss latency
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-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu.dcache.writebacks::writebacks 435341 # number of writebacks
-system.cpu.dcache.writebacks::total 435341 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082898000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6082898000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082898000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6082898000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses
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-system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
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-system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.605433 # average WriteReq mshr miss latency
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-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency
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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2539 # number of replacements
system.cpu.l2cache.tagsinuse 22253.549915 # Cycle average of tags in use
system.cpu.l2cache.total_refs 534785 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.368297 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 449125 # number of replacements
+system.cpu.dcache.tagsinuse 4095.236014 # Cycle average of tags in use
+system.cpu.dcache.total_refs 568907764 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 1255.254642 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 559340000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4095.236014 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999813 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999813 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 402319357 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 402319357 # number of ReadReq hits
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+system.cpu.dcache.overall_misses::total 453214 # number of overall misses
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+system.cpu.dcache.ReadReq_miss_latency::total 2694826000 # number of ReadReq miss cycles
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+system.cpu.dcache.overall_miss_latency::total 6989326000 # number of overall miss cycles
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+system.cpu.dcache.SwapReq_accesses::total 1326 # number of SwapReq accesses(hits+misses)
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+system.cpu.dcache.demand_miss_rate::total 0.000796 # miss rate for demand accesses
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+system.cpu.dcache.overall_miss_rate::total 0.000796 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13927.757047 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13927.757047 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16534.605433 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 16534.605433 # average WriteReq miss latency
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+system.cpu.dcache.SwapReq_avg_miss_latency::total 19000 # average SwapReq miss latency
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+system.cpu.dcache.demand_avg_miss_latency::total 15421.690416 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15421.690416 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15421.690416 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 435341 # number of writebacks
+system.cpu.dcache.writebacks::total 435341 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 193486 # number of ReadReq MSHR misses
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+system.cpu.dcache.WriteReq_mshr_misses::total 259728 # number of WriteReq MSHR misses
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+system.cpu.dcache.overall_mshr_misses::cpu.data 453214 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 453214 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2307854000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2307854000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3775044000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3775044000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 119000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total 119000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6082898000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6082898000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6082898000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6082898000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000481 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001557 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001557 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.005279 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000796 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000796 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000796 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11927.757047 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11927.757047 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14534.605433 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14534.605433 # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 17000 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 17000 # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13421.690416 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13421.690416 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/x86/linux/gzip
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:20:54
-gem5 started Jan 4 2013 22:11:32
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:48:34
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 607445544000 # Number of ticks simulated
final_tick 607445544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 35384 # Simulator instruction rate (inst/s)
-host_op_rate 65197 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 24424271 # Simulator tick rate (ticks/s)
-host_mem_usage 239876 # Number of bytes of host memory used
-host_seconds 24870.57 # Real time elapsed on the host
+host_inst_rate 56942 # Simulator instruction rate (inst/s)
+host_op_rate 104918 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 39304494 # Simulator tick rate (ticks/s)
+host_mem_usage 295872 # Number of bytes of host memory used
+host_seconds 15454.86 # Real time elapsed on the host
sim_insts 880025277 # Number of instructions simulated
sim_ops 1621493926 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 57728 # Number of bytes read from this memory
system.physmem.readRowHitRate 64.68 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 42.78 # Row buffer hit rate for writes
system.physmem.avgGap 20320661.36 # Average gap between requests
+system.cpu.branchPred.lookups 158385701 # Number of BP lookups
+system.cpu.branchPred.condPredicted 158385701 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 26390414 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 84292336 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 84079165 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 99.747105 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1214891089 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 158385701 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 158385701 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 26390414 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 84292336 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 84079165 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 179135725 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1458430747 # Number of instructions fetch has processed
system.cpu.fetch.Branches 158385701 # Number of branches that fetch encountered
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:35:29
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:52:14
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
sim_ticks 963992671500 # Number of ticks simulated
final_tick 963992671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 908989 # Simulator instruction rate (inst/s)
-host_op_rate 1674860 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 995719480 # Simulator tick rate (ticks/s)
-host_mem_usage 267620 # Number of bytes of host memory used
-host_seconds 968.14 # Real time elapsed on the host
+host_inst_rate 911190 # Simulator instruction rate (inst/s)
+host_op_rate 1678916 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 998130396 # Simulator tick rate (ticks/s)
+host_mem_usage 284224 # Number of bytes of host memory used
+host_seconds 965.80 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
sim_ops 1621493927 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 9492133560 # Number of bytes read from this memory
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:35:29
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:22:44
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
sim_ticks 1800193397000 # Number of ticks simulated
final_tick 1800193397000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 477976 # Simulator instruction rate (inst/s)
-host_op_rate 880696 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 977754272 # Simulator tick rate (ticks/s)
-host_mem_usage 276196 # Number of bytes of host memory used
-host_seconds 1841.15 # Real time elapsed on the host
+host_inst_rate 575805 # Simulator instruction rate (inst/s)
+host_op_rate 1060952 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1177876462 # Simulator tick rate (ticks/s)
+host_mem_usage 292800 # Number of bytes of host memory used
+host_seconds 1528.34 # Real time elapsed on the host
sim_insts 880025278 # Number of instructions simulated
sim_ops 1621493927 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 46208 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53002.770083 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53002.770083 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 437952 # number of replacements
-system.cpu.dcache.tagsinuse 4094.905742 # Cycle average of tags in use
-system.cpu.dcache.total_refs 606786131 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 1372.670233 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 771787000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4094.905742 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 187941336 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 187941336 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 606786131 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 606786131 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 606786131 # number of overall hits
-system.cpu.dcache.overall_hits::total 606786131 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 244722 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 442048 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses
-system.cpu.dcache.overall_misses::total 442048 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 2746552000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 2746552000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4105029000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4105029000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 6851581000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 6851581000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 6851581000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 607228179 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 607228179 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 607228179 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 607228179 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.001300 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13918.855093 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16774.254052 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 16774.254052 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15499.631262 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15499.631262 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 422980 # number of writebacks
-system.cpu.dcache.writebacks::total 422980 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 244722 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 442048 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615585000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615585000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967485000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 5967485000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967485000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 5967485000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14774.254052 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14774.254052 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2532 # number of replacements
system.cpu.l2cache.tagsinuse 22211.029327 # Cycle average of tags in use
system.cpu.l2cache.total_refs 519268 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40034.351581 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40033.507349 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 437952 # number of replacements
+system.cpu.dcache.tagsinuse 4094.905742 # Cycle average of tags in use
+system.cpu.dcache.total_refs 606786131 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 1372.670233 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 771787000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4094.905742 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999733 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999733 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 418844795 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 418844795 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 187941336 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 187941336 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 606786131 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 606786131 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 606786131 # number of overall hits
+system.cpu.dcache.overall_hits::total 606786131 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 197326 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 197326 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 244722 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 244722 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 442048 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 442048 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 442048 # number of overall misses
+system.cpu.dcache.overall_misses::total 442048 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 2746552000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 2746552000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4105029000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4105029000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 6851581000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 6851581000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 6851581000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 6851581000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 419042121 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 419042121 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 188186058 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 188186058 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 607228179 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 607228179 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 607228179 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 607228179 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000471 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000471 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001300 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.001300 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000728 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000728 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000728 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000728 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13918.855093 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13918.855093 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 16774.254052 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 16774.254052 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15499.631262 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15499.631262 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15499.631262 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 422980 # number of writebacks
+system.cpu.dcache.writebacks::total 422980 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197326 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 197326 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 244722 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 244722 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 442048 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 442048 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 442048 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 442048 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2351900000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2351900000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3615585000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3615585000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5967485000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 5967485000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5967485000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 5967485000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000471 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.001300 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000728 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000728 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11918.855093 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11918.855093 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14774.254052 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14774.254052 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13499.631262 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 13499.631262 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/arm/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/gem5/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
+Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 4 2013 23:47:37
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:55:20
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 26786364500 because target called exit()
+Exiting @ tick 26773408500 because target called exit()
sim_ticks 26773408500 # Number of ticks simulated
final_tick 26773408500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 153523 # Simulator instruction rate (inst/s)
-host_op_rate 154625 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45373007 # Simulator tick rate (ticks/s)
-host_mem_usage 376436 # Number of bytes of host memory used
-host_seconds 590.07 # Real time elapsed on the host
+host_inst_rate 111467 # Simulator instruction rate (inst/s)
+host_op_rate 112267 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32943427 # Simulator tick rate (ticks/s)
+host_mem_usage 421388 # Number of bytes of host memory used
+host_seconds 812.71 # Real time elapsed on the host
sim_insts 90589798 # Number of instructions simulated
sim_ops 91240351 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 44992 # Number of bytes read from this memory
system.physmem.readRowHitRate 97.27 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 1726302.76 # Average gap between requests
+system.cpu.branchPred.lookups 26672080 # Number of BP lookups
+system.cpu.branchPred.condPredicted 21992542 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 842598 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 11362388 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 11268059 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 99.169814 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 70167 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 188 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.numCycles 53546818 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 26672080 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 21992542 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 842598 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 11362388 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 11268059 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 70167 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 188 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 14171508 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 127778991 # Number of instructions fetch has processed
system.cpu.fetch.Branches 26672080 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 14:03:25
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 20:04:57
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 54240661000 # Number of ticks simulated
final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2374877 # Simulator instruction rate (inst/s)
-host_op_rate 2391929 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1421759359 # Simulator tick rate (ticks/s)
-host_mem_usage 351688 # Number of bytes of host memory used
-host_seconds 38.15 # Real time elapsed on the host
+host_inst_rate 1585065 # Simulator instruction rate (inst/s)
+host_op_rate 1596445 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 948925064 # Simulator tick rate (ticks/s)
+host_mem_usage 411788 # Number of bytes of host memory used
+host_seconds 57.16 # Real time elapsed on the host
sim_insts 90602407 # Number of instructions simulated
sim_ops 91252960 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:45:02
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 20:06:05
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 148267705000 because target called exit()
+Exiting @ tick 147135976000 because target called exit()
sim_ticks 147135976000 # Number of ticks simulated
final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1200528 # Simulator instruction rate (inst/s)
-host_op_rate 1209136 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1950176496 # Simulator tick rate (ticks/s)
-host_mem_usage 364464 # Number of bytes of host memory used
-host_seconds 75.45 # Real time elapsed on the host
+host_inst_rate 836188 # Simulator instruction rate (inst/s)
+host_op_rate 842183 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1358330065 # Simulator tick rate (ticks/s)
+host_mem_usage 420368 # Number of bytes of host memory used
+host_seconds 108.32 # Real time elapsed on the host
sim_insts 90576861 # Number of instructions simulated
sim_ops 91226312 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51527.545910 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 942702 # number of replacements
-system.cpu.dcache.tagsinuse 3565.217259 # Cycle average of tags in use
-system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.870414 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 26337590 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 26337590 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 26337590 # number of overall hits
-system.cpu.dcache.overall_hits::total 26337590 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 946798 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
-system.cpu.dcache.overall_misses::total 946798 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711445000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11711445000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1216933000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1216933000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 12928378000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 12928378000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 12928378000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 12928378000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 27284388 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 27284388 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 27284388 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 27284388 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.984570 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.984570 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26109.399472 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 26109.399472 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13654.842955 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13654.842955 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks
-system.cpu.dcache.writebacks::total 942334 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 946798 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 9565.271881 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1827177 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 942702 # number of replacements
+system.cpu.dcache.tagsinuse 3565.217259 # Cycle average of tags in use
+system.cpu.dcache.total_refs 26345364 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 27.825750 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 54472394000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.870414 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 26337590 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 26337590 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 26337590 # number of overall hits
+system.cpu.dcache.overall_hits::total 26337590 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 900189 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 46609 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 46609 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 946798 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 946798 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 946798 # number of overall misses
+system.cpu.dcache.overall_misses::total 946798 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711445000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 11711445000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1216933000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 1216933000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 12928378000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 12928378000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 12928378000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 12928378000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 22549407 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 22549407 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 27284388 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 27284388 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 27284388 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 27284388 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.039921 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.039921 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.009844 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.034701 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.034701 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.034701 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.034701 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.984570 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.984570 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26109.399472 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 26109.399472 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 13654.842955 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 13654.842955 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 13654.842955 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 942334 # number of writebacks
+system.cpu.dcache.writebacks::total 942334 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900189 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 900189 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 46609 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 946798 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 946798 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9911067000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9911067000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123715000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123715000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034782000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 11034782000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11034782000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 11034782000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.039921 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.039921 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.034701 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034701 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.034701 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.984570 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.984570 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24109.399472 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11654.842955 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11654.842955 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:13:50
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:10:07
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 122215823500 # Number of ticks simulated
final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2900370 # Simulator instruction rate (inst/s)
-host_op_rate 2900489 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1453791405 # Simulator tick rate (ticks/s)
-host_mem_usage 355144 # Number of bytes of host memory used
-host_seconds 84.07 # Real time elapsed on the host
+host_inst_rate 2097981 # Simulator instruction rate (inst/s)
+host_op_rate 2098068 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1051599524 # Simulator tick rate (ticks/s)
+host_mem_usage 405208 # Number of bytes of host memory used
+host_seconds 116.22 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100
-input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:15:25
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:04:08
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 362481563000 because target called exit()
+Exiting @ tick 361488530000 because target called exit()
sim_ticks 361488530000 # Number of ticks simulated
final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1414417 # Simulator instruction rate (inst/s)
-host_op_rate 1414475 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2096975339 # Simulator tick rate (ticks/s)
-host_mem_usage 357072 # Number of bytes of host memory used
-host_seconds 172.39 # Real time elapsed on the host
+host_inst_rate 1027753 # Simulator instruction rate (inst/s)
+host_op_rate 1027796 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1523718944 # Simulator tick rate (ticks/s)
+host_mem_usage 413792 # Number of bytes of host memory used
+host_seconds 237.24 # Real time elapsed on the host
sim_insts 243825150 # Number of instructions simulated
sim_ops 243835265 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 935475 # number of replacements
-system.cpu.dcache.tagsinuse 3562.469056 # Cycle average of tags in use
-system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.869743 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
-system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
-system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
-system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
-system.cpu.dcache.overall_misses::total 939567 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
-system.cpu.dcache.writebacks::total 935266 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 9730.625290 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1813290 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 935475 # number of replacements
+system.cpu.dcache.tagsinuse 3562.469056 # Cycle average of tags in use
+system.cpu.dcache.total_refs 104186699 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 110.887521 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.869743 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
+system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
+system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
+system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
+system.cpu.dcache.overall_misses::total 939567 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks
+system.cpu.dcache.writebacks::total 935266 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/x86/linux/mcf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/gem5/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
+Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:20:54
-gem5 started Jan 4 2013 22:18:55
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 16:36:34
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 65982862500 # Number of ticks simulated
final_tick 65982862500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 123083 # Simulator instruction rate (inst/s)
-host_op_rate 216729 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 51404636 # Simulator tick rate (ticks/s)
-host_mem_usage 379576 # Number of bytes of host memory used
-host_seconds 1283.60 # Real time elapsed on the host
+host_inst_rate 72483 # Simulator instruction rate (inst/s)
+host_op_rate 127630 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 30271870 # Simulator tick rate (ticks/s)
+host_mem_usage 430980 # Number of bytes of host memory used
+host_seconds 2179.68 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192463 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
system.physmem.readRowHitRate 97.54 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 25.86 # Row buffer hit rate for writes
system.physmem.avgGap 2155034.39 # Average gap between requests
+system.cpu.branchPred.lookups 34537566 # Number of BP lookups
+system.cpu.branchPred.condPredicted 34537566 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 909846 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 24744786 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 24642661 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 99.587287 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 131965726 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 34537566 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 34537566 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 909846 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 24744786 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 24642661 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 26601821 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 185569905 # Number of instructions fetch has processed
system.cpu.fetch.Branches 34537566 # Number of branches that fetch encountered
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:45:38
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:49:17
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
sim_ticks 168950039500 # Number of ticks simulated
final_tick 168950039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 911205 # Simulator instruction rate (inst/s)
-host_op_rate 1604486 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 974425819 # Simulator tick rate (ticks/s)
-host_mem_usage 402856 # Number of bytes of host memory used
-host_seconds 173.38 # Real time elapsed on the host
+host_inst_rate 951900 # Simulator instruction rate (inst/s)
+host_op_rate 1676143 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1017943887 # Simulator tick rate (ticks/s)
+host_mem_usage 420484 # Number of bytes of host memory used
+host_seconds 165.97 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:35:30
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 16:31:05
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
sim_ticks 365989064000 # Number of ticks simulated
final_tick 365989064000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 426513 # Simulator instruction rate (inst/s)
-host_op_rate 751021 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 988040650 # Simulator tick rate (ticks/s)
-host_mem_usage 411308 # Number of bytes of host memory used
-host_seconds 370.42 # Real time elapsed on the host
+host_inst_rate 496442 # Simulator instruction rate (inst/s)
+host_op_rate 874155 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1150035399 # Simulator tick rate (ticks/s)
+host_mem_usage 428932 # Number of bytes of host memory used
+host_seconds 318.24 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2062733 # number of replacements
-system.cpu.dcache.tagsinuse 4076.488630 # Cycle average of tags in use
-system.cpu.dcache.total_refs 120152369 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 126079700000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4076.488630 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 120152369 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 120152369 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 120152369 # number of overall hits
-system.cpu.dcache.overall_hits::total 120152369 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
-system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 122219198 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 122219198 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 122219198 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 122219198 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks
-system.cpu.dcache.writebacks::total 2062484 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 318 # number of replacements
system.cpu.l2cache.tagsinuse 20041.899820 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3992419 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 2062733 # number of replacements
+system.cpu.dcache.tagsinuse 4076.488630 # Cycle average of tags in use
+system.cpu.dcache.total_refs 120152369 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2066829 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 58.133677 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 126079700000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4076.488630 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.995236 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 88818726 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 88818726 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 120152369 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 120152369 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 120152369 # number of overall hits
+system.cpu.dcache.overall_hits::total 120152369 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses
+system.cpu.dcache.overall_misses::total 2066829 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 90779446 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 90779446 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 122219198 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 122219198 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 122219198 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 122219198 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks
+system.cpu.dcache.writebacks::total 2062484 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/arm/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
-input=/gem5/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
-input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:53:48
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 20:09:03
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 290498967000 # Number of ticks simulated
final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2312706 # Simulator instruction rate (inst/s)
-host_op_rate 2606651 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1326219887 # Simulator tick rate (ticks/s)
-host_mem_usage 222284 # Number of bytes of host memory used
-host_seconds 219.04 # Real time elapsed on the host
+host_inst_rate 1613323 # Simulator instruction rate (inst/s)
+host_op_rate 1818377 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 925159382 # Simulator tick rate (ticks/s)
+host_mem_usage 282068 # Number of bytes of host memory used
+host_seconds 314.00 # Real time elapsed on the host
sim_insts 506581607 # Number of instructions simulated
sim_ops 570968167 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
-input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:31:48
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 20:10:40
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 720345914000 because target called exit()
+Exiting @ tick 717366012000 because target called exit()
sim_ticks 717366012000 # Number of ticks simulated
final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 512177 # Simulator instruction rate (inst/s)
-host_op_rate 577137 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 727580493 # Simulator tick rate (ticks/s)
-host_mem_usage 234620 # Number of bytes of host memory used
-host_seconds 985.96 # Real time elapsed on the host
+host_inst_rate 858996 # Simulator instruction rate (inst/s)
+host_op_rate 967944 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1220258898 # Simulator tick rate (ticks/s)
+host_mem_usage 290524 # Number of bytes of host memory used
+host_seconds 587.88 # Real time elapsed on the host
sim_insts 504986853 # Number of instructions simulated
sim_ops 569034839 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21105.199201 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 21105.199201 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1134822 # number of replacements
-system.cpu.dcache.tagsinuse 4065.297446 # Cycle average of tags in use
-system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.992504 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 53883046 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 176840704 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 176840704 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 176840704 # number of overall hits
-system.cpu.dcache.overall_hits::total 176840704 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 782658 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 782658 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 356260 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 356260 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1138918 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1138918 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses
-system.cpu.dcache.overall_misses::total 1138918 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11817433000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11817433000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 8864744000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 8864744000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 20682177000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 20682177000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 20682177000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 20682177000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 123740316 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 123740316 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 177979622 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 177979622 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 177979622 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 177979622 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.006325 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.006325 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006568 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.006568 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.006399 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.006399 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.006399 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.006399 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15099.102034 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 15099.102034 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24882.793465 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 24882.793465 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18159.496118 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 18159.496118 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 18159.496118 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks
-system.cpu.dcache.writebacks::total 1064905 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses
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-system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10252117000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 10252117000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8152224000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8152224000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18404341000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 18404341000 # number of demand (read+write) MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total 18404341000 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses
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-system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13099.102034 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13099.102034 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22882.793465 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22882.793465 # average WriteReq mshr miss latency
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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 109895 # number of replacements
system.cpu.l2cache.tagsinuse 27243.192324 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1668833 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.472473 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.863371 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 1134822 # number of replacements
+system.cpu.dcache.tagsinuse 4065.297446 # Cycle average of tags in use
+system.cpu.dcache.total_refs 179817786 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1138918 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 157.884752 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 11885124000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.992504 # Average percentage of cache occupancy
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+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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+system.cpu.dcache.writebacks::writebacks 1064905 # number of writebacks
+system.cpu.dcache.writebacks::total 1064905 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 782658 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 782658 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356260 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 356260 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1138918 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1138918 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10252117000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 10252117000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8152224000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8152224000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18404341000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 18404341000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18404341000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 18404341000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006325 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006325 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006568 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.006399 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006399 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.006399 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13099.102034 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13099.102034 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22882.793465 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22882.793465 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16159.496118 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 16159.496118 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/x86/linux/parser
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/gem5/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
+Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:20:54
-gem5 started Jan 4 2013 22:32:47
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 16:49:19
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 434474519000 # Number of ticks simulated
final_tick 434474519000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 38128 # Simulator instruction rate (inst/s)
-host_op_rate 70503 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 20033995 # Simulator tick rate (ticks/s)
-host_mem_usage 425632 # Number of bytes of host memory used
-host_seconds 21686.86 # Real time elapsed on the host
+host_inst_rate 63257 # Simulator instruction rate (inst/s)
+host_op_rate 116969 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33237666 # Simulator tick rate (ticks/s)
+host_mem_usage 473612 # Number of bytes of host memory used
+host_seconds 13071.75 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988700 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 208768 # Number of bytes read from this memory
system.physmem.readRowHitRate 88.35 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 51.49 # Row buffer hit rate for writes
system.physmem.avgGap 639455.00 # Average gap between requests
+system.cpu.branchPred.lookups 215014033 # Number of BP lookups
+system.cpu.branchPred.condPredicted 215014033 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 13139181 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 150598539 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 147901505 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 98.209123 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 868949039 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 215014033 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 215014033 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 13139181 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 150598539 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 147901505 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 180614847 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1193262475 # Number of instructions fetch has processed
system.cpu.fetch.Branches 215014033 # Number of branches that fetch encountered
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:35:29
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 16:35:03
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
sim_ticks 885229327500 # Number of ticks simulated
final_tick 885229327500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 941243 # Simulator instruction rate (inst/s)
-host_op_rate 1740465 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1007666185 # Simulator tick rate (ticks/s)
-host_mem_usage 271920 # Number of bytes of host memory used
-host_seconds 878.49 # Real time elapsed on the host
+host_inst_rate 978383 # Simulator instruction rate (inst/s)
+host_op_rate 1809140 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1047426540 # Simulator tick rate (ticks/s)
+host_mem_usage 293648 # Number of bytes of host memory used
+host_seconds 845.15 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:51:49
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:08:30
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
sim_ticks 1647872848000 # Number of ticks simulated
final_tick 1647872848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 488671 # Simulator instruction rate (inst/s)
-host_op_rate 903607 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 973865405 # Simulator tick rate (ticks/s)
-host_mem_usage 280376 # Number of bytes of host memory used
-host_seconds 1692.10 # Real time elapsed on the host
+host_inst_rate 579757 # Simulator instruction rate (inst/s)
+host_op_rate 1072035 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1155389699 # Simulator tick rate (ticks/s)
+host_mem_usage 301076 # Number of bytes of host memory used
+host_seconds 1426.25 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2514362 # number of replacements
-system.cpu.dcache.tagsinuse 4086.415786 # Cycle average of tags in use
-system.cpu.dcache.total_refs 530743929 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 8211723000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4086.415786 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 530743929 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 530743929 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 530743929 # number of overall hits
-system.cpu.dcache.overall_hits::total 530743929 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
-system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 533262387 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 533262387 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 533262387 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 533262387 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19324.874387 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 19324.874387 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks
-system.cpu.dcache.writebacks::total 2323523 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26249455000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 26249455000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17382513500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 17382513500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43631968500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 43631968500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43631968500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 43631968500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 348459 # number of replacements
system.cpu.l2cache.tagsinuse 29286.402681 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3655011 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 2514362 # number of replacements
+system.cpu.dcache.tagsinuse 4086.415786 # Cycle average of tags in use
+system.cpu.dcache.total_refs 530743929 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2518458 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 210.741624 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 8211723000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4086.415786 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.997660 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 382374771 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 382374771 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 530743929 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 530743929 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 530743929 # number of overall hits
+system.cpu.dcache.overall_hits::total 530743929 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses
+system.cpu.dcache.overall_misses::total 2518458 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 384102185 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 384102185 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 533262387 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 533262387 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 533262387 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 533262387 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 19324.874387 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 19324.874387 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks
+system.cpu.dcache.writebacks::total 2323523 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26249455000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 26249455000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17382513500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 17382513500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43631968500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 43631968500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43631968500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 43631968500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 11:24:52
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:33:34
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 139846906500 # Number of ticks simulated
final_tick 139846906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 122154 # Simulator instruction rate (inst/s)
-host_op_rate 122154 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42850332 # Simulator tick rate (ticks/s)
-host_mem_usage 220236 # Number of bytes of host memory used
-host_seconds 3263.61 # Real time elapsed on the host
+host_inst_rate 94955 # Simulator instruction rate (inst/s)
+host_op_rate 94955 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33309069 # Simulator tick rate (ticks/s)
+host_mem_usage 278532 # Number of bytes of host memory used
+host_seconds 4198.46 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
system.physmem.readRowHitRate 87.94 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 19083904.82 # Average gap between requests
+system.cpu.branchPred.lookups 53489670 # Number of BP lookups
+system.cpu.branchPred.condPredicted 30685393 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 32882351 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 15212538 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 46.263535 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 279693814 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 53489670 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 30685393 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 15149659 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 32882351 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 15212538 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 8007516 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 20 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 46.263535 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 24259165 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 280386588 # Number of Reads from Int. Register File
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 11:29:31
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:48:30
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 77336466500 # Number of ticks simulated
final_tick 77336466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 195499 # Simulator instruction rate (inst/s)
-host_op_rate 195499 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 40256068 # Simulator tick rate (ticks/s)
-host_mem_usage 221208 # Number of bytes of host memory used
-host_seconds 1921.11 # Real time elapsed on the host
+host_inst_rate 141610 # Simulator instruction rate (inst/s)
+host_op_rate 141610 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 29159685 # Simulator tick rate (ticks/s)
+host_mem_usage 279556 # Number of bytes of host memory used
+host_seconds 2652.17 # Real time elapsed on the host
sim_insts 375574808 # Number of instructions simulated
sim_ops 375574808 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 220800 # Number of bytes read from this memory
system.physmem.readRowHitRate 87.37 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 10391883.63 # Average gap between requests
+system.cpu.branchPred.lookups 50254079 # Number of BP lookups
+system.cpu.branchPred.condPredicted 29238788 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1202354 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 26185724 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 23237791 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 88.742213 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 9009650 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1041 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 154672935 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 50254079 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 29238788 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1202354 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 26185724 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 23237791 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 9009650 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 1041 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 51121474 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 448760218 # Number of instructions fetch has processed
system.cpu.fetch.Branches 50254079 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 14:23:04
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:04:20
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 199332411500 # Number of ticks simulated
final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3372014 # Simulator instruction rate (inst/s)
-host_op_rate 3372014 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1686007461 # Simulator tick rate (ticks/s)
-host_mem_usage 211928 # Number of bytes of host memory used
-host_seconds 118.23 # Real time elapsed on the host
+host_inst_rate 2294613 # Simulator instruction rate (inst/s)
+host_op_rate 2294613 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1147307033 # Simulator tick rate (ticks/s)
+host_mem_usage 269948 # Number of bytes of host memory used
+host_seconds 173.74 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:30:56
-gem5 started Jul 2 2012 09:39:35
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:49:24
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.566667
-Exiting @ tick 567365869000 because target called exit()
+Exiting @ tick 567335093000 because target called exit()
sim_ticks 567335093000 # Number of ticks simulated
final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1803555 # Simulator instruction rate (inst/s)
-host_op_rate 1803555 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2566617886 # Simulator tick rate (ticks/s)
-host_mem_usage 223016 # Number of bytes of host memory used
-host_seconds 221.04 # Real time elapsed on the host
+host_inst_rate 853902 # Simulator instruction rate (inst/s)
+host_op_rate 853902 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1215178011 # Simulator tick rate (ticks/s)
+host_mem_usage 278532 # Number of bytes of host memory used
+host_seconds 466.87 # Real time elapsed on the host
sim_insts 398664609 # Number of instructions simulated
sim_ops 398664609 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 764 # number of replacements
-system.cpu.dcache.tagsinuse 3288.930576 # Cycle average of tags in use
-system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.802962 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits
-system.cpu.dcache.overall_hits::total 168271068 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
-system.cpu.dcache.overall_misses::total 4152 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
-system.cpu.dcache.writebacks::total 649 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 3772.485305 # Cycle average of tags in use
system.cpu.l2cache.total_refs 677 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 764 # number of replacements
+system.cpu.dcache.tagsinuse 3288.930576 # Cycle average of tags in use
+system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.802962 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits
+system.cpu.dcache.overall_hits::total 168271068 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses
+system.cpu.dcache.overall_misses::total 4152 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 649 # number of writebacks
+system.cpu.dcache.writebacks::total 649 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/arm/linux/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 5 2013 00:06:54
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 20:14:28
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.060000
-Exiting @ tick 68267465500 because target called exit()
+Exiting @ tick 68071881000 because target called exit()
sim_ticks 68071881000 # Number of ticks simulated
final_tick 68071881000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 138205 # Simulator instruction rate (inst/s)
-host_op_rate 176689 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 34456552 # Simulator tick rate (ticks/s)
-host_mem_usage 251760 # Number of bytes of host memory used
-host_seconds 1975.59 # Real time elapsed on the host
+host_inst_rate 102151 # Simulator instruction rate (inst/s)
+host_op_rate 130595 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 25467625 # Simulator tick rate (ticks/s)
+host_mem_usage 296712 # Number of bytes of host memory used
+host_seconds 2672.88 # Real time elapsed on the host
sim_insts 273036725 # Number of instructions simulated
sim_ops 349064449 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 193792 # Number of bytes read from this memory
system.physmem.readRowHitRate 87.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 9342830.15 # Average gap between requests
+system.cpu.branchPred.lookups 41692065 # Number of BP lookups
+system.cpu.branchPred.condPredicted 21046025 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1612310 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 25558633 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 16675018 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 65.242214 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 6736046 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 7190 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.numCycles 136143763 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 41692065 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 21046025 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1612310 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 25558633 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 16675018 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 6736046 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 7190 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 38720751 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 316654874 # Number of instructions fetch has processed
system.cpu.fetch.Branches 41692065 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:08:07
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 20:20:38
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 212344043000 # Number of ticks simulated
final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1672295 # Simulator instruction rate (inst/s)
-host_op_rate 2137948 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1300559764 # Simulator tick rate (ticks/s)
-host_mem_usage 226736 # Number of bytes of host memory used
-host_seconds 163.27 # Real time elapsed on the host
+host_inst_rate 1130367 # Simulator instruction rate (inst/s)
+host_op_rate 1445119 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 879097302 # Simulator tick rate (ticks/s)
+host_mem_usage 286212 # Number of bytes of host memory used
+host_seconds 241.55 # Real time elapsed on the host
sim_insts 273037663 # Number of instructions simulated
sim_ops 349065399 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1394641404 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 13:57:28
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 20:24:50
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.520000
-Exiting @ tick 525920061000 because target called exit()
+Exiting @ tick 525834342000 because target called exit()
sim_ticks 525834342000 # Number of ticks simulated
final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 739511 # Simulator instruction rate (inst/s)
-host_op_rate 945437 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1425757824 # Simulator tick rate (ticks/s)
-host_mem_usage 241188 # Number of bytes of host memory used
-host_seconds 368.81 # Real time elapsed on the host
+host_inst_rate 589682 # Simulator instruction rate (inst/s)
+host_op_rate 753887 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1136891744 # Simulator tick rate (ticks/s)
+host_mem_usage 294668 # Number of bytes of host memory used
+host_seconds 462.52 # Real time elapsed on the host
sim_insts 272739283 # Number of instructions simulated
sim_ops 348687122 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1332 # number of replacements
-system.cpu.dcache.tagsinuse 3078.412981 # Cycle average of tags in use
-system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.751566 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits
-system.cpu.dcache.overall_hits::total 176619809 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
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-system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses
-system.cpu.dcache.overall_misses::total 4478 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles
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-system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses
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-system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
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-system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu.dcache.writebacks::writebacks 998 # number of writebacks
-system.cpu.dcache.writebacks::total 998 # number of writebacks
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-system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses
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-system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency
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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 3487.723791 # Cycle average of tags in use
system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 12:07:24
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:57:22
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 626365181000 # Number of ticks simulated
final_tick 626365181000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 141169 # Simulator instruction rate (inst/s)
-host_op_rate 141169 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48503245 # Simulator tick rate (ticks/s)
-host_mem_usage 240100 # Number of bytes of host memory used
-host_seconds 12913.88 # Real time elapsed on the host
+host_inst_rate 114572 # Simulator instruction rate (inst/s)
+host_op_rate 114572 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 39364843 # Simulator tick rate (ticks/s)
+host_mem_usage 295992 # Number of bytes of host memory used
+host_seconds 15911.79 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
sim_ops 1823043370 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 176064 # Number of bytes read from this memory
system.physmem.readRowHitRate 55.77 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 72.92 # Row buffer hit rate for writes
system.physmem.avgGap 1153499.31 # Average gap between requests
+system.cpu.branchPred.lookups 388924238 # Number of BP lookups
+system.cpu.branchPred.condPredicted 255857711 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 25855826 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 319270007 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 258448229 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 80.949736 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 57345473 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 6929 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 1252730363 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 388924238 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 255857711 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 25855826 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 319270007 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 258448229 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 57345473 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 6929 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 410516643 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 3276851782 # Number of instructions fetch has processed
system.cpu.fetch.Branches 388924238 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 14:31:15
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:44:11
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 1004710587000 # Number of ticks simulated
final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3539563 # Simulator instruction rate (inst/s)
-host_op_rate 3539563 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1770163280 # Simulator tick rate (ticks/s)
-host_mem_usage 211940 # Number of bytes of host memory used
-host_seconds 567.58 # Real time elapsed on the host
+host_inst_rate 2509174 # Simulator instruction rate (inst/s)
+host_op_rate 2509174 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1254857691 # Simulator tick rate (ticks/s)
+host_mem_usage 273968 # Number of bytes of host memory used
+host_seconds 800.66 # Real time elapsed on the host
sim_insts 2008987605 # Number of instructions simulated
sim_ops 2008987605 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 8037684280 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:30:56
-gem5 started Jul 2 2012 09:50:30
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:29:25
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
-Exiting @ tick 2813572242000 because target called exit()
+Exiting @ tick 2769739533000 because target called exit()
sim_ticks 2769739533000 # Number of ticks simulated
final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1761560 # Simulator instruction rate (inst/s)
-host_op_rate 1761559 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2428616742 # Simulator tick rate (ticks/s)
-host_mem_usage 226024 # Number of bytes of host memory used
-host_seconds 1140.46 # Real time elapsed on the host
+host_inst_rate 964642 # Simulator instruction rate (inst/s)
+host_op_rate 964642 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1329927483 # Simulator tick rate (ticks/s)
+host_mem_usage 281524 # Number of bytes of host memory used
+host_seconds 2082.62 # Real time elapsed on the host
sim_insts 2008987605 # Number of instructions simulated
sim_ops 2008987605 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19533.975085 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19533.975085 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1526048 # number of replacements
-system.cpu.dcache.tagsinuse 4095.197836 # Cycle average of tags in use
-system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999804 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 210722944 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 720334778 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 720334778 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 720334778 # number of overall hits
-system.cpu.dcache.overall_hits::total 720334778 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1458192 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1458192 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 71952 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 71952 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1530144 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses
-system.cpu.dcache.overall_misses::total 1530144 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 36022065000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 36022065000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 3744042000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 3744042000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 39766107000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 39766107000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 39766107000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 39766107000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 721864922 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 721864922 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 721864922 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 721864922 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002853 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002853 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000341 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000341 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24703.238668 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24703.238668 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25988.473634 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 25988.473634 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 96129 # number of writebacks
-system.cpu.dcache.writebacks::total 96129 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1458192 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1458192 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71952 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 71952 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33105681000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 33105681000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36705819000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 36705819000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36705819000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 36705819000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22703.238668 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22703.238668 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 442570 # number of replacements
system.cpu.l2cache.tagsinuse 32706.854192 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1089464 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.006340 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.006311 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 1526048 # number of replacements
+system.cpu.dcache.tagsinuse 4095.197836 # Cycle average of tags in use
+system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 1041395000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999804 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 210722944 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 720334778 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 720334778 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 720334778 # number of overall hits
+system.cpu.dcache.overall_hits::total 720334778 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1458192 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1458192 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 71952 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 71952 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 1530144 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1530144 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1530144 # number of overall misses
+system.cpu.dcache.overall_misses::total 1530144 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 36022065000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 36022065000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 3744042000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 3744042000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 39766107000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 39766107000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 39766107000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 39766107000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 511070026 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 511070026 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 210794896 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 210794896 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 721864922 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 721864922 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 721864922 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 721864922 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002853 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002853 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000341 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000341 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.002120 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.002120 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.002120 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.002120 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24703.238668 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24703.238668 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52035.273516 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 52035.273516 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25988.473634 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25988.473634 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 25988.473634 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 96129 # number of writebacks
+system.cpu.dcache.writebacks::total 96129 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1458192 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1458192 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 71952 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 71952 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1530144 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1530144 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1530144 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1530144 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33105681000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 33105681000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3600138000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3600138000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36705819000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 36705819000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36705819000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 36705819000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002853 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002853 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000341 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000341 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002120 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002120 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002120 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22703.238668 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22703.238668 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50035.273516 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23988.473634 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23988.473634 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 5 2013 00:23:14
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 20:27:21
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
2000: 760651391
1000: 4031656975
0: 2206428413
-Exiting @ tick 624867585500 because target called exit()
+Exiting @ tick 625047295000 because target called exit()
sim_ticks 625047295000 # Number of ticks simulated
final_tick 625047295000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 94484 # Simulator instruction rate (inst/s)
-host_op_rate 128674 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42659692 # Simulator tick rate (ticks/s)
-host_mem_usage 264788 # Number of bytes of host memory used
-host_seconds 14651.94 # Real time elapsed on the host
+host_inst_rate 72768 # Simulator instruction rate (inst/s)
+host_op_rate 99100 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32855066 # Simulator tick rate (ticks/s)
+host_mem_usage 309740 # Number of bytes of host memory used
+host_seconds 19024.38 # Real time elapsed on the host
sim_insts 1384370590 # Number of instructions simulated
sim_ops 1885325342 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 155456 # Number of bytes read from this memory
system.physmem.readRowHitRate 52.47 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 72.67 # Row buffer hit rate for writes
system.physmem.avgGap 1155201.56 # Average gap between requests
+system.cpu.branchPred.lookups 438808047 # Number of BP lookups
+system.cpu.branchPred.condPredicted 349805436 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 30625316 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 249957064 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 227370417 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 90.963789 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 52357585 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 2806128 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.numCycles 1250094591 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 438808047 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 349805436 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 30625316 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 249957064 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 227370417 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 52357585 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 2806128 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 353851966 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2287455875 # Number of instructions fetch has processed
system.cpu.fetch.Branches 438808047 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:53:48
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 20:32:44
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 945613126000 # Number of ticks simulated
final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1877363 # Simulator instruction rate (inst/s)
-host_op_rate 2556708 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1282347761 # Simulator tick rate (ticks/s)
-host_mem_usage 223904 # Number of bytes of host memory used
-host_seconds 737.41 # Real time elapsed on the host
+host_inst_rate 1270703 # Simulator instruction rate (inst/s)
+host_op_rate 1730522 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 867964073 # Simulator tick rate (ticks/s)
+host_mem_usage 286692 # Number of bytes of host memory used
+host_seconds 1089.46 # Real time elapsed on the host
sim_insts 1384381606 # Number of instructions simulated
sim_ops 1885336358 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:04:21
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 20:51:04
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
2000: 760651391
1000: 4031656975
0: 2206428413
-Exiting @ tick 2369931974000 because target called exit()
+Exiting @ tick 2326118592000 because target called exit()
sim_ticks 2326118592000 # Number of ticks simulated
final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 541548 # Simulator instruction rate (inst/s)
-host_op_rate 734649 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 911769830 # Simulator tick rate (ticks/s)
-host_mem_usage 240408 # Number of bytes of host memory used
-host_seconds 2551.21 # Real time elapsed on the host
+host_inst_rate 664911 # Simulator instruction rate (inst/s)
+host_op_rate 901999 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1119467924 # Simulator tick rate (ticks/s)
+host_mem_usage 296296 # Number of bytes of host memory used
+host_seconds 2077.88 # Real time elapsed on the host
sim_insts 1381604339 # Number of instructions simulated
sim_ops 1874244941 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14760.642327 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14760.642327 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1529557 # number of replacements
-system.cpu.dcache.tagsinuse 4094.947189 # Cycle average of tags in use
-system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999743 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 895737438 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 895737438 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 895737438 # number of overall hits
-system.cpu.dcache.overall_hits::total 895737438 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 72780 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1533653 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses
-system.cpu.dcache.overall_misses::total 1533653 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 36055529000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 36055529000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 39777575000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 39777575000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 39777575000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 39777575000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 897271091 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 897271091 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 897271091 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 897271091 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000263 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25936.489545 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 25936.489545 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 96257 # number of writebacks
-system.cpu.dcache.writebacks::total 96257 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 72780 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33133783000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 33133783000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36710269000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 36710269000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36710269000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 441378 # number of replacements
system.cpu.l2cache.tagsinuse 32692.891822 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1102614 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.012654 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 1529557 # number of replacements
+system.cpu.dcache.tagsinuse 4094.947189 # Cycle average of tags in use
+system.cpu.dcache.total_refs 895757408 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 584.067848 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 991199000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999743 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 276862898 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 9985 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 9985 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 895737438 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 895737438 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 895737438 # number of overall hits
+system.cpu.dcache.overall_hits::total 895737438 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1460873 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1460873 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 72780 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 72780 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 1533653 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1533653 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1533653 # number of overall misses
+system.cpu.dcache.overall_misses::total 1533653 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 36055529000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 36055529000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 3722046000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 3722046000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 39777575000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 39777575000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 39777575000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 39777575000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 620335413 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 620335413 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9985 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 897271091 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 897271091 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 897271091 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 897271091 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002355 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002355 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000263 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000263 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.001709 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.001709 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.001709 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.001709 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24680.810036 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 24680.810036 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51141.055235 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 51141.055235 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25936.489545 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25936.489545 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 25936.489545 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 96257 # number of writebacks
+system.cpu.dcache.writebacks::total 96257 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1460873 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1460873 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72780 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 72780 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1533653 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1533653 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1533653 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1533653 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33133783000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 33133783000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3576486000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3576486000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36710269000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 36710269000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36710269000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 36710269000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002355 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002355 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000263 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.001709 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001709 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.001709 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22680.810036 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22680.810036 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49141.055235 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23936.489545 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 23936.489545 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 12:19:26
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:34:49
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 43266024500 # Number of ticks simulated
final_tick 43266024500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 113775 # Simulator instruction rate (inst/s)
-host_op_rate 113775 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 55722813 # Simulator tick rate (ticks/s)
-host_mem_usage 252752 # Number of bytes of host memory used
-host_seconds 776.45 # Real time elapsed on the host
+host_inst_rate 92573 # Simulator instruction rate (inst/s)
+host_op_rate 92573 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 45339086 # Simulator tick rate (ticks/s)
+host_mem_usage 308556 # Number of bytes of host memory used
+host_seconds 954.28 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 454720 # Number of bytes read from this memory
system.physmem.readRowHitRate 91.81 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 36.59 # Row buffer hit rate for writes
system.physmem.avgGap 154790.12 # Average gap between requests
+system.cpu.branchPred.lookups 18742312 # Number of BP lookups
+system.cpu.branchPred.condPredicted 12317439 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 4774431 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 15498318 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 4661486 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 30.077367 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1660962 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 86532050 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 18742312 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 12317439 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 4774431 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 15498318 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 4661486 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 1660962 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 1030 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 30.077367 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 8071751 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 10670561 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 74169472 # Number of Reads from Int. Register File
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 12:32:34
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:35:07
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 24414646000 # Number of ticks simulated
final_tick 24414646000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 171645 # Simulator instruction rate (inst/s)
-host_op_rate 171645 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 52651835 # Simulator tick rate (ticks/s)
-host_mem_usage 254848 # Number of bytes of host memory used
-host_seconds 463.70 # Real time elapsed on the host
+host_inst_rate 131517 # Simulator instruction rate (inst/s)
+host_op_rate 131517 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 40342582 # Simulator tick rate (ticks/s)
+host_mem_usage 309584 # Number of bytes of host memory used
+host_seconds 605.18 # Real time elapsed on the host
sim_insts 79591756 # Number of instructions simulated
sim_ops 79591756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 490368 # Number of bytes read from this memory
system.physmem.readRowHitRate 91.56 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 35.80 # Row buffer hit rate for writes
system.physmem.avgGap 87091.78 # Average gap between requests
+system.cpu.branchPred.lookups 16536427 # Number of BP lookups
+system.cpu.branchPred.condPredicted 10675204 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 418905 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 11705282 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7341882 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 62.722812 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1987114 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 42052 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 48829295 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 16536427 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 10675204 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 418905 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 11705282 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7341882 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1987114 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 42052 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 15791672 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 105370615 # Number of instructions fetch has processed
system.cpu.fetch.Branches 16536427 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 14:30:37
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:34:02
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 44221003000 # Number of ticks simulated
final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3187268 # Simulator instruction rate (inst/s)
-host_op_rate 3187266 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1595460185 # Simulator tick rate (ticks/s)
-host_mem_usage 214012 # Number of bytes of host memory used
-host_seconds 27.72 # Real time elapsed on the host
+host_inst_rate 2426632 # Simulator instruction rate (inst/s)
+host_op_rate 2426631 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1214706702 # Simulator tick rate (ticks/s)
+host_mem_usage 272072 # Number of bytes of host memory used
+host_seconds 36.40 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:30:56
-gem5 started Jul 2 2012 10:09:02
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:15:43
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 134581343000 because target called exit()
+Exiting @ tick 133634727000 because target called exit()
sim_ticks 133634727000 # Number of ticks simulated
final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 783809 # Simulator instruction rate (inst/s)
-host_op_rate 783809 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1185683886 # Simulator tick rate (ticks/s)
-host_mem_usage 225136 # Number of bytes of host memory used
-host_seconds 112.71 # Real time elapsed on the host
+host_inst_rate 996502 # Simulator instruction rate (inst/s)
+host_op_rate 996501 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1507427540 # Simulator tick rate (ticks/s)
+host_mem_usage 280652 # Number of bytes of host memory used
+host_seconds 88.65 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 200248 # number of replacements
-system.cpu.dcache.tagsinuse 4078.863631 # Cycle average of tags in use
-system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 936463000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.995816 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits
-system.cpu.dcache.overall_hits::total 34685671 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
-system.cpu.dcache.overall_misses::total 204344 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945752000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 1945752000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363555000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 7363555000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 9309307000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 9309307000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 9309307000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 9309307000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32020.406148 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32020.406148 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51286.095363 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 51286.095363 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45557.036174 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45557.036174 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks
-system.cpu.dcache.writebacks::total 168375 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1824220000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1824220000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7076399000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 7076399000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8900619000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 8900619000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8900619000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 8900619000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30020.406148 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.406148 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49286.095363 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49286.095363 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 131235 # number of replacements
system.cpu.l2cache.tagsinuse 30728.810101 # Cycle average of tags in use
system.cpu.l2cache.total_refs 142024 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 200248 # number of replacements
+system.cpu.dcache.tagsinuse 4078.863631 # Cycle average of tags in use
+system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 936463000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.995816 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits
+system.cpu.dcache.overall_hits::total 34685671 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses
+system.cpu.dcache.overall_misses::total 204344 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945752000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 1945752000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363555000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 7363555000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 9309307000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 9309307000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 9309307000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 9309307000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32020.406148 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32020.406148 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51286.095363 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 51286.095363 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45557.036174 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 45557.036174 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks
+system.cpu.dcache.writebacks::total 168375 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1824220000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 1824220000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7076399000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 7076399000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8900619000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 8900619000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8900619000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 8900619000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30020.406148 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.406148 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49286.095363 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49286.095363 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/arm/linux/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 5 2013 00:36:17
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 20:59:12
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 26292466000 because target called exit()
+Exiting @ tick 26275145500 because target called exit()
sim_ticks 26275145500 # Number of ticks simulated
final_tick 26275145500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 119366 # Simulator instruction rate (inst/s)
-host_op_rate 169395 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44231565 # Simulator tick rate (ticks/s)
-host_mem_usage 271872 # Number of bytes of host memory used
-host_seconds 594.04 # Real time elapsed on the host
+host_inst_rate 87619 # Simulator instruction rate (inst/s)
+host_op_rate 124343 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32467681 # Simulator tick rate (ticks/s)
+host_mem_usage 316828 # Number of bytes of host memory used
+host_seconds 809.27 # Real time elapsed on the host
sim_insts 70907629 # Number of instructions simulated
sim_ops 100626876 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 298112 # Number of bytes read from this memory
system.physmem.readRowHitRate 92.36 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 32.37 # Row buffer hit rate for writes
system.physmem.avgGap 123527.37 # Average gap between requests
+system.cpu.branchPred.lookups 16626972 # Number of BP lookups
+system.cpu.branchPred.condPredicted 12763144 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 604576 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 10780847 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7773827 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 72.107757 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1825491 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 113784 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.numCycles 52550292 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 16626972 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 12763144 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 604576 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 10780847 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 7773827 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1825491 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 113784 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 12554350 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 85230964 # Number of instructions fetch has processed
system.cpu.fetch.Branches 16626972 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 14:04:14
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:10:40
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 53932157000 # Number of ticks simulated
final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1829500 # Simulator instruction rate (inst/s)
-host_op_rate 2596230 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1391402909 # Simulator tick rate (ticks/s)
-host_mem_usage 226332 # Number of bytes of host memory used
-host_seconds 38.76 # Real time elapsed on the host
+host_inst_rate 1242714 # Simulator instruction rate (inst/s)
+host_op_rate 1763527 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 945130731 # Simulator tick rate (ticks/s)
+host_mem_usage 286616 # Number of bytes of host memory used
+host_seconds 57.06 # Real time elapsed on the host
sim_insts 70913181 # Number of instructions simulated
sim_ops 100632428 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:06:20
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:11:48
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 133513136000 because target called exit()
+Exiting @ tick 132689045000 because target called exit()
sim_ticks 132689045000 # Number of ticks simulated
final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 796611 # Simulator instruction rate (inst/s)
-host_op_rate 1129615 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1502004709 # Simulator tick rate (ticks/s)
-host_mem_usage 239164 # Number of bytes of host memory used
-host_seconds 88.34 # Real time elapsed on the host
+host_inst_rate 652363 # Simulator instruction rate (inst/s)
+host_op_rate 925068 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1230026759 # Simulator tick rate (ticks/s)
+host_mem_usage 295072 # Number of bytes of host memory used
+host_seconds 107.88 # Real time elapsed on the host
sim_insts 70373628 # Number of instructions simulated
sim_ops 99791654 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19880.791199 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19880.791199 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 155902 # number of replacements
-system.cpu.dcache.tagsinuse 4076.954355 # Cycle average of tags in use
-system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.995350 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 46830236 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 46830236 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 46830236 # number of overall hits
-system.cpu.dcache.overall_hits::total 46830236 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 52966 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 52966 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 159998 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 159998 # number of overall misses
-system.cpu.dcache.overall_misses::total 159998 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 1599899000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 1599899000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 5687190000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 5687190000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7287089000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7287089000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7287089000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7287089000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 46990234 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 46990234 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 46990234 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 46990234 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.001952 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30206.151116 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 30206.151116 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53135.417445 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 53135.417445 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 45544.875561 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 45544.875561 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks
-system.cpu.dcache.writebacks::total 128239 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 159998 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1493967000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1493967000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5473126000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 5473126000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6967093000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6967093000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6967093000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6967093000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28206.151116 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28206.151116 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51135.417445 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51135.417445 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 94693 # number of replacements
system.cpu.l2cache.tagsinuse 30368.194893 # Cycle average of tags in use
system.cpu.l2cache.total_refs 74295 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40053.908900 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40054.212437 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 155902 # number of replacements
+system.cpu.dcache.tagsinuse 4076.954355 # Cycle average of tags in use
+system.cpu.dcache.total_refs 46862074 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 292.891624 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 1072595000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.995350 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 46830236 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 46830236 # number of demand (read+write) hits
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+system.cpu.dcache.overall_hits::total 46830236 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 52966 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 52966 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 159998 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 159998 # number of demand (read+write) misses
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+system.cpu.dcache.overall_misses::total 159998 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 1599899000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 1599899000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 5687190000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 5687190000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7287089000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7287089000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7287089000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7287089000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 27140333 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 27140333 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 46990234 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 46990234 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 46990234 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 46990234 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001952 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.001952 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.003405 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.003405 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.003405 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.003405 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30206.151116 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 30206.151116 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53135.417445 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 53135.417445 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 45544.875561 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 45544.875561 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 45544.875561 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks
+system.cpu.dcache.writebacks::total 128239 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 52966 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 52966 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 107032 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 159998 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 159998 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1493967000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 1493967000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5473126000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5473126000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6967093000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6967093000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6967093000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6967093000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001952 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001952 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.003405 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003405 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.003405 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28206.151116 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28206.151116 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51135.417445 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51135.417445 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43544.875561 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 43544.875561 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:18:28
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:08:27
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 68148672000 # Number of ticks simulated
final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2819750 # Simulator instruction rate (inst/s)
-host_op_rate 2856259 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1429788311 # Simulator tick rate (ticks/s)
-host_mem_usage 230172 # Number of bytes of host memory used
-host_seconds 47.66 # Real time elapsed on the host
+host_inst_rate 2091817 # Simulator instruction rate (inst/s)
+host_op_rate 2118902 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1060681468 # Simulator tick rate (ticks/s)
+host_mem_usage 281256 # Number of bytes of host memory used
+host_seconds 64.25 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:19:26
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:01:47
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 204097178000 because target called exit()
+Exiting @ tick 202242260000 because target called exit()
sim_ticks 202242260000 # Number of ticks simulated
final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1258181 # Simulator instruction rate (inst/s)
-host_op_rate 1274472 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1893298806 # Simulator tick rate (ticks/s)
-host_mem_usage 233128 # Number of bytes of host memory used
-host_seconds 106.82 # Real time elapsed on the host
+host_inst_rate 1033030 # Simulator instruction rate (inst/s)
+host_op_rate 1046406 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1554493166 # Simulator tick rate (ticks/s)
+host_mem_usage 289840 # Number of bytes of host memory used
+host_seconds 130.10 # Real time elapsed on the host
sim_insts 134398962 # Number of instructions simulated
sim_ops 136139190 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 146582 # number of replacements
-system.cpu.dcache.tagsinuse 4087.648350 # Cycle average of tags in use
-system.cpu.dcache.total_refs 57960842 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 384.666919 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 769040000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.997961 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits
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-system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits
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-system.cpu.dcache.overall_hits::total 57944941 # number of overall hits
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-system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses
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-system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses
-system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses
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-system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses
-system.cpu.dcache.overall_misses::total 150663 # number of overall misses
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-system.cpu.dcache.ReadReq_miss_latency::total 1475111000 # number of ReadReq miss cycles
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-system.cpu.dcache.WriteReq_miss_latency::total 5619675000 # number of WriteReq miss cycles
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-system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles
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-system.cpu.dcache.demand_miss_latency::total 7094786000 # number of demand (read+write) miss cycles
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-system.cpu.dcache.overall_miss_latency::total 7094786000 # number of overall miss cycles
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-system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses)
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-system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses
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-system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses
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-system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses
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-system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses
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-system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 32420.734522 # average ReadReq miss latency
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.250390 # average WriteReq miss latency
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-system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency
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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 47090.433617 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks
-system.cpu.dcache.writebacks::total 123970 # number of writebacks
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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
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-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 98540 # number of replacements
system.cpu.l2cache.tagsinuse 30850.759699 # Cycle average of tags in use
system.cpu.l2cache.total_refs 226933 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1384113000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 1384113000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5409347000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5409347000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793460000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6793460000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6793460000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6793460000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30420.734522 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30420.734522 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51437.250390 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51437.250390 # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 12:40:49
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:29:25
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 985089830500 # Number of ticks simulated
final_tick 985089830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 109003 # Simulator instruction rate (inst/s)
-host_op_rate 109003 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 59005665 # Simulator tick rate (ticks/s)
-host_mem_usage 485696 # Number of bytes of host memory used
-host_seconds 16694.83 # Real time elapsed on the host
+host_inst_rate 87940 # Simulator instruction rate (inst/s)
+host_op_rate 87940 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 47603973 # Simulator tick rate (ticks/s)
+host_mem_usage 516412 # Number of bytes of host memory used
+host_seconds 20693.44 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
system.physmem.readRowHitRate 42.60 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 19.07 # Row buffer hit rate for writes
system.physmem.avgGap 330817.71 # Average gap between requests
+system.cpu.branchPred.lookups 326556831 # Number of BP lookups
+system.cpu.branchPred.condPredicted 252596788 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 138232865 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 218937552 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 135479530 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 61.880444 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 1970179662 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 326556831 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 252596788 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 138232865 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 218937552 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 135479530 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 16767439 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 6 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 61.880444 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 172296521 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 154260310 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 1667620352 # Number of Reads from Int. Register File
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 12:41:35
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:57:42
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 655919824500 # Number of ticks simulated
final_tick 655919824500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 137989 # Simulator instruction rate (inst/s)
-host_op_rate 137989 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 52135439 # Simulator tick rate (ticks/s)
-host_mem_usage 496344 # Number of bytes of host memory used
-host_seconds 12581.07 # Real time elapsed on the host
+host_inst_rate 111017 # Simulator instruction rate (inst/s)
+host_op_rate 111017 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 41944886 # Simulator tick rate (ticks/s)
+host_mem_usage 517560 # Number of bytes of host memory used
+host_seconds 15637.66 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
sim_ops 1736043781 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 61504 # Number of bytes read from this memory
system.physmem.readRowHitRate 42.77 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 19.01 # Row buffer hit rate for writes
system.physmem.avgGap 219646.04 # Average gap between requests
+system.cpu.branchPred.lookups 381024003 # Number of BP lookups
+system.cpu.branchPred.condPredicted 296029232 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 16079219 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 261934224 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 259237388 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 98.970415 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 24703724 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 3041 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 1311839650 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 381024003 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 296029232 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 16079219 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 261934224 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 259237388 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 24703724 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 3041 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 402148068 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 3157560086 # Number of instructions fetch has processed
system.cpu.fetch.Branches 381024003 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 14:21:33
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:47:45
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 913189263000 # Number of ticks simulated
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3414010 # Simulator instruction rate (inst/s)
-host_op_rate 3414010 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1713194291 # Simulator tick rate (ticks/s)
-host_mem_usage 206032 # Number of bytes of host memory used
-host_seconds 533.03 # Real time elapsed on the host
+host_inst_rate 2288605 # Simulator instruction rate (inst/s)
+host_op_rate 2288605 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1148451794 # Simulator tick rate (ticks/s)
+host_mem_usage 263992 # Number of bytes of host memory used
+host_seconds 795.15 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:30:56
-gem5 started Jul 2 2012 10:19:14
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:15:18
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2642007987000 because target called exit()
+Exiting @ tick 2623386226000 because target called exit()
sim_ticks 2623386226000 # Number of ticks simulated
final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1789114 # Simulator instruction rate (inst/s)
-host_op_rate 1789114 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2579177735 # Simulator tick rate (ticks/s)
-host_mem_usage 217052 # Number of bytes of host memory used
-host_seconds 1017.14 # Real time elapsed on the host
+host_inst_rate 1056521 # Simulator instruction rate (inst/s)
+host_op_rate 1056521 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1523075909 # Simulator tick rate (ticks/s)
+host_mem_usage 272444 # Number of bytes of host memory used
+host_seconds 1722.43 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 9107638 # number of replacements
-system.cpu.dcache.tagsinuse 4079.262869 # Cycle average of tags in use
-system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.995914 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits
-system.cpu.dcache.overall_hits::total 596212431 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses
-system.cpu.dcache.overall_misses::total 9111734 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 143374726000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 143374726000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 57377180000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 57377180000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 200751906000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 200751906000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 200751906000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 200751906000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19851.358009 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19851.358009 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30369.222789 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30369.222789 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22032.239528 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22032.239528 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks
-system.cpu.dcache.writebacks::total 3693497 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses
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-system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 128929898000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53598540000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 53598540000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182528438000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 182528438000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182528438000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 182528438000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17851.358009 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17851.358009 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28369.222789 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28369.222789 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1926937 # number of replacements
system.cpu.l2cache.tagsinuse 30535.257456 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8959453 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 9107638 # number of replacements
+system.cpu.dcache.tagsinuse 4079.262869 # Cycle average of tags in use
+system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.995914 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits
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+system.cpu.dcache.demand_miss_latency::total 200751906000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 200751906000 # number of overall miss cycles
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+system.cpu.dcache.overall_avg_miss_latency::total 22032.239528 # average overall miss latency
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+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks
+system.cpu.dcache.writebacks::total 3693497 # number of writebacks
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+system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128929898000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 128929898000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53598540000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 53598540000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182528438000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 182528438000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182528438000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 182528438000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17851.358009 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17851.358009 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28369.222789 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28369.222789 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 5 2013 00:51:58
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:12:52
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 506577346000 because target called exit()
+Exiting @ tick 506353996500 because target called exit()
sim_ticks 506353996500 # Number of ticks simulated
final_tick 506353996500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 136322 # Simulator instruction rate (inst/s)
-host_op_rate 152077 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44690362 # Simulator tick rate (ticks/s)
-host_mem_usage 507940 # Number of bytes of host memory used
-host_seconds 11330.27 # Real time elapsed on the host
+host_inst_rate 105319 # Simulator instruction rate (inst/s)
+host_op_rate 117491 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 34526611 # Simulator tick rate (ticks/s)
+host_mem_usage 552892 # Number of bytes of host memory used
+host_seconds 14665.62 # Real time elapsed on the host
sim_insts 1544563023 # Number of instructions simulated
sim_ops 1723073835 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 48000 # Number of bytes read from this memory
system.physmem.readRowHitRate 40.71 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 17.17 # Row buffer hit rate for writes
system.physmem.avgGap 151240.81 # Average gap between requests
+system.cpu.branchPred.lookups 301930111 # Number of BP lookups
+system.cpu.branchPred.condPredicted 248173247 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 15201095 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 171785530 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 160276899 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 93.300582 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 17551988 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 206 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.numCycles 1012707994 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 301930111 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 248173247 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 15201095 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 171785530 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 160276899 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 17551988 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 206 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 296178013 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2176838116 # Number of instructions fetch has processed
system.cpu.fetch.Branches 301930111 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:26:56
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:13:46
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 861538200000 # Number of ticks simulated
final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2426875 # Simulator instruction rate (inst/s)
-host_op_rate 2707358 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1353681051 # Simulator tick rate (ticks/s)
-host_mem_usage 219056 # Number of bytes of host memory used
-host_seconds 636.44 # Real time elapsed on the host
+host_inst_rate 1602478 # Simulator instruction rate (inst/s)
+host_op_rate 1787682 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 893842215 # Simulator tick rate (ticks/s)
+host_mem_usage 278712 # Number of bytes of host memory used
+host_seconds 963.86 # Real time elapsed on the host
sim_insts 1544563041 # Number of instructions simulated
sim_ops 1723073853 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:53:48
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:25:52
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2409361491000 because target called exit()
+Exiting @ tick 2391205115000 because target called exit()
sim_ticks 2391205115000 # Number of ticks simulated
final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1213159 # Simulator instruction rate (inst/s)
-host_op_rate 1353897 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1885227488 # Simulator tick rate (ticks/s)
-host_mem_usage 231376 # Number of bytes of host memory used
-host_seconds 1268.39 # Real time elapsed on the host
+host_inst_rate 809589 # Simulator instruction rate (inst/s)
+host_op_rate 903509 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1258086461 # Simulator tick rate (ticks/s)
+host_mem_usage 287292 # Number of bytes of host memory used
+host_seconds 1900.67 # Real time elapsed on the host
sim_insts 1538759601 # Number of instructions simulated
sim_ops 1717270334 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 9111140 # number of replacements
-system.cpu.dcache.tagsinuse 4083.522356 # Cycle average of tags in use
-system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.996954 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits
-system.cpu.dcache.overall_hits::total 645854937 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
-system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks
-system.cpu.dcache.writebacks::total 3697418 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1926075 # number of replacements
system.cpu.l2cache.tagsinuse 30987.094489 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8967572 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 9111140 # number of replacements
+system.cpu.dcache.tagsinuse 4083.522356 # Cycle average of tags in use
+system.cpu.dcache.total_refs 645855059 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.996954 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits
+system.cpu.dcache.overall_hits::total 645854937 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
+system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks
+system.cpu.dcache.writebacks::total 3697418 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:35:30
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 17:13:04
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
sim_ticks 2846007227000 # Number of ticks simulated
final_tick 2846007227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1003542 # Simulator instruction rate (inst/s)
-host_op_rate 1563610 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 949472024 # Simulator tick rate (ticks/s)
-host_mem_usage 267592 # Number of bytes of host memory used
-host_seconds 2997.46 # Real time elapsed on the host
+host_inst_rate 1019064 # Simulator instruction rate (inst/s)
+host_op_rate 1587794 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 964157561 # Simulator tick rate (ticks/s)
+host_mem_usage 283172 # Number of bytes of host memory used
+host_seconds 2951.81 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:38:11
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:35:45
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
sim_ticks 5882580525000 # Number of ticks simulated
final_tick 5882580525000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 506721 # Simulator instruction rate (inst/s)
-host_op_rate 789517 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 990939541 # Simulator tick rate (ticks/s)
-host_mem_usage 276172 # Number of bytes of host memory used
-host_seconds 5936.37 # Real time elapsed on the host
+host_inst_rate 639726 # Simulator instruction rate (inst/s)
+host_op_rate 996751 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1251043124 # Simulator tick rate (ticks/s)
+host_mem_usage 291744 # Number of bytes of host memory used
+host_seconds 4702.14 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 9108581 # number of replacements
-system.cpu.dcache.tagsinuse 4084.587031 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1668600406 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 58853921000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 4084.587031 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1668600406 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1668600406 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1668600406 # number of overall hits
-system.cpu.dcache.overall_hits::total 1668600406 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
-system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382215000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 57382215000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1677713083 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1677713083 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1677713083 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1677713083 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.765411 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.765411 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.739644 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.739644 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 22025.443895 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 22025.443895 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks
-system.cpu.dcache.writebacks::total 3697956 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128882841000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 128882841000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53602561000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 53602561000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182485402000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 182485402000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182485402000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 182485402000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1926197 # number of replacements
system.cpu.l2cache.tagsinuse 31136.249384 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8965026 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 9108581 # number of replacements
+system.cpu.dcache.tagsinuse 4084.587031 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1668600406 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 58853921000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 4084.587031 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.997214 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1231961895 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1231961895 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 1668600406 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1668600406 # number of demand (read+write) hits
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+system.cpu.dcache.overall_hits::total 1668600406 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
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+system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
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+system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
+system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382215000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 57382215000 # number of WriteReq miss cycles
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+system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1239184745 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1239184745 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 1677713083 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1677713083 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1677713083 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1677713083 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.765411 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.765411 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.739644 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.739644 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 22025.443895 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 22025.443895 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks
+system.cpu.dcache.writebacks::total 3697956 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128882841000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 128882841000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53602561000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 53602561000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182485402000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 182485402000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182485402000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 182485402000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 13:10:16
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:29:27
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 41615049000 # Number of ticks simulated
final_tick 41615049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 117678 # Simulator instruction rate (inst/s)
-host_op_rate 117678 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 53286406 # Simulator tick rate (ticks/s)
-host_mem_usage 217828 # Number of bytes of host memory used
-host_seconds 780.97 # Real time elapsed on the host
+host_inst_rate 92405 # Simulator instruction rate (inst/s)
+host_op_rate 92405 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 41842312 # Simulator tick rate (ticks/s)
+host_mem_usage 276220 # Number of bytes of host memory used
+host_seconds 994.57 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
system.physmem.readRowHitRate 90.26 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 8427500.41 # Average gap between requests
+system.cpu.branchPred.lookups 13412629 # Number of BP lookups
+system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 7424481 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 3768497 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 50.757716 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 83230099 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 13412629 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 9650146 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 4269214 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 7424481 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 3768497 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 1029619 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 126 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 50.757716 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 5905664 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 73570547 # Number of Reads from Int. Register File
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 13:23:29
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:04:24
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 23378067000 # Number of ticks simulated
final_tick 23378067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 166789 # Simulator instruction rate (inst/s)
-host_op_rate 166789 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 46320112 # Simulator tick rate (ticks/s)
-host_mem_usage 219224 # Number of bytes of host memory used
-host_seconds 504.71 # Real time elapsed on the host
+host_inst_rate 125836 # Simulator instruction rate (inst/s)
+host_op_rate 125836 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 34946651 # Simulator tick rate (ticks/s)
+host_mem_usage 277248 # Number of bytes of host memory used
+host_seconds 668.96 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
sim_ops 84179709 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 196096 # Number of bytes read from this memory
system.physmem.readRowHitRate 89.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 4471683.44 # Average gap between requests
+system.cpu.branchPred.lookups 14833517 # Number of BP lookups
+system.cpu.branchPred.condPredicted 10762267 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 917019 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 8075874 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 6944735 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 85.993603 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1466052 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 3147 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 46756135 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 14833517 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 10762267 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 917019 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 8075874 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 6944735 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 1466052 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 3147 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 15430530 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 126815242 # Number of instructions fetch has processed
system.cpu.fetch.Branches 14833517 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
clock=1000
header_cycles=1
use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 13:46:55
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:46:14
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2
sim_ticks 45951567500 # Number of ticks simulated
final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3561938 # Simulator instruction rate (inst/s)
-host_op_rate 3561935 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1780967913 # Simulator tick rate (ticks/s)
-host_mem_usage 209744 # Number of bytes of host memory used
-host_seconds 25.80 # Real time elapsed on the host
+host_inst_rate 1141309 # Simulator instruction rate (inst/s)
+host_op_rate 1141309 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 570654979 # Simulator tick rate (ticks/s)
+host_mem_usage 267644 # Number of bytes of host memory used
+host_seconds 80.52 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
header_cycles=1
use_default_range=false
width=8
-master=system.physmem.port[0]
+master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:30:56
-gem5 started Jul 2 2012 10:59:12
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing
-Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav
-Couldn't unlink build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:17:33
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 118779533000 because target called exit()
+122 123 124 Exiting @ tick 118729316000 because target called exit()
sim_ticks 118729316000 # Number of ticks simulated
final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 979371 # Simulator instruction rate (inst/s)
-host_op_rate 979371 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1265246648 # Simulator tick rate (ticks/s)
-host_mem_usage 223148 # Number of bytes of host memory used
-host_seconds 93.84 # Real time elapsed on the host
+host_inst_rate 1044383 # Simulator instruction rate (inst/s)
+host_op_rate 1044383 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1349235521 # Simulator tick rate (ticks/s)
+host_mem_usage 276220 # Number of bytes of host memory used
+host_seconds 88.00 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 157 # number of replacements
-system.cpu.dcache.tagsinuse 1442.043392 # Cycle average of tags in use
-system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.352061 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits
-system.cpu.dcache.overall_hits::total 26495078 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses
-system.cpu.dcache.overall_misses::total 2223 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
-system.cpu.dcache.writebacks::total 107 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2074.070560 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5956 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 157 # number of replacements
+system.cpu.dcache.tagsinuse 1442.043392 # Cycle average of tags in use
+system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.352061 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits
+system.cpu.dcache.overall_hits::total 26495078 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses
+system.cpu.dcache.overall_misses::total 2223 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
+system.cpu.dcache.writebacks::total 107 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/arm/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 5 2013 01:10:37
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:30:01
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 74245032000 because target called exit()
+122 123 124 Exiting @ tick 74148853000 because target called exit()
sim_ticks 74148853000 # Number of ticks simulated
final_tick 74148853000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 112590 # Simulator instruction rate (inst/s)
-host_op_rate 123276 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48451809 # Simulator tick rate (ticks/s)
-host_mem_usage 247684 # Number of bytes of host memory used
-host_seconds 1530.36 # Real time elapsed on the host
+host_inst_rate 87257 # Simulator instruction rate (inst/s)
+host_op_rate 95539 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37550131 # Simulator tick rate (ticks/s)
+host_mem_usage 292636 # Number of bytes of host memory used
+host_seconds 1974.66 # Real time elapsed on the host
sim_insts 172303021 # Number of instructions simulated
sim_ops 188656503 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 131648 # Number of bytes read from this memory
system.physmem.readRowHitRate 86.91 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 19492332.94 # Average gap between requests
+system.cpu.branchPred.lookups 94799058 # Number of BP lookups
+system.cpu.branchPred.condPredicted 74801869 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 6279291 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 44724397 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 43048437 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 96.252694 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 4355507 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 88338 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.numCycles 148297707 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 94799058 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 74801869 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 6279291 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 44724397 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 43048437 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 4355507 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 88338 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 39650853 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 380235632 # Number of instructions fetch has processed
system.cpu.fetch.Branches 94799058 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:39:32
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:36:32
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2
sim_ticks 103106766000 # Number of ticks simulated
final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2085648 # Simulator instruction rate (inst/s)
-host_op_rate 2283582 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1247954818 # Simulator tick rate (ticks/s)
-host_mem_usage 222132 # Number of bytes of host memory used
-host_seconds 82.62 # Real time elapsed on the host
+host_inst_rate 1465257 # Simulator instruction rate (inst/s)
+host_op_rate 1604314 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 876741604 # Simulator tick rate (ticks/s)
+host_mem_usage 282008 # Number of bytes of host memory used
+host_seconds 117.60 # Real time elapsed on the host
sim_insts 172317409 # Number of instructions simulated
sim_ops 188670891 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 12:07:48
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 21:38:40
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 232089948000 because target called exit()
+122 123 124 Exiting @ tick 232072304000 because target called exit()
sim_ticks 232072304000 # Number of ticks simulated
final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 603492 # Simulator instruction rate (inst/s)
-host_op_rate 660888 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 815011792 # Simulator tick rate (ticks/s)
-host_mem_usage 237088 # Number of bytes of host memory used
-host_seconds 284.75 # Real time elapsed on the host
+host_inst_rate 817822 # Simulator instruction rate (inst/s)
+host_op_rate 895603 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1104464333 # Simulator tick rate (ticks/s)
+host_mem_usage 290584 # Number of bytes of host memory used
+host_seconds 210.12 # Real time elapsed on the host
sim_insts 171842483 # Number of instructions simulated
sim_ops 188185920 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 34801.376598 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 40 # number of replacements
-system.cpu.dcache.tagsinuse 1363.611259 # Cycle average of tags in use
-system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.332913 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 41962544 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 41962544 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 41962544 # number of overall hits
-system.cpu.dcache.overall_hits::total 41962544 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 689 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 689 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1789 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
-system.cpu.dcache.overall_misses::total 1789 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 35501000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 35501000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 60164000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 60164000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 95665000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 95665000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 95665000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 95665000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 41964333 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 41964333 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 41964333 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 41964333 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51525.399129 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 51525.399129 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54694.545455 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54694.545455 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 53474.007826 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 53474.007826 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
-system.cpu.dcache.writebacks::total 16 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 689 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 689 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1789 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 1675.655740 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1380 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 40 # number of replacements
+system.cpu.dcache.tagsinuse 1363.611259 # Cycle average of tags in use
+system.cpu.dcache.total_refs 42007358 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1789 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 23480.915595 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.332913 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 41962544 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 41962544 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 41962544 # number of overall hits
+system.cpu.dcache.overall_hits::total 41962544 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 689 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 689 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 1789 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1789 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
+system.cpu.dcache.overall_misses::total 1789 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 35501000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 35501000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 60164000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 60164000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 95665000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 95665000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 95665000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 95665000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 29600046 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 29600046 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 41964333 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 41964333 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 41964333 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 41964333 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51525.399129 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 51525.399129 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54694.545455 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54694.545455 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 53474.007826 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 53474.007826 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 53474.007826 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
+system.cpu.dcache.writebacks::total 16 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 689 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 689 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1789 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1789 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34123000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 34123000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57964000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 57964000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 92087000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92087000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 92087000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000043 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000043 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49525.399129 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52694.545455 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 51474.007826 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/twolf
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:21:10
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 15:49:57
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2
sim_ticks 96722945000 # Number of ticks simulated
final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2917410 # Simulator instruction rate (inst/s)
-host_op_rate 2917413 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1458714810 # Simulator tick rate (ticks/s)
-host_mem_usage 226640 # Number of bytes of host memory used
-host_seconds 66.31 # Real time elapsed on the host
+host_inst_rate 1868868 # Simulator instruction rate (inst/s)
+host_op_rate 1868870 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 934440193 # Simulator tick rate (ticks/s)
+host_mem_usage 277724 # Number of bytes of host memory used
+host_seconds 103.51 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
env=
errout=cerr
euid=100
-executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/twolf
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
+bandwidth=73.000000
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
latency=30000
latency_var=0
+Redirecting stdout to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:04:37
-gem5 started Aug 13 2012 18:21:48
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:12:46
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
info: Increasing stack size by one page.
-122 123 124 Exiting @ tick 270628667000 because target called exit()
+122 123 124 Exiting @ tick 270563082000 because target called exit()
sim_ticks 270563082000 # Number of ticks simulated
final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 662631 # Simulator instruction rate (inst/s)
-host_op_rate 662631 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 926794797 # Simulator tick rate (ticks/s)
-host_mem_usage 226156 # Number of bytes of host memory used
-host_seconds 291.93 # Real time elapsed on the host
+host_inst_rate 1012263 # Simulator instruction rate (inst/s)
+host_op_rate 1012264 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1415810765 # Simulator tick rate (ticks/s)
+host_mem_usage 286308 # Number of bytes of host memory used
+host_seconds 191.10 # Real time elapsed on the host
sim_insts 193444518 # Number of instructions simulated
sim_ops 193444756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2 # number of replacements
-system.cpu.dcache.tagsinuse 1237.203941 # Cycle average of tags in use
-system.cpu.dcache.total_refs 76732337 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 48688.031091 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.302052 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits
-system.cpu.dcache.overall_hits::total 76709932 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses
-system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses
-system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses
-system.cpu.dcache.overall_misses::total 1575 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 2 # number of writebacks
-system.cpu.dcache.writebacks::total 2 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26394000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 26394000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57081000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 57081000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency::total 53000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83475000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 83475000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2678.340865 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 2 # number of replacements
+system.cpu.dcache.tagsinuse 1237.203941 # Cycle average of tags in use
+system.cpu.dcache.total_refs 76732337 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 48688.031091 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.302052 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits
+system.cpu.dcache.overall_hits::total 76709932 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses
+system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses
+system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses
+system.cpu.dcache.overall_misses::total 1575 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 2 # number of writebacks
+system.cpu.dcache.writebacks::total 2 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26394000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 26394000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57081000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 57081000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total 53000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83475000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 83475000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/cpu2000/binaries/x86/linux/twolf
+executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:20:54
-gem5 started Jan 4 2013 23:04:52
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 19:08:30
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
+Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
+Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 82648140000 # Number of ticks simulated
final_tick 82648140000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 100436 # Simulator instruction rate (inst/s)
-host_op_rate 168340 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 62851400 # Simulator tick rate (ticks/s)
-host_mem_usage 270508 # Number of bytes of host memory used
-host_seconds 1314.98 # Real time elapsed on the host
+host_inst_rate 59257 # Simulator instruction rate (inst/s)
+host_op_rate 99320 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37082179 # Simulator tick rate (ticks/s)
+host_mem_usage 321776 # Number of bytes of host memory used
+host_seconds 2228.78 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221362961 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 217728 # Number of bytes read from this memory
system.physmem.readRowHitRate 88.67 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 15454021.88 # Average gap between requests
+system.cpu.branchPred.lookups 19953215 # Number of BP lookups
+system.cpu.branchPred.condPredicted 19953215 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2011335 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 13840594 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 13098591 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 94.638937 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 165296281 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 19953215 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 19953215 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 2011335 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 13840594 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 13098591 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 25831000 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 218891152 # Number of instructions fetch has processed
system.cpu.fetch.Branches 19953215 # Number of branches that fetch encountered
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 00:50:19
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:05:52
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
sim_ticks 131393067500 # Number of ticks simulated
final_tick 131393067500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 889897 # Simulator instruction rate (inst/s)
-host_op_rate 1491546 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 885328041 # Simulator tick rate (ticks/s)
-host_mem_usage 275216 # Number of bytes of host memory used
-host_seconds 148.41 # Real time elapsed on the host
+host_inst_rate 897941 # Simulator instruction rate (inst/s)
+host_op_rate 1505028 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 893330062 # Simulator tick rate (ticks/s)
+host_mem_usage 308196 # Number of bytes of host memory used
+host_seconds 147.08 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221362962 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 01:16:52
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 16:30:54
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
sim_ticks 250953956000 # Number of ticks simulated
final_tick 250953956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 472281 # Simulator instruction rate (inst/s)
-host_op_rate 791585 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 897401473 # Simulator tick rate (ticks/s)
-host_mem_usage 283668 # Number of bytes of host memory used
-host_seconds 279.65 # Real time elapsed on the host
+host_inst_rate 580885 # Simulator instruction rate (inst/s)
+host_op_rate 973614 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1103763503 # Simulator tick rate (ticks/s)
+host_mem_usage 316652 # Number of bytes of host memory used
+host_seconds 227.36 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221362962 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 41 # number of replacements
-system.cpu.dcache.tagsinuse 1363.457576 # Cycle average of tags in use
-system.cpu.dcache.total_refs 77195830 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 40522.745407 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 1363.457576 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 77195830 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 77195830 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 77195830 # number of overall hits
-system.cpu.dcache.overall_hits::total 77195830 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses
-system.cpu.dcache.overall_misses::total 1905 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 56682004 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 77197735 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 77197735 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 77197735 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 77197735 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 7 # number of writebacks
-system.cpu.dcache.writebacks::total 7 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2058.178694 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1862 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 41 # number of replacements
+system.cpu.dcache.tagsinuse 1363.457576 # Cycle average of tags in use
+system.cpu.dcache.total_refs 77195830 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 40522.745407 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 1363.457576 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.332875 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 56681677 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 56681677 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 77195830 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 77195830 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 77195830 # number of overall hits
+system.cpu.dcache.overall_hits::total 77195830 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses
+system.cpu.dcache.overall_misses::total 1905 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 56682004 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 56682004 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 77197735 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 77197735 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 77197735 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 77197735 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 7 # number of writebacks
+system.cpu.dcache.writebacks::total 7 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+clock=1000
+console=/scratch/nilay/GEM5/system/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
[system.bridge]
type=Bridge
+clock=1000
delay=50000
-nack_delay=4000
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
-write_ack=false
master=system.iobus.slave[0]
slave=system.membus.master[0]
[system.cpu0]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu0.tracer
width=1
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
[system.cpu0.interrupts]
type=AlphaInterrupts
+[system.cpu0.isa]
+type=AlphaISA
+
[system.cpu0.itb]
type=AlphaTLB
size=48
[system.cpu1]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=1
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu1.tracer
width=1
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
[system.cpu1.interrupts]
type=AlphaInterrupts
+[system.cpu1.isa]
+type=AlphaISA
+
[system.cpu1.itb]
type=AlphaTLB
size=48
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
[system.iocache]
type=BaseCache
-addr_ranges=0:8589934591
+addr_ranges=0:134217727
assoc=8
block_size=64
+clock=1000
forward_snoops=false
-hash_delay=1
+hit_latency=50
is_top_level=true
-latency=50000
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=92
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=4194304
-subblock_size=0
system=system
-tgts_per_mshr=16
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
+mem_side=system.membus.slave[1]
[system.membus]
type=CoherentBus
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=0
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=true
ret_data16=65535
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[1]
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
[system.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
width=8
[system.tsunami.backdoor]
type=AlphaBackdoor
+clock=1000
cpu=system.cpu0
disk=system.simple_disk
pio_addr=8804682956800
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
[system.tsunami.cchip]
type=TsunamiCChip
+clock=1000
pio_addr=8803072344064
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[0]
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
-clock=0
+clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false
dma_write_factor=0
hardware_address=00:90:00:00:00:01
intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=1
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
rss=false
rx_delay=1000000
[system.tsunami.fake_OROM]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8796093677568
-pio_latency=1000
+pio_latency=100000
pio_size=393216
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_ata0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848432
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_ata1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848304
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_addr]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848569
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848451
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848515
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848579
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848643
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848707
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read5]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848771
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read6]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848835
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read7]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848899
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_write]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615850617
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_ppc]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848891
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_sm_chip]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848816
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848696
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848936
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848680
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848944
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fb]
type=BadDevice
+clock=1000
devicename=FrameBuffer
pio_addr=8804615848912
-pio_latency=1000
+pio_latency=100000
system=system
pio=system.iobus.master[21]
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
+clock=1000
config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=0
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
system=system
config=system.iobus.master[26]
[system.tsunami.io]
type=TsunamiIO
+clock=1000
frequency=976562500
pio_addr=8804615847936
-pio_latency=1000
+pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
[system.tsunami.pchip]
type=TsunamiPChip
+clock=1000
pio_addr=8802535473152
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[1]
[system.tsunami.pciconfig]
type=PciConfigAll
bus=0
-pio_latency=1
+clock=1000
+pio_latency=30000
platform=system.tsunami
size=16777216
system=system
[system.tsunami.uart]
type=Uart8250
+clock=1000
pio_addr=8804615848952
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
+Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 26 2012 21:20:05
-gem5 started Jul 26 2012 21:40:04
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:01:11
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 97861500
-Exiting @ tick 1870335522500 because m5_exit instruction encountered
+Exiting @ tick 1870325497500 because m5_exit instruction encountered
sim_ticks 1870325497500 # Number of ticks simulated
final_tick 1870325497500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1528286 # Simulator instruction rate (inst/s)
-host_op_rate 1528286 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45262701867 # Simulator tick rate (ticks/s)
-host_mem_usage 296828 # Number of bytes of host memory used
-host_seconds 41.32 # Real time elapsed on the host
+host_inst_rate 2356651 # Simulator instruction rate (inst/s)
+host_op_rate 2356650 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69796056257 # Simulator tick rate (ticks/s)
+host_mem_usage 349376 # Number of bytes of host memory used
+host_seconds 26.80 # Real time elapsed on the host
sim_insts 63151114 # Number of instructions simulated
sim_ops 63151114 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 760896 # Number of bytes read from this memory
[system]
type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
+children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+clock=1000
+console=/scratch/nilay/GEM5/system/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
[system.bridge]
type=Bridge
+clock=1000
delay=50000
-nack_delay=4000
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
-write_ack=false
master=system.iobus.slave[0]
slave=system.membus.master[0]
[system.cpu]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
+[system.cpu.l2cache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
[system.cpu.tracer]
type=ExeTracer
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
[system.iocache]
type=BaseCache
-addr_ranges=0:8589934591
+addr_ranges=0:134217727
assoc=8
block_size=64
+clock=1000
forward_snoops=false
-hash_delay=1
+hit_latency=50
is_top_level=true
-latency=50000
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
-mem_side=system.membus.slave[1]
-
-[system.l2c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-prefetch_on_access=false
-prefetcher=Null
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-system=system
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
[system.membus]
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=0
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=true
ret_data16=65535
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[1]
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
output=true
port=3456
-[system.toL2Bus]
-type=CoherentBus
-block_size=64
-clock=1000
-header_cycles=1
-use_default_range=false
-width=8
-master=system.l2c.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
[system.tsunami]
type=Tsunami
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
[system.tsunami.backdoor]
type=AlphaBackdoor
+clock=1000
cpu=system.cpu
disk=system.simple_disk
pio_addr=8804682956800
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
[system.tsunami.cchip]
type=TsunamiCChip
+clock=1000
pio_addr=8803072344064
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[0]
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
-clock=0
+clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false
dma_write_factor=0
hardware_address=00:90:00:00:00:01
intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=1
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
rss=false
rx_delay=1000000
[system.tsunami.fake_OROM]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8796093677568
-pio_latency=1000
+pio_latency=100000
pio_size=393216
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_ata0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848432
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_ata1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848304
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_addr]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848569
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848451
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848515
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848579
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848643
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848707
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read5]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848771
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read6]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848835
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read7]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848899
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_write]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615850617
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_ppc]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848891
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_sm_chip]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848816
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848696
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848936
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848680
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848944
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fb]
type=BadDevice
+clock=1000
devicename=FrameBuffer
pio_addr=8804615848912
-pio_latency=1000
+pio_latency=100000
system=system
pio=system.iobus.master[21]
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
+clock=1000
config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=0
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
system=system
config=system.iobus.master[26]
[system.tsunami.io]
type=TsunamiIO
+clock=1000
frequency=976562500
pio_addr=8804615847936
-pio_latency=1000
+pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
[system.tsunami.pchip]
type=TsunamiPChip
+clock=1000
pio_addr=8802535473152
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[1]
[system.tsunami.pciconfig]
type=PciConfigAll
bus=0
-pio_latency=1
+clock=1000
+pio_latency=30000
platform=system.tsunami
size=16777216
system=system
[system.tsunami.uart]
type=Uart8250
+clock=1000
pio_addr=8804615848952
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
+Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 26 2012 21:20:05
-gem5 started Jul 26 2012 21:39:53
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:01:49
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1829332258000 because m5_exit instruction encountered
+Exiting @ tick 1829330593000 because m5_exit instruction encountered
sim_ticks 1829330593000 # Number of ticks simulated
final_tick 1829330593000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1577718 # Simulator instruction rate (inst/s)
-host_op_rate 1577717 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48072530632 # Simulator tick rate (ticks/s)
-host_mem_usage 294780 # Number of bytes of host memory used
-host_seconds 38.05 # Real time elapsed on the host
+host_inst_rate 1133415 # Simulator instruction rate (inst/s)
+host_op_rate 1133413 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 34534714924 # Simulator tick rate (ticks/s)
+host_mem_usage 347332 # Number of bytes of host memory used
+host_seconds 52.97 # Real time elapsed on the host
sim_insts 60037737 # Number of instructions simulated
sim_ops 60037737 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 857856 # Number of bytes read from this memory
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 2042707 # number of replacements
-system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits
-system.cpu.dcache.overall_hits::total 13655968 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
-system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
-system.cpu.dcache.writebacks::total 833491 # number of writebacks
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 992297 # number of replacements
system.cpu.l2cache.tagsinuse 65424.375500 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2433228 # Total number of references to valid blocks.
system.cpu.l2cache.writebacks::writebacks 74287 # number of writebacks
system.cpu.l2cache.writebacks::total 74287 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 2042707 # number of replacements
+system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
+system.cpu.dcache.total_refs 14038405 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 2043219 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 6.870729 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 7807769 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7807769 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 5848199 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 5848199 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 199281 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 199281 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 13655968 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 13655968 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 13655968 # number of overall hits
+system.cpu.dcache.overall_hits::total 13655968 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 1721709 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1721709 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 304365 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 304365 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
+system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data 9529478 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 9529478 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 6152564 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6152564 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200302 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 200302 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 199281 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 199281 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 15682042 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 15682042 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 15682042 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 15682042 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085681 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085681 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
+system.cpu.dcache.writebacks::total 833491 # number of writebacks
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+clock=1000
+console=/scratch/nilay/GEM5/system/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
+mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
[system.bridge]
type=Bridge
+clock=1000
delay=50000
-nack_delay=4000
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
-write_ack=false
master=system.iobus.slave[0]
slave=system.membus.master[0]
[system.cpu0]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu0.tracer
workload=
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
[system.cpu0.interrupts]
type=AlphaInterrupts
+[system.cpu0.isa]
+type=AlphaISA
+
[system.cpu0.itb]
type=AlphaTLB
size=48
[system.cpu1]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=1
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu1.tracer
workload=
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
[system.cpu1.interrupts]
type=AlphaInterrupts
+[system.cpu1.isa]
+type=AlphaISA
+
[system.cpu1.itb]
type=AlphaTLB
size=48
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
[system.iocache]
type=BaseCache
-addr_ranges=0:8589934591
+addr_ranges=0:134217727
assoc=8
block_size=64
+clock=1000
forward_snoops=false
-hash_delay=1
+hit_latency=50
is_top_level=true
-latency=50000
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
-mem_side=system.membus.slave[1]
+mem_side=system.membus.slave[2]
[system.l2c]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=20
is_top_level=false
-latency=10000
max_miss_count=0
-mshrs=92
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=20
size=4194304
-subblock_size=0
system=system
-tgts_per_mshr=16
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[2]
+mem_side=system.membus.slave[1]
[system.membus]
type=CoherentBus
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=0
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=true
ret_data16=65535
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[1]
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
[system.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
width=8
[system.tsunami.backdoor]
type=AlphaBackdoor
+clock=1000
cpu=system.cpu0
disk=system.simple_disk
pio_addr=8804682956800
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
[system.tsunami.cchip]
type=TsunamiCChip
+clock=1000
pio_addr=8803072344064
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[0]
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
-clock=0
+clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false
dma_write_factor=0
hardware_address=00:90:00:00:00:01
intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=1
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
rss=false
rx_delay=1000000
[system.tsunami.fake_OROM]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8796093677568
-pio_latency=1000
+pio_latency=100000
pio_size=393216
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_ata0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848432
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_ata1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848304
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_addr]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848569
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848451
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848515
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848579
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848643
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848707
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read5]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848771
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read6]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848835
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read7]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848899
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_write]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615850617
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_ppc]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848891
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_sm_chip]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848816
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848696
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848936
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848680
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848944
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fb]
type=BadDevice
+clock=1000
devicename=FrameBuffer
pio_addr=8804615848912
-pio_latency=1000
+pio_latency=100000
system=system
pio=system.iobus.master[21]
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
+clock=1000
config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=0
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
system=system
config=system.iobus.master[26]
[system.tsunami.io]
type=TsunamiIO
+clock=1000
frequency=976562500
pio_addr=8804615847936
-pio_latency=1000
+pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
[system.tsunami.pchip]
type=TsunamiPChip
+clock=1000
pio_addr=8802535473152
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[1]
[system.tsunami.pciconfig]
type=PciConfigAll
bus=0
-pio_latency=1
+clock=1000
+pio_latency=30000
platform=system.tsunami
size=16777216
system=system
[system.tsunami.uart]
type=Uart8250
+clock=1000
pio_addr=8804615848952
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
+Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 26 2012 21:20:05
-gem5 started Jul 26 2012 21:40:05
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:46:42
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-info: Launching CPU 1 @ 573593000
-Exiting @ tick 1954209529000 because m5_exit instruction encountered
+info: Launching CPU 1 @ 608846000
+Exiting @ tick 1950813955500 because m5_exit instruction encountered
sim_ticks 1950813955500 # Number of ticks simulated
final_tick 1950813955500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 770652 # Simulator instruction rate (inst/s)
-host_op_rate 770652 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 24652738853 # Simulator tick rate (ticks/s)
-host_mem_usage 325660 # Number of bytes of host memory used
-host_seconds 79.13 # Real time elapsed on the host
+host_inst_rate 720692 # Simulator instruction rate (inst/s)
+host_op_rate 720692 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 23054537293 # Simulator tick rate (ticks/s)
+host_mem_usage 378432 # Number of bytes of host memory used
+host_seconds 84.62 # Real time elapsed on the host
sim_insts 60983017 # Number of instructions simulated
sim_ops 60983017 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 827264 # Number of bytes read from this memory
[system]
type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
+children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/dist/m5/system/binaries/console
+clock=1000
+console=/scratch/nilay/GEM5/system/binaries/console
init_param=0
-kernel=/dist/m5/system/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
+mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/dist/m5/system/binaries/ts_osfpal
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
[system.bridge]
type=Bridge
+clock=1000
delay=50000
-nack_delay=4000
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
-write_ack=false
master=system.iobus.slave[0]
slave=system.membus.master[0]
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
-phase=0
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=AlphaTLB
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
+clock=500
forward_snoops=true
-hash_delay=1
+hit_latency=2
is_top_level=true
-latency=1000
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
+[system.cpu.l2cache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
+
[system.cpu.tracer]
type=ExeTracer
[system.disk0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
[system.iocache]
type=BaseCache
-addr_ranges=0:8589934591
+addr_ranges=0:134217727
assoc=8
block_size=64
+clock=1000
forward_snoops=false
-hash_delay=1
+hit_latency=50
is_top_level=true
-latency=50000
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
-mem_side=system.membus.slave[1]
-
-[system.l2c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=8
-block_size=64
-forward_snoops=true
-hash_delay=1
-is_top_level=false
-latency=10000
-max_miss_count=0
-mshrs=92
-prefetch_on_access=false
-prefetcher=Null
-prioritizeRequests=false
-repl=Null
-size=4194304
-subblock_size=0
-system=system
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
[system.membus]
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=0
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=true
ret_data16=65535
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=false
-file=
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[1]
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[system.terminal]
output=true
port=3456
-[system.toL2Bus]
-type=CoherentBus
-block_size=64
-clock=1000
-header_cycles=1
-use_default_range=false
-width=8
-master=system.l2c.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
-
[system.tsunami]
type=Tsunami
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
[system.tsunami.backdoor]
type=AlphaBackdoor
+clock=1000
cpu=system.cpu
disk=system.simple_disk
pio_addr=8804682956800
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
[system.tsunami.cchip]
type=TsunamiCChip
+clock=1000
pio_addr=8803072344064
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[0]
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
-clock=0
+clock=2000
config_latency=20000
dma_data_free=false
dma_desc_free=false
dma_write_factor=0
hardware_address=00:90:00:00:00:01
intr_delay=10000000
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=1
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
rss=false
rx_delay=1000000
[system.tsunami.fake_OROM]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8796093677568
-pio_latency=1000
+pio_latency=100000
pio_size=393216
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_ata0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848432
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_ata1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848304
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_addr]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848569
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read0]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848451
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848515
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848579
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848643
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848707
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read5]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848771
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read6]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848835
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_read7]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848899
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_pnp_write]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615850617
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_ppc]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848891
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_sm_chip]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848816
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart1]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848696
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart2]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848936
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart3]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848680
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fake_uart4]
type=IsaFake
+clock=1000
fake_mem=false
pio_addr=8804615848944
-pio_latency=1000
+pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
[system.tsunami.fb]
type=BadDevice
+clock=1000
devicename=FrameBuffer
pio_addr=8804615848912
-pio_latency=1000
+pio_latency=100000
system=system
pio=system.iobus.master[21]
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
+clock=1000
config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
io_shift=0
-max_backoff_delay=10000000
-min_backoff_delay=4000
pci_bus=0
pci_dev=0
pci_func=0
-pio_latency=1000
+pio_latency=30000
platform=system.tsunami
system=system
config=system.iobus.master[26]
[system.tsunami.io]
type=TsunamiIO
+clock=1000
frequency=976562500
pio_addr=8804615847936
-pio_latency=1000
+pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
[system.tsunami.pchip]
type=TsunamiPChip
+clock=1000
pio_addr=8802535473152
-pio_latency=1000
+pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[1]
[system.tsunami.pciconfig]
type=PciConfigAll
bus=0
-pio_latency=1
+clock=1000
+pio_latency=30000
platform=system.tsunami
size=16777216
system=system
[system.tsunami.uart]
type=Uart8250
+clock=1000
pio_addr=8804615848952
-pio_latency=1000
+pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
+Redirecting stdout to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 26 2012 21:20:05
-gem5 started Jul 26 2012 21:40:05
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:32:52
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1920853042000 because m5_exit instruction encountered
+Exiting @ tick 1910582068000 because m5_exit instruction encountered
sim_ticks 1910582068000 # Number of ticks simulated
final_tick 1910582068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 942466 # Simulator instruction rate (inst/s)
-host_op_rate 942466 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 32082735017 # Simulator tick rate (ticks/s)
-host_mem_usage 321492 # Number of bytes of host memory used
-host_seconds 59.55 # Real time elapsed on the host
+host_inst_rate 951839 # Simulator instruction rate (inst/s)
+host_op_rate 951839 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32401800424 # Simulator tick rate (ticks/s)
+host_mem_usage 374212 # Number of bytes of host memory used
+host_seconds 58.97 # Real time elapsed on the host
sim_insts 56125446 # Number of instructions simulated
sim_ops 56125446 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11647.123628 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11647.123628 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1389800 # number of replacements
-system.cpu.dcache.tagsinuse 511.980808 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14036386 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 1390312 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 10.095853 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 93442000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.980808 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999963 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999963 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 7806239 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7806239 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 5847887 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 5847887 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 183020 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 183020 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 13654126 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13654126 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 13654126 # number of overall hits
-system.cpu.dcache.overall_hits::total 13654126 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 1068876 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1068876 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 304232 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 304232 # number of WriteReq misses
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-system.cpu.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13220.519073 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13220.519073 # average LoadLockedReq miss latency
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-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 336061 # number of replacements
system.cpu.l2cache.tagsinuse 65323.847661 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2445310 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 1389800 # number of replacements
+system.cpu.dcache.tagsinuse 511.980808 # Cycle average of tags in use
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+system.cpu.dcache.warmup_cycle 93442000 # Cycle when the warmup percentage was hit.
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+system.cpu.dcache.ReadReq_avg_miss_latency::total 21247.653610 # average ReadReq miss latency
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+system.cpu.dcache.WriteReq_avg_miss_latency::total 28263.090339 # average WriteReq miss latency
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+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13220.519073 # average LoadLockedReq miss latency
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+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11220.519073 # average LoadLockedReq mshr miss latency
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+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20802.025405 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20802.025405 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/gem5/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
[system.cpu1]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=1
+Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simout
+Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 4 2013 23:29:32
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:45:38
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 912096763500 because m5_exit instruction encountered
sim_ticks 912096763500 # Number of ticks simulated
final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 599236 # Simulator instruction rate (inst/s)
-host_op_rate 771515 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 8869004975 # Simulator tick rate (ticks/s)
-host_mem_usage 384344 # Number of bytes of host memory used
-host_seconds 102.84 # Real time elapsed on the host
+host_inst_rate 1193297 # Simulator instruction rate (inst/s)
+host_op_rate 1536367 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17661410361 # Simulator tick rate (ticks/s)
+host_mem_usage 435356 # Number of bytes of host memory used
+host_seconds 51.64 # Real time elapsed on the host
sim_insts 61625970 # Number of instructions simulated
sim_ops 79343340 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 70658 # number of replacements
system.l2c.tagsinuse 51560.149653 # Cycle average of tags in use
system.l2c.total_refs 1623339 # Total number of references to valid blocks.
[system]
type=LinuxArmSystem
-children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/projects/pd/randd/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1
+clock=1000
dtb_filename=
early_kernel_symbols=false
+enable_context_switch_stats_dump=false
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
+mem_ranges=0:134217727
memories=system.physmem system.realview.nvmem
-midr_regval=890224640
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.bridge]
type=Bridge
-clock=1
+clock=1000
delay=50000
ranges=268435456:520093695 1073741824:1610612735
req_size=16
[system.cf0.image.child]
type=RawDiskImage
-image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
-mem_side=system.toL2Bus.slave[1]
+mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dtb]
type=ArmTLB
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[3]
+port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=BaseCache
addr_ranges=0:18446744073709551615
assoc=1
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
-mem_side=system.toL2Bus.slave[0]
+mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
-port=system.toL2Bus.slave[2]
+port=system.cpu.toL2Bus.slave[2]
+
+[system.cpu.l2cache]
+type=BaseCache
+addr_ranges=0:18446744073709551615
+assoc=8
+block_size=64
+clock=500
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+size=4194304
+system=system
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.master[0]
+mem_side=system.membus.slave[1]
+
+[system.cpu.toL2Bus]
+type=CoherentBus
+block_size=64
+clock=500
+header_cycles=1
+use_default_range=false
+width=32
+master=system.cpu.l2cache.cpu_side
+slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.cpu.tracer]
type=ExeTracer
[system.iocache]
type=BaseCache
-addr_ranges=0:268435455
+addr_ranges=0:134217727
assoc=8
block_size=64
-clock=1
+clock=1000
forward_snoops=false
-hash_delay=1
-hit_latency=50000
-is_top_level=false
+hit_latency=50
+is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=50000
+response_latency=50
size=1024
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[25]
-mem_side=system.membus.slave[1]
-
-[system.l2c]
-type=BaseCache
-addr_ranges=0:18446744073709551615
-assoc=8
-block_size=64
-clock=1
-forward_snoops=true
-hash_delay=1
-hit_latency=10000
-is_top_level=false
-max_miss_count=0
-mshrs=92
-prefetch_on_access=false
-prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
-size=4194304
-subblock_size=0
-system=system
-tgts_per_mshr=16
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[2]
[system.membus]
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
-slave=system.system_port system.iocache.mem_side system.l2c.mem_side
+slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=0
pio_latency=100000
pio=system.membus.default
[system.physmem]
-type=SimpleMemory
-bandwidth=73.000000
-clock=1
+type=SimpleDRAM
+addr_mapping=openmap
+banks_per_rank=8
+clock=1000
conf_table_reported=true
in_addr_map=true
-latency=30000
-latency_var=0
+lines_per_rowbuffer=64
+mem_sched_policy=fcfs
null=false
+page_policy=open
range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+tBURST=4000
+tCL=14000
+tRCD=14000
+tREFI=7800000
+tRFC=300000
+tRP=14000
+tWTR=1000
+write_buffer_size=32
+write_thresh_perc=70
zero=false
port=system.membus.master[2]
[system.realview.a9scu]
type=A9SCU
-clock=1
+clock=1000
pio_addr=520093696
pio_latency=100000
system=system
[system.realview.aaci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268451840
pio_latency=100000
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
-clock=1
+clock=1000
config_latency=20000
ctrl_offset=2
disks=system.cf0
[system.realview.clcd]
type=Pl111
amba_id=1315089
-clock=41667
+clock=1000
gic=system.realview.gic
int_num=55
pio_addr=268566528
pio_latency=10000
+pixel_clock=41667
system=system
vnc=system.vncserver
dma=system.iobus.slave[1]
[system.realview.dmac_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268632064
pio_latency=100000
[system.realview.flash_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=true
pio_addr=1073741824
pio_latency=100000
[system.realview.gic]
type=Gic
-clock=1
+clock=1000
cpu_addr=520093952
cpu_pio_delay=10000
dist_addr=520097792
[system.realview.gpio0_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268513280
pio_latency=100000
[system.realview.gpio1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268517376
pio_latency=100000
[system.realview.gpio2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268521472
pio_latency=100000
[system.realview.kmi0]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=52
[system.realview.kmi1]
type=Pl050
amba_id=1314896
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=1000000
int_num=53
[system.realview.l2x0_fake]
type=IsaFake
-clock=1
+clock=1000
fake_mem=false
pio_addr=520101888
pio_latency=100000
[system.realview.mmc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268455936
pio_latency=100000
[system.realview.nvmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
[system.realview.realview_io]
type=RealViewCtrl
-clock=1
+clock=1000
idreg=0
pio_addr=268435456
pio_latency=100000
[system.realview.rtc]
type=PL031
amba_id=3412017
-clock=1
+clock=1000
gic=system.realview.gic
int_delay=100000
int_num=42
[system.realview.sci_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268492800
pio_latency=100000
[system.realview.smc_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=269357056
pio_latency=100000
[system.realview.sp810_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=true
pio_addr=268439552
pio_latency=100000
[system.realview.ssp_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268488704
pio_latency=100000
[system.realview.timer0]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
[system.realview.timer1]
type=Sp804
amba_id=1316868
-clock=1
+clock=1000
clock0=1000000
clock1=1000000
gic=system.realview.gic
[system.realview.uart]
type=Pl011
-clock=1
+clock=1000
end_on_eot=false
gic=system.realview.gic
int_delay=100000
[system.realview.uart1_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268476416
pio_latency=100000
[system.realview.uart2_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268480512
pio_latency=100000
[system.realview.uart3_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268484608
pio_latency=100000
[system.realview.watchdog_fake]
type=AmbaFake
amba_id=0
-clock=1
+clock=1000
ignore_access=false
pio_addr=268500992
pio_latency=100000
output=true
port=3456
-[system.toL2Bus]
-type=CoherentBus
-block_size=64
-clock=1000
-header_cycles=1
-use_default_range=false
-width=8
-master=system.l2c.cpu_side
-slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
-
[system.vncserver]
type=VncServer
frame_capture=false
warn: instruction 'mcr dccmvau' unimplemented
warn: instruction 'mcr icimvau' unimplemented
warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
warn: instruction 'mcr bpiallis' unimplemented
hack: be nice to actually delete the event here
+Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:19:18
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:44:32
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2332810264000 because m5_exit instruction encountered
sim_ticks 2332810264000 # Number of ticks simulated
final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1184768 # Simulator instruction rate (inst/s)
-host_op_rate 1523538 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45752340761 # Simulator tick rate (ticks/s)
-host_mem_usage 382236 # Number of bytes of host memory used
-host_seconds 50.99 # Real time elapsed on the host
+host_inst_rate 1101050 # Simulator instruction rate (inst/s)
+host_op_rate 1415882 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 42519386287 # Simulator tick rate (ticks/s)
+host_mem_usage 435224 # Number of bytes of host memory used
+host_seconds 54.86 # Real time elapsed on the host
sim_insts 60408639 # Number of instructions simulated
sim_ops 77681819 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 623337 # number of replacements
-system.cpu.dcache.tagsinuse 511.997031 # Cycle average of tags in use
-system.cpu.dcache.total_refs 23628343 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 623849 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 37.875100 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits
-system.cpu.dcache.overall_hits::total 23142138 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses
-system.cpu.dcache.overall_misses::total 615611 # number of overall misses
-system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks
-system.cpu.dcache.writebacks::total 592643 # number of writebacks
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 62243 # number of replacements
system.cpu.l2cache.tagsinuse 50007.272909 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1669922 # Total number of references to valid blocks.
system.cpu.l2cache.writebacks::writebacks 57863 # number of writebacks
system.cpu.l2cache.writebacks::total 57863 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 623337 # number of replacements
+system.cpu.dcache.tagsinuse 511.997031 # Cycle average of tags in use
+system.cpu.dcache.total_refs 23628343 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 623849 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 37.875100 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits
+system.cpu.dcache.overall_hits::total 23142138 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses
+system.cpu.dcache.overall_misses::total 615611 # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.025912 # miss rate for overall accesses
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks
+system.cpu.dcache.writebacks::total 592643 # number of writebacks
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/gem5/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
[system.cpu1]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=1
+Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simout
+Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 4 2013 23:31:36
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:46:40
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1182882156500 because m5_exit instruction encountered
sim_ticks 1182882156500 # Number of ticks simulated
final_tick 1182882156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 184229 # Simulator instruction rate (inst/s)
-host_op_rate 234741 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3546252898 # Simulator tick rate (ticks/s)
-host_mem_usage 402168 # Number of bytes of host memory used
-host_seconds 333.56 # Real time elapsed on the host
+host_inst_rate 497131 # Simulator instruction rate (inst/s)
+host_op_rate 633435 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9569364300 # Simulator tick rate (ticks/s)
+host_mem_usage 452888 # Number of bytes of host memory used
+host_seconds 123.61 # Real time elapsed on the host
sim_insts 61450993 # Number of instructions simulated
sim_ops 78299715 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.readRowHitRate 99.61 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 96.12 # Row buffer hit rate for writes
system.physmem.avgGap 158232.25 # Average gap between requests
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s)
system.l2c.replacements 69442 # number of replacements
system.l2c.tagsinuse 53039.972087 # Cycle average of tags in use
system.l2c.total_refs 1672967 # Total number of references to valid blocks.
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
atags_addr=256
-boot_loader=/gem5/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
readfile=tests/halt.sh
[system.cf0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
+Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 4 2013 23:31:27
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:45:50
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2603634694000 because m5_exit instruction encountered
sim_ticks 2603634694000 # Number of ticks simulated
final_tick 2603634694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 156094 # Simulator instruction rate (inst/s)
-host_op_rate 198627 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6751306864 # Simulator tick rate (ticks/s)
-host_mem_usage 397752 # Number of bytes of host memory used
-host_seconds 385.65 # Real time elapsed on the host
+host_inst_rate 413538 # Simulator instruction rate (inst/s)
+host_op_rate 526220 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17886148072 # Simulator tick rate (ticks/s)
+host_mem_usage 448796 # Number of bytes of host memory used
+host_seconds 145.57 # Real time elapsed on the host
sim_insts 60197457 # Number of instructions simulated
sim_ops 76600355 # Number of ops (including micro ops) simulated
-system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 96.74 # Row buffer hit rate for writes
system.physmem.avgGap 159677.30 # Average gap between requests
+system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
atags_addr=256
-boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
clock=1000
dtb_filename=
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=atomic
memories=system.physmem system.realview.nvmem
multi_proc=true
num_work_ids=16
-panic_on_oops=true
-panic_on_panic=true
readfile=tests/halt.sh
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
-image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
type=AtomicSimpleCPU
children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
[system.cpu1]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
+Redirecting stdout to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 11 2012 16:28:23
-gem5 started Dec 11 2012 16:28:36
-gem5 executing on e103721-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:48:26
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Switching CPUs...
sim_ticks 2332810256000 # Number of ticks simulated
final_tick 2332810256000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 669803 # Simulator instruction rate (inst/s)
-host_op_rate 861325 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 25865872844 # Simulator tick rate (ticks/s)
-host_mem_usage 384756 # Number of bytes of host memory used
-host_seconds 90.19 # Real time elapsed on the host
+host_inst_rate 1011951 # Simulator instruction rate (inst/s)
+host_op_rate 1301307 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 39078665084 # Simulator tick rate (ticks/s)
+host_mem_usage 435224 # Number of bytes of host memory used
+host_seconds 59.70 # Real time elapsed on the host
sim_insts 60408639 # Number of instructions simulated
sim_ops 77681819 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory
[system.cpu]
type=AtomicSimpleCPU
children=dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 21:50:34
-gem5 started Sep 10 2012 21:50:39
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:32:27
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
warning: add_child('terminal'): child 'terminal' already has parent
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5112043255000 because m5_exit instruction encountered
+Exiting @ tick 5112040970500 because m5_exit instruction encountered
sim_ticks 5112040970500 # Number of ticks simulated
final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1661898 # Simulator instruction rate (inst/s)
-host_op_rate 3402855 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42518772648 # Simulator tick rate (ticks/s)
-host_mem_usage 621064 # Number of bytes of host memory used
-host_seconds 120.23 # Real time elapsed on the host
+host_inst_rate 1071475 # Simulator instruction rate (inst/s)
+host_op_rate 2193921 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 27413112180 # Simulator tick rate (ticks/s)
+host_mem_usage 626876 # Number of bytes of host memory used
+host_seconds 186.48 # Real time elapsed on the host
sim_insts 199810242 # Number of instructions simulated
sim_ops 409125923 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory
[system.cpu]
type=TimingSimpleCPU
children=dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 10 2012 21:50:34
-gem5 started Sep 10 2012 21:50:39
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:02:27
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
warning: add_child('terminal'): child 'terminal' already has parent
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5196043137000 because m5_exit instruction encountered
+Exiting @ tick 5191112864000 because m5_exit instruction encountered
sim_ticks 5191112864000 # Number of ticks simulated
final_tick 5191112864000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1076481 # Simulator instruction rate (inst/s)
-host_op_rate 2075111 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 43574012985 # Simulator tick rate (ticks/s)
-host_mem_usage 651144 # Number of bytes of host memory used
-host_seconds 119.13 # Real time elapsed on the host
+host_inst_rate 663100 # Simulator instruction rate (inst/s)
+host_op_rate 1278245 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26841102406 # Simulator tick rate (ticks/s)
+host_mem_usage 658020 # Number of bytes of host memory used
+host_seconds 193.40 # Real time elapsed on the host
sim_insts 128244620 # Number of instructions simulated
sim_ops 247214608 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::pc.south_bridge.ide 2852352 # Number of bytes read from this memory
boot_cpu_frequency=250
boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000
-console=/gem5/dist/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
init_param=0
-kernel=/gem5/dist/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
mem_ranges=0:134217727
memories=drivesys.physmem
num_work_ids=16
-pal=/gem5/dist/binaries/ts_osfpal
-readfile=/gem5/configs/boot/netperf-server.rcS
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+readfile=/scratch/nilay/GEM5/gem5/configs/boot/netperf-server.rcS
symbolfile=
system_rev=1024
system_type=34
[drivesys.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=250
cpu_id=0
[drivesys.disk0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[drivesys.disk2]
[drivesys.disk2.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[drivesys.intrctrl]
[drivesys.simple_disk.disk]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[drivesys.terminal]
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
clock=1000
-console=/gem5/dist/binaries/console
+console=/scratch/nilay/GEM5/system/binaries/console
init_param=0
-kernel=/gem5/dist/binaries/vmlinux
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=atomic
mem_ranges=0:134217727
memories=testsys.physmem
num_work_ids=16
-pal=/gem5/dist/binaries/ts_osfpal
-readfile=/gem5/configs/boot/netperf-stream-client.rcS
+pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+readfile=/scratch/nilay/GEM5/gem5/configs/boot/netperf-stream-client.rcS
symbolfile=
system_rev=1024
system_type=34
[testsys.cpu]
type=AtomicSimpleCPU
children=dtb interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
[testsys.disk0.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[testsys.disk2]
[testsys.disk2.image.child]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[testsys.intrctrl]
[testsys.simple_disk.disk]
type=RawDiskImage
-image_file=/gem5/dist/disks/linux-latest.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
read_only=true
[testsys.terminal]
+Redirecting stdout to build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:09:21
-gem5 started Jan 4 2013 21:17:35
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:07:46
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
-info: kernel located at: /gem5/dist/binaries/vmlinux
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 4321612280500 because checkpoint
sim_ticks 200409284500 # Number of ticks simulated
final_tick 4321205328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 7091560 # Simulator instruction rate (inst/s)
-host_op_rate 7091556 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2715554324 # Simulator tick rate (ticks/s)
-host_mem_usage 465632 # Number of bytes of host memory used
-host_seconds 73.80 # Real time elapsed on the host
+host_inst_rate 13697441 # Simulator instruction rate (inst/s)
+host_op_rate 13697433 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5245128514 # Simulator tick rate (ticks/s)
+host_mem_usage 514692 # Number of bytes of host memory used
+host_seconds 38.21 # Real time elapsed on the host
sim_insts 523360203 # Number of instructions simulated
sim_ops 523360203 # Number of ops (including micro ops) simulated
testsys.physmem.bytes_read::cpu.inst 80888044 # Number of bytes read from this memory
sim_ticks 406952000 # Number of ticks simulated
final_tick 4321612280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3682675458 # Simulator instruction rate (inst/s)
-host_op_rate 3681807032 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2861829739 # Simulator tick rate (ticks/s)
-host_mem_usage 465632 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
+host_inst_rate 7058170696 # Simulator instruction rate (inst/s)
+host_op_rate 7056390513 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5484794115 # Simulator tick rate (ticks/s)
+host_mem_usage 514692 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 523432506 # Number of instructions simulated
sim_ops 523432506 # Number of ops (including micro ops) simulated
testsys.physmem.bytes_read::cpu.inst 144604 # Number of bytes read from this memory
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 11:20:12
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:17:23
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 18737000 # Number of ticks simulated
final_tick 18737000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 37767 # Simulator instruction rate (inst/s)
-host_op_rate 37763 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 110721753 # Simulator tick rate (ticks/s)
-host_mem_usage 213516 # Number of bytes of host memory used
-host_seconds 0.17 # Real time elapsed on the host
+host_inst_rate 42684 # Simulator instruction rate (inst/s)
+host_op_rate 42679 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 125129111 # Simulator tick rate (ticks/s)
+host_mem_usage 269636 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 39920.04 # Average gap between requests
+system.cpu.branchPred.lookups 1632 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1266 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 352 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 27.804107 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 126 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 37475 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 1632 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 1160 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 706 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 1266 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 352 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 27.804107 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5202 # Number of Reads from Int. Register File
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 11:20:12
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:07:24
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 15802500 # Number of ticks simulated
final_tick 15802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 38730 # Simulator instruction rate (inst/s)
-host_op_rate 38726 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 96032767 # Simulator tick rate (ticks/s)
-host_mem_usage 214332 # Number of bytes of host memory used
-host_seconds 0.16 # Real time elapsed on the host
+host_inst_rate 36566 # Simulator instruction rate (inst/s)
+host_op_rate 36562 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 90663114 # Simulator tick rate (ticks/s)
+host_mem_usage 270656 # Number of bytes of host memory used
+host_seconds 0.17 # Real time elapsed on the host
sim_insts 6372 # Number of instructions simulated
sim_ops 6372 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory
system.physmem.readRowHitRate 85.42 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 32145.79 # Average gap between requests
+system.cpu.branchPred.lookups 2927 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1718 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 517 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 2238 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 757 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 33.824844 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 420 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 77 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 31606 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2927 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1718 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 517 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 2238 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 757 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 420 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 77 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 8266 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 16744 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2927 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 16:51:51
-gem5 started Aug 13 2012 17:17:12
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:33:24
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 3208000 # Number of ticks simulated
final_tick 3208000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 57981 # Simulator instruction rate (inst/s)
-host_op_rate 57971 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 29099028 # Simulator tick rate (ticks/s)
-host_mem_usage 214184 # Number of bytes of host memory used
-host_seconds 0.11 # Real time elapsed on the host
+host_inst_rate 84722 # Simulator instruction rate (inst/s)
+host_op_rate 84702 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 42507676 # Simulator tick rate (ticks/s)
+host_mem_usage 261184 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=1
cpu_id=0
-Real time: Jan/14/2013 08:12:30
+Real time: Jan/23/2013 13:45:24
Profiler Stats
--------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
-Virtual_time_in_seconds: 0.51
-Virtual_time_in_minutes: 0.0085
-Virtual_time_in_hours: 0.000141667
-Virtual_time_in_days: 5.90278e-06
+Virtual_time_in_seconds: 0.52
+Virtual_time_in_minutes: 0.00866667
+Virtual_time_in_hours: 0.000144444
+Virtual_time_in_days: 6.01852e-06
Ruby_current_time: 143853
Ruby_start_time: 0
Ruby_cycles: 143853
-mbytes_resident: 54.9062
-mbytes_total: 274.051
-resident_ratio: 0.200393
+mbytes_resident: 55.0117
+mbytes_total: 274.062
+resident_ratio: 0.20077
ruby_cycles_executed: [ 143854 ]
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11208
+page_reclaims: 11797
page_faults: 0
swaps: 0
-block_inputs: 0
+block_inputs: 8
block_outputs: 88
Network Stats
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 1 2012 13:41:29
-gem5 started Sep 1 2012 13:43:15
-gem5 executing on doudou.cs.wisc.edu
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:45:23
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 143853 # Number of ticks simulated
final_tick 143853 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 34510 # Simulator instruction rate (inst/s)
-host_op_rate 34507 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 776735 # Simulator tick rate (ticks/s)
-host_mem_usage 280632 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
+host_inst_rate 28953 # Simulator instruction rate (inst/s)
+host_op_rate 28951 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 651686 # Simulator tick rate (ticks/s)
+host_mem_usage 280644 # Number of bytes of host memory used
+host_seconds 0.22 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 25600 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 16:51:51
-gem5 started Aug 13 2012 17:17:12
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:45:47
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 34409000 because target called exit()
+Exiting @ tick 32544000 because target called exit()
sim_ticks 32544000 # Number of ticks simulated
final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 68117 # Simulator instruction rate (inst/s)
-host_op_rate 68101 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 346770993 # Simulator tick rate (ticks/s)
-host_mem_usage 218620 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 97330 # Simulator instruction rate (inst/s)
+host_op_rate 97300 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 495402774 # Simulator tick rate (ticks/s)
+host_mem_usage 269640 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits
-system.cpu.dcache.overall_hits::total 1880 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
-system.cpu.dcache.overall_misses::total 168 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 184.497210 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 103.762109 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1880 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 11.190476 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.025333 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits
+system.cpu.dcache.overall_hits::total 1880 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
+system.cpu.dcache.overall_misses::total 168 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:02:14
-gem5 started Oct 30 2012 11:20:24
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:48:19
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 9059000 # Number of ticks simulated
final_tick 9059000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 28083 # Simulator instruction rate (inst/s)
-host_op_rate 28078 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 106544733 # Simulator tick rate (ticks/s)
-host_mem_usage 213348 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 18337 # Simulator instruction rate (inst/s)
+host_op_rate 18335 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69572663 # Simulator tick rate (ticks/s)
+host_mem_usage 270376 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
sim_ops 2387 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory
system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 33053.31 # Average gap between requests
+system.cpu.branchPred.lookups 1180 # Number of BP lookups
+system.cpu.branchPred.condPredicted 594 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 261 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 806 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 235 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 29.156328 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 227 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 39 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 18119 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 1180 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 594 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 261 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 806 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 235 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 227 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 39 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 4211 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 7069 # Number of instructions fetch has processed
system.cpu.fetch.Branches 1180 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 4 2012 11:50:11
-gem5 started Jun 4 2012 14:15:42
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:45:35
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 1297500 # Number of ticks simulated
final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 760610 # Simulator instruction rate (inst/s)
-host_op_rate 756680 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 379104629 # Simulator tick rate (ticks/s)
-host_mem_usage 204432 # Number of bytes of host memory used
-host_seconds 0.00 # Real time elapsed on the host
+host_inst_rate 34130 # Simulator instruction rate (inst/s)
+host_op_rate 34121 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17175609 # Simulator tick rate (ticks/s)
+host_mem_usage 260900 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=1
cpu_id=0
-Real time: Jan/14/2013 08:12:30
+Real time: Jan/23/2013 13:29:25
Profiler Stats
--------------
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.42
-Virtual_time_in_minutes: 0.007
-Virtual_time_in_hours: 0.000116667
-Virtual_time_in_days: 4.86111e-06
+Virtual_time_in_seconds: 0.59
+Virtual_time_in_minutes: 0.00983333
+Virtual_time_in_hours: 0.000163889
+Virtual_time_in_days: 6.8287e-06
Ruby_current_time: 52498
Ruby_start_time: 0
Ruby_cycles: 52498
-mbytes_resident: 52.5664
-mbytes_total: 272.77
-resident_ratio: 0.192757
+mbytes_resident: 52.6836
+mbytes_total: 272.781
+resident_ratio: 0.193178
ruby_cycles_executed: [ 52499 ]
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 10106
-page_faults: 0
+page_reclaims: 11189
+page_faults: 18
swaps: 0
-block_inputs: 0
-block_outputs: 88
+block_inputs: 1600
+block_outputs: 128
Network Stats
-------------
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
warn: Sockets disabled, not accepting gdb connections
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
hack: be nice to actually delete the event here
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 9 2012 13:25:55
-gem5 started Sep 9 2012 13:26:05
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:29:25
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
sim_ticks 52498 # Number of ticks simulated
final_tick 52498 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 26806 # Simulator instruction rate (inst/s)
-host_op_rate 26801 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 545876 # Simulator tick rate (ticks/s)
-host_mem_usage 279320 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 10060 # Simulator instruction rate (inst/s)
+host_op_rate 10059 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 204912 # Simulator tick rate (ticks/s)
+host_mem_usage 279332 # Number of bytes of host memory used
+host_seconds 0.26 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 2 2012 08:30:56
-gem5 started Jul 2 2012 09:08:33
-gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:46:30
+gem5 executing on ribera.cs.wisc.edu
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 17541000 because target called exit()
+Exiting @ tick 16524000 because target called exit()
sim_ticks 16524000 # Number of ticks simulated
final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 93431 # Simulator instruction rate (inst/s)
-host_op_rate 93371 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 598358642 # Simulator tick rate (ticks/s)
-host_mem_usage 217312 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 14244 # Simulator instruction rate (inst/s)
+host_op_rate 14243 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 91318433 # Simulator tick rate (ticks/s)
+host_mem_usage 268332 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 10432 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 47.437790 # Cycle average of tags in use
-system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.011581 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits
-system.cpu.dcache.overall_hits::total 627 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses
-system.cpu.dcache.overall_misses::total 82 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4346000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 4346000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 107.162861 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 47.437790 # Cycle average of tags in use
+system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.011581 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits
+system.cpu.dcache.overall_hits::total 627 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses
+system.cpu.dcache.overall_misses::total 82 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4346000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 4346000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=system.cpu.checker
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.checker]
type=O3Checker
children=dtb isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=0
env=
errout=cerr
euid=100
-executable=/gem5/dist/test-progs/hello/bin/arm/linux/hello
+executable=tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 4 2013 23:26:41
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:43:45
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 13372000 because target called exit()
+Exiting @ tick 13354000 because target called exit()
sim_ticks 13354000 # Number of ticks simulated
final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 46154 # Simulator instruction rate (inst/s)
-host_op_rate 57584 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 134203003 # Simulator tick rate (ticks/s)
-host_mem_usage 242404 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 22763 # Simulator instruction rate (inst/s)
+host_op_rate 28403 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 66199618 # Simulator tick rate (ticks/s)
+host_mem_usage 285296 # Number of bytes of host memory used
+host_seconds 0.20 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 33747.46 # Average gap between requests
+system.cpu.branchPred.lookups 2501 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 702 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 35.526316 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
system.cpu.checker.dtb.read_hits 0 # DTB read hits
system.cpu.numCycles 26709 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2501 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1795 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1976 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 702 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 292 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/test-progs/hello/bin/arm/linux/hello
+executable=tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:17:24
-gem5 started Jan 4 2013 23:26:30
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:43:34
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 13372000 because target called exit()
+Exiting @ tick 13354000 because target called exit()
sim_ticks 13354000 # Number of ticks simulated
final_tick 13354000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 53438 # Simulator instruction rate (inst/s)
-host_op_rate 66670 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 155374810 # Simulator tick rate (ticks/s)
-host_mem_usage 242400 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 20035 # Simulator instruction rate (inst/s)
+host_op_rate 24999 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 58267208 # Simulator tick rate (ticks/s)
+host_mem_usage 285296 # Number of bytes of host memory used
+host_seconds 0.23 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory
system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 33747.46 # Average gap between requests
+system.cpu.branchPred.lookups 2501 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 702 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 35.526316 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.numCycles 26709 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2501 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1795 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 485 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1976 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 702 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 292 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 6895 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=checker dtb interrupts itb tracer workload
+children=checker dtb interrupts isa itb tracer workload
+branchPred=Null
checker=system.cpu.checker
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.checker]
type=DummyChecker
-children=dtb itb tracer
+children=dtb isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=-1
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=Null
+isa=system.cpu.checker.isa
itb=system.cpu.checker.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.checker.tracer
workload=system.cpu.workload
num_squash_per_cycle=2
sys=system
+[system.cpu.checker.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.checker.itb]
type=ArmTLB
children=walker
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 1 2012 15:18:10
-gem5 started Nov 1 2012 22:41:17
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:44:07
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 2870500 # Number of ticks simulated
final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 135088 # Simulator instruction rate (inst/s)
-host_op_rate 168502 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 84394877 # Simulator tick rate (ticks/s)
-host_mem_usage 218472 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 1926 # Simulator instruction rate (inst/s)
+host_op_rate 2404 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1204405 # Simulator tick rate (ticks/s)
+host_mem_usage 275696 # Number of bytes of host memory used
+host_seconds 2.38 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[4]
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.membus.slave[3]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:19:53
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:43:56
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 2870500 # Number of ticks simulated
final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 116328 # Simulator instruction rate (inst/s)
-host_op_rate 145112 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 72682624 # Simulator tick rate (ticks/s)
-host_mem_usage 217124 # Number of bytes of host memory used
+host_inst_rate 122854 # Simulator instruction rate (inst/s)
+host_op_rate 153228 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 76735417 # Simulator tick rate (ticks/s)
+host_mem_usage 275692 # Number of bytes of host memory used
host_seconds 0.04 # Real time elapsed on the host
sim_insts 4591 # Number of instructions simulated
sim_ops 5729 # Number of ops (including micro ops) simulated
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
[system.cpu.dtb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[3]
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=ArmInterrupts
+[system.cpu.isa]
+type=ArmISA
+fpsid=1090793632
+id_isar0=34607377
+id_isar1=34677009
+id_isar2=555950401
+id_isar3=17899825
+id_isar4=268501314
+id_isar5=0
+id_mmfr0=3
+id_mmfr1=0
+id_mmfr2=19070976
+id_mmfr3=4027589137
+id_pfr0=49
+id_pfr1=1
+midr=890224640
+
[system.cpu.itb]
type=ArmTLB
children=walker
[system.cpu.itb.walker]
type=ArmTableWalker
-clock=1
+clock=500
num_squash_per_cycle=2
sys=system
port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
+executable=tests/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 21 2012 11:19:00
-gem5 started Sep 21 2012 11:19:07
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 19:44:20
+gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 27316000 because target called exit()
+Exiting @ tick 25969000 because target called exit()
sim_ticks 25969000 # Number of ticks simulated
final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 147661 # Simulator instruction rate (inst/s)
-host_op_rate 183366 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 839095918 # Simulator tick rate (ticks/s)
-host_mem_usage 231680 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 66941 # Simulator instruction rate (inst/s)
+host_op_rate 83151 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 380602116 # Simulator tick rate (ticks/s)
+host_mem_usage 284140 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 4565 # Number of instructions simulated
sim_ops 5672 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 83.000387 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.020264 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 1918 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1918 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1918 # number of overall hits
-system.cpu.dcache.overall_hits::total 1918 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
-system.cpu.dcache.overall_misses::total 141 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2059 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2059 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2059 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2059 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085515 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.085515 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085515 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085515 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 154.071129 # Cycle average of tags in use
system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 83.000387 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 83.000387 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.020264 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.020264 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 1918 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1918 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1918 # number of overall hits
+system.cpu.dcache.overall_hits::total 1918 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
+system.cpu.dcache.overall_misses::total 141 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 2059 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 2059 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2059 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2059 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085515 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.085515 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085515 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085515 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/mips/linux/hello
+executable=tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 30 2012 11:08:52
-gem5 started Oct 30 2012 13:57:29
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:16:48
+gem5 started Jan 23 2013 15:16:55
+gem5 executing on ribera.cs.wisc.edu
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 18578000 # Number of ticks simulated
final_tick 18578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 59954 # Simulator instruction rate (inst/s)
-host_op_rate 59945 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 191522194 # Simulator tick rate (ticks/s)
-host_mem_usage 214528 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 49489 # Simulator instruction rate (inst/s)
+host_op_rate 49481 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 158085302 # Simulator tick rate (ticks/s)
+host_mem_usage 270352 # Number of bytes of host memory used
+host_seconds 0.12 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 40665.93 # Average gap between requests
+system.cpu.branchPred.lookups 1154 # Number of BP lookups
+system.cpu.branchPred.condPredicted 858 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 603 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 877 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 336 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 38.312429 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 86 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.numCycles 37157 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 1154 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 858 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 603 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 877 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 336 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 86 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 32 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 38.312429 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 429 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 725 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5127 # Number of Reads from Int. Register File
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/test-progs/hello/bin/mips/linux/hello
+executable=tests/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:13:46
-gem5 started Jan 4 2013 21:58:53
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 15:16:48
+gem5 started Jan 23 2013 15:17:06
+gem5 executing on ribera.cs.wisc.edu
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 16532500 # Number of ticks simulated
final_tick 16532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 25568 # Simulator instruction rate (inst/s)
-host_op_rate 25564 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 81956278 # Simulator tick rate (ticks/s)
-host_mem_usage 217336 # Number of bytes of host memory used
-host_seconds 0.20 # Real time elapsed on the host
+host_inst_rate 36398 # Simulator instruction rate (inst/s)
+host_op_rate 36393 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 116675957 # Simulator tick rate (ticks/s)
+host_mem_usage 271376 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
sim_insts 5156 # Number of instructions simulated
sim_ops 5156 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 34566.18 # Average gap between requests
+system.cpu.branchPred.lookups 2120 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1453 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 517 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 31.314355 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 258 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.numCycles 33066 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2120 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1453 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 419 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1651 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 517 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 258 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 68 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 8642 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 12896 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2120 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=MipsInterrupts
+[system.cpu.isa]
+type=MipsISA
+num_threads=1
+num_vpes=1
+
[system.cpu.itb]
type=MipsTLB
size=64
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:00:38
-gem5 started Aug 13 2012 18:11:50
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:16:48
+gem5 started Jan 23 2013 15:17:17
+gem5 executing on ribera.cs.wisc.edu
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 2907000 # Number of ticks simulated
final_tick 2907000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 264545 # Simulator instruction rate (inst/s)
-host_op_rate 264338 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 132069950 # Simulator tick rate (ticks/s)
-host_mem_usage 214924 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 85249 # Simulator instruction rate (inst/s)
+host_op_rate 85225 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 42601271 # Simulator tick rate (ticks/s)
+host_mem_usage 261900 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 23260 # Number of bytes read from this memory
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=1
cpu_id=0
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
warn: Sockets disabled, not accepting gdb connections
hack: be nice to actually delete the event here
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 9 2012 13:41:09
-gem5 started Sep 9 2012 13:41:16
+gem5 compiled Jan 23 2013 15:16:48
+gem5 started Jan 23 2013 15:17:40
gem5 executing on ribera.cs.wisc.edu
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
sim_ticks 125334 # Number of ticks simulated
final_tick 125334 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 23120 # Simulator instruction rate (inst/s)
-host_op_rate 23118 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 498325 # Simulator tick rate (ticks/s)
-host_mem_usage 282364 # Number of bytes of host memory used
-host_seconds 0.25 # Real time elapsed on the host
+host_inst_rate 34119 # Simulator instruction rate (inst/s)
+host_op_rate 34115 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 735344 # Simulator tick rate (ticks/s)
+host_mem_usage 282376 # Number of bytes of host memory used
+host_seconds 0.17 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 23260 # Number of bytes read from this memory
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=262144
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
addr_ranges=0:18446744073709551615
assoc=2
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=10
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=131072
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=MipsInterrupts
+[system.cpu.isa]
+type=MipsISA
+num_threads=1
+num_vpes=1
+
[system.cpu.itb]
type=MipsTLB
size=64
[system.cpu.l2cache]
type=BaseCache
addr_ranges=0:18446744073709551615
-assoc=2
+assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=10
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=2097152
-subblock_size=0
system=system
-tgts_per_mshr=5
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
[system.cpu.toL2Bus]
type=CoherentBus
block_size=64
-clock=1000
+clock=500
header_cycles=1
use_default_range=false
-width=8
+width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simout
+Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:00:38
-gem5 started Aug 13 2012 18:12:01
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:16:48
+gem5 started Jan 23 2013 15:17:28
+gem5 executing on ribera.cs.wisc.edu
command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 33399000 because target called exit()
+Exiting @ tick 31633000 because target called exit()
sim_ticks 31633000 # Number of ticks simulated
final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 284864 # Simulator instruction rate (inst/s)
-host_op_rate 284628 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1547353604 # Simulator tick rate (ticks/s)
-host_mem_usage 219460 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 3112 # Simulator instruction rate (inst/s)
+host_op_rate 3112 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 16931146 # Simulator tick rate (ticks/s)
+host_mem_usage 270356 # Number of bytes of host memory used
+host_seconds 1.87 # Real time elapsed on the host
sim_insts 5814 # Number of instructions simulated
sim_ops 5814 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 87.492114 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1950 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 14.130435 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.021360 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1950 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1950 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1950 # number of overall hits
-system.cpu.dcache.overall_hits::total 1950 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
-system.cpu.dcache.overall_misses::total 138 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 2805000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 2805000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074807 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.074807 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.066092 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.066092 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.066092 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.066092 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 188.114191 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 87.492114 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1950 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 14.130435 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 87.492114 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.021360 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.021360 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 1950 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1950 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1950 # number of overall hits
+system.cpu.dcache.overall_hits::total 1950 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 51 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 51 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
+system.cpu.dcache.overall_misses::total 138 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 2805000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 2805000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074807 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.074807 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.066092 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.066092 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.066092 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.066092 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
UnifiedTLB=true
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/test-progs/hello/bin/power/linux/hello
+executable=tests/test-progs/hello/bin/power/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simout
+Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:14:12
-gem5 started Jan 4 2013 21:59:04
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 15:33:02
+gem5 started Jan 23 2013 15:33:08
+gem5 executing on ribera.cs.wisc.edu
command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 14065500 # Number of ticks simulated
final_tick 14065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 28037 # Simulator instruction rate (inst/s)
-host_op_rate 28032 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 68062430 # Simulator tick rate (ticks/s)
-host_mem_usage 213288 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
+host_inst_rate 44313 # Simulator instruction rate (inst/s)
+host_op_rate 44306 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 107578636 # Simulator tick rate (ticks/s)
+host_mem_usage 267272 # Number of bytes of host memory used
+host_seconds 0.13 # Real time elapsed on the host
sim_insts 5792 # Number of instructions simulated
sim_ops 5792 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory
system.physmem.readRowHitRate 82.74 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 31295.96 # Average gap between requests
+system.cpu.branchPred.lookups 2247 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1810 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 419 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1863 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 602 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 32.313473 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 198 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.numCycles 28132 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 2247 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 1810 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 419 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 1863 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 602 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 198 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 7398 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 13218 # Number of instructions fetch has processed
system.cpu.fetch.Branches 2247 # Number of branches that fetch encountered
type=System
children=cpu membus physmem
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
UnifiedTLB=true
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=PowerInterrupts
+[system.cpu.isa]
+type=PowerISA
+
[system.cpu.itb]
type=PowerTLB
size=64
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
+Redirecting stdout to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic/simout
+Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 13 2012 17:02:09
-gem5 started Aug 13 2012 18:12:35
-gem5 executing on zizzer
+gem5 compiled Jan 23 2013 15:33:02
+gem5 started Jan 23 2013 15:33:19
+gem5 executing on ribera.cs.wisc.edu
command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 2896000 # Number of ticks simulated
final_tick 2896000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 332855 # Simulator instruction rate (inst/s)
-host_op_rate 332536 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 166086520 # Simulator tick rate (ticks/s)
-host_mem_usage 209936 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 57024 # Simulator instruction rate (inst/s)
+host_op_rate 57013 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 28496468 # Simulator tick rate (ticks/s)
+host_mem_usage 257792 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 5793 # Number of instructions simulated
sim_ops 5793 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 23172 # Number of bytes read from this memory
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello
+executable=tests/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:45:52
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:01:02
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 16286500 # Number of ticks simulated
final_tick 16286500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 32524 # Simulator instruction rate (inst/s)
-host_op_rate 32520 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 99417983 # Simulator tick rate (ticks/s)
-host_mem_usage 221588 # Number of bytes of host memory used
+host_inst_rate 32843 # Simulator instruction rate (inst/s)
+host_op_rate 32839 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 100387600 # Simulator tick rate (ticks/s)
+host_mem_usage 278524 # Number of bytes of host memory used
host_seconds 0.16 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 38380.61 # Average gap between requests
+system.cpu.branchPred.lookups 1636 # Number of BP lookups
+system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 1343 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 584 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 43.484736 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 32574 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 1636 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 1090 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 897 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 1343 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 584 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 43.484736 # BTB Hit Percentage
system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5612 # Number of Reads from Int. Register File
system.cpu.stage4.utilization 9.691779 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.tagsinuse 143.423519 # Cycle average of tags in use
-system.cpu.icache.total_refs 896 # Total number of references to valid blocks.
+system.cpu.icache.total_refs 895 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 3.079038 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 3.075601 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 143.423519 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.070031 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.070031 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 896 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 896 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 896 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 896 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 896 # number of overall hits
-system.cpu.icache.overall_hits::total 896 # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst 895 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 895 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 895 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 895 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 895 # number of overall hits
+system.cpu.icache.overall_hits::total 895 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses
system.cpu.icache.demand_miss_latency::total 18347500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 18347500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 18347500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287758 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.287758 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.287758 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.287758 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.287758 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.287758 # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst 1257 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1257 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1257 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1257 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1257 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1257 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287987 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.287987 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.287987 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.287987 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.287987 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.287987 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50683.701657 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 50683.701657 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 50683.701657 # average overall miss latency
system.cpu.icache.demand_mshr_miss_latency::total 15194000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15194000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 15194000 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231504 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.231504 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.231504 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52213.058419 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52213.058419 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 85.216900 # Cycle average of tags in use
-system.cpu.dcache.total_refs 914 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 85.216900 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.020805 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.020805 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits
-system.cpu.dcache.overall_hits::total 914 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses
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-system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 474 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3347000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 19183000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 19183000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 22530000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 22530000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 22530000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 22530000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses
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-system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses
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-system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54868.852459 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 54868.852459 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46447.941889 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 46447.941889 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 47531.645570 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 47531.645570 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.656250 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4152500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4152500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7091500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7091500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7091500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7091500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51265.432099 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51265.432099 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 170.006396 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39355.522388 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39030.914894 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 85.216900 # Cycle average of tags in use
+system.cpu.dcache.total_refs 914 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 85.216900 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.020805 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.020805 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits
+system.cpu.dcache.overall_hits::total 914 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses
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+system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses
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+system.cpu.dcache.overall_misses::total 474 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 3347000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 19183000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 19183000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 22530000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 22530000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 22530000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 22530000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses
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+system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54868.852459 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 54868.852459 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46447.941889 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 46447.941889 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 47531.645570 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 47531.645570 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 47531.645570 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.656250 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits
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+system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4152500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4152500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7091500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7091500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7091500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7091500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51265.432099 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51265.432099 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52529.629630 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52529.629630 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello
+executable=tests/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:46:02
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:12:14
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 2694500 # Number of ticks simulated
final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 63026 # Simulator instruction rate (inst/s)
-host_op_rate 63015 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 31868954 # Simulator tick rate (ticks/s)
-host_mem_usage 212680 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 73566 # Simulator instruction rate (inst/s)
+host_op_rate 73547 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 37192728 # Simulator tick rate (ticks/s)
+host_mem_usage 269044 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=1
cpu_id=0
-Real time: Jan/14/2013 08:36:36
+Real time: Jan/23/2013 16:01:36
Profiler Stats
--------------
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.57
-Virtual_time_in_minutes: 0.0095
-Virtual_time_in_hours: 0.000158333
-Virtual_time_in_days: 6.59722e-06
+Virtual_time_in_seconds: 0.47
+Virtual_time_in_minutes: 0.00783333
+Virtual_time_in_hours: 0.000130556
+Virtual_time_in_days: 5.43981e-06
Ruby_current_time: 107952
Ruby_start_time: 0
Ruby_cycles: 107952
-mbytes_resident: 55.6602
-mbytes_total: 282.727
-resident_ratio: 0.196911
+mbytes_resident: 57.3125
+mbytes_total: 282.734
+resident_ratio: 0.202749
ruby_cycles_executed: [ 107953 ]
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11405
+page_reclaims: 10848
page_faults: 0
swaps: 0
block_inputs: 0
-block_outputs: 88
+block_outputs: 96
Network Stats
-------------
+Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:45:52
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:01:36
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 107952 # Number of ticks simulated
final_tick 107952 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 20687 # Simulator instruction rate (inst/s)
-host_op_rate 20685 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 419155 # Simulator tick rate (ticks/s)
-host_mem_usage 289516 # Number of bytes of host memory used
-host_seconds 0.26 # Real time elapsed on the host
+host_inst_rate 30407 # Simulator instruction rate (inst/s)
+host_op_rate 30404 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 616066 # Simulator tick rate (ticks/s)
+host_mem_usage 289524 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21480 # Number of bytes read from this memory
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/sparc/linux/hello
+executable=tests/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:46:02
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:12:36
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 27800000 # Number of ticks simulated
final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 85623 # Simulator instruction rate (inst/s)
-host_op_rate 85602 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 446634768 # Simulator tick rate (ticks/s)
-host_mem_usage 221096 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 116604 # Simulator instruction rate (inst/s)
+host_op_rate 116555 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 608021957 # Simulator tick rate (ticks/s)
+host_mem_usage 277492 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 5327 # Number of instructions simulated
sim_ops 5327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 16320 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 82.118455 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1253 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
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-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits
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-system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits
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-system.cpu.dcache.overall_hits::total 1253 # number of overall hits
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-system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses
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-system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 135 # number of overall misses
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-system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles
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-system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles
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-system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles
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-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency
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+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/test-progs/hello/bin/x86/linux/hello
+executable=tests/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout
+Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:20:54
-gem5 started Jan 4 2013 22:09:04
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 18:48:24
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 15014000 # Number of ticks simulated
final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 15963 # Simulator instruction rate (inst/s)
-host_op_rate 28915 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44538984 # Simulator tick rate (ticks/s)
-host_mem_usage 232848 # Number of bytes of host memory used
-host_seconds 0.34 # Real time elapsed on the host
+host_inst_rate 24822 # Simulator instruction rate (inst/s)
+host_op_rate 44962 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69258779 # Simulator tick rate (ticks/s)
+host_mem_usage 286624 # Number of bytes of host memory used
+host_seconds 0.22 # Real time elapsed on the host
sim_insts 5380 # Number of instructions simulated
sim_ops 9746 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory
system.physmem.readRowHitRate 78.22 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 33318.89 # Average gap between requests
+system.cpu.branchPred.lookups 3018 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3018 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 2500 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 796 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 31.840000 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.numCycles 30029 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 3018 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 3018 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 546 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 2500 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 796 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 8963 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 14512 # Number of instructions fetch has processed
system.cpu.fetch.Branches 3018 # Number of branches that fetch encountered
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 01:20:22
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 16:30:54
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
sim_ticks 5614500 # Number of ticks simulated
final_tick 5614500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 95396 # Simulator instruction rate (inst/s)
-host_op_rate 172737 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 99466308 # Simulator tick rate (ticks/s)
-host_mem_usage 263448 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 59484 # Simulator instruction rate (inst/s)
+host_op_rate 107725 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 62039506 # Simulator tick rate (ticks/s)
+host_mem_usage 277020 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory
[system.cpu]
type=TimingSimpleCPU
children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=1
cpu_id=0
-Real time: Jan/14/2013 08:41:48
+Real time: Jan/23/2013 16:34:52
Profiler Stats
--------------
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.61
-Virtual_time_in_minutes: 0.0101667
-Virtual_time_in_hours: 0.000169444
-Virtual_time_in_days: 7.06019e-06
+Virtual_time_in_seconds: 0.54
+Virtual_time_in_minutes: 0.009
+Virtual_time_in_hours: 0.00015
+Virtual_time_in_days: 6.25e-06
Ruby_current_time: 121759
Ruby_start_time: 0
Ruby_cycles: 121759
-mbytes_resident: 66.375
-mbytes_total: 290.48
-resident_ratio: 0.228541
+mbytes_resident: 66.3984
+mbytes_total: 290.648
+resident_ratio: 0.22849
ruby_cycles_executed: [ 121760 ]
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 13678
+page_reclaims: 13733
page_faults: 0
swaps: 0
-block_inputs: 240
-block_outputs: 152
+block_inputs: 0
+block_outputs: 88
Network Stats
-------------
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 01:12:43
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 16:34:52
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
sim_ticks 121759 # Number of ticks simulated
final_tick 121759 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 22533 # Simulator instruction rate (inst/s)
-host_op_rate 40812 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 509771 # Simulator tick rate (ticks/s)
-host_mem_usage 297456 # Number of bytes of host memory used
-host_seconds 0.24 # Real time elapsed on the host
+host_inst_rate 27688 # Simulator instruction rate (inst/s)
+host_op_rate 50147 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 626365 # Simulator tick rate (ticks/s)
+host_mem_usage 297628 # Number of bytes of host memory used
+host_seconds 0.19 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 54912 # Number of bytes read from this memory
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
int_slave=system.membus.master[2]
pio=system.membus.master[1]
+[system.cpu.isa]
+type=X86ISA
+
[system.cpu.itb]
type=X86TLB
children=walker
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Dec 30 2012 00:35:18
-gem5 started Dec 30 2012 01:20:12
+gem5 compiled Jan 23 2013 16:30:44
+gem5 started Jan 23 2013 19:18:31
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
sim_ticks 28357000 # Number of ticks simulated
final_tick 28357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 86866 # Simulator instruction rate (inst/s)
-host_op_rate 157296 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 457476490 # Simulator tick rate (ticks/s)
-host_mem_usage 271900 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 55225 # Simulator instruction rate (inst/s)
+host_op_rate 100013 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 290910277 # Simulator tick rate (ticks/s)
+host_mem_usage 285604 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9747 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 14528 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 80.799099 # Cycle average of tags in use
-system.cpu.dcache.total_refs 1853 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 13.828358 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 80.799099 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.019726 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 997 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 997 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1853 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1853 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1853 # number of overall hits
-system.cpu.dcache.overall_hits::total 1853 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
-system.cpu.dcache.overall_misses::total 134 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 1052 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 1052 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 1987 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 1987 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 1987 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 1987 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052281 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.052281 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.067438 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.067438 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.067438 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.067438 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052281 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052281 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.067438 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.067438 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 134.037527 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 80.799099 # Cycle average of tags in use
+system.cpu.dcache.total_refs 1853 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 13.828358 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 80.799099 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.019726 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 997 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 997 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 1853 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 1853 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 1853 # number of overall hits
+system.cpu.dcache.overall_hits::total 1853 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses
+system.cpu.dcache.overall_misses::total 134 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 1052 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 1052 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 1987 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 1987 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 1987 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 1987 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052281 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.052281 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.067438 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.067438 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.067438 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.067438 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052281 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052281 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.067438 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067438 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.067438 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload0 workload1
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
-defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa0 system.cpu.isa1
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=2
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
+switched_out=false
system=system
tracer=system.cpu.tracer
trapLatency=13
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=2
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=AlphaInterrupts
+[system.cpu.isa0]
+type=AlphaISA
+
+[system.cpu.isa1]
+type=AlphaISA
+
[system.cpu.itb]
type=AlphaTLB
size=48
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 1 2012 14:46:44
-gem5 started Nov 1 2012 15:18:34
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:39:20
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 19857000 # Number of ticks simulated
final_tick 19857000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 50642 # Simulator instruction rate (inst/s)
-host_op_rate 50640 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 78893380 # Simulator tick rate (ticks/s)
-host_mem_usage 214784 # Number of bytes of host memory used
-host_seconds 0.25 # Real time elapsed on the host
+host_inst_rate 38427 # Simulator instruction rate (inst/s)
+host_op_rate 38425 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 59863252 # Simulator tick rate (ticks/s)
+host_mem_usage 271256 # Number of bytes of host memory used
+host_seconds 0.33 # Real time elapsed on the host
sim_insts 12745 # Number of instructions simulated
sim_ops 12745 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory
system.physmem.readRowHitRate 75.41 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 20387.35 # Average gap between requests
+system.cpu.branchPred.lookups 6348 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3569 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1446 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 4530 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 874 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 19.293598 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 898 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 184 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.numCycles 39715 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 6348 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 3569 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1446 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 4530 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 874 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 898 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 184 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 1539 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 35371 # Number of instructions fetch has processed
system.cpu.fetch.Branches 6348 # Number of branches that fetch encountered
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60835.195200 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 60835.195200 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements::0 0 # number of replacements
-system.cpu.dcache.replacements::1 0 # number of replacements
-system.cpu.dcache.replacements::total 0 # number of replacements
-system.cpu.dcache.tagsinuse 210.613846 # Cycle average of tags in use
-system.cpu.dcache.total_refs 4387 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 349 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 12.570201 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 210.613846 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.051419 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.051419 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 3369 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 3369 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 1018 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 1018 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 4387 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 4387 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 4387 # number of overall hits
-system.cpu.dcache.overall_hits::total 4387 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 712 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 712 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1035 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1035 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1035 # number of overall misses
-system.cpu.dcache.overall_misses::total 1035 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 19559500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 19559500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 33573958 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 33573958 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 53133458 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 53133458 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 53133458 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 53133458 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 3692 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 3692 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 5422 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 5422 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 5422 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 5422 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087486 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.087486 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.190889 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.190889 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.190889 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.190889 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60555.727554 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60555.727554 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47154.435393 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 47154.435393 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 51336.674396 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 51336.674396 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 3056 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 103 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.669903 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 685 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 685 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 685 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 685 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14127500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 14127500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8703496 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 8703496 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22830996 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 22830996 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22830996 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 22830996 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055255 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055255 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.064552 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.064552 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69252.450980 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69252.450980 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59612.986301 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59612.986301 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements::0 0 # number of replacements
system.cpu.l2cache.replacements::1 0 # number of replacements
system.cpu.l2cache.replacements::total 0 # number of replacements
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51982.314286 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49210.888889 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements::0 0 # number of replacements
+system.cpu.dcache.replacements::1 0 # number of replacements
+system.cpu.dcache.replacements::total 0 # number of replacements
+system.cpu.dcache.tagsinuse 210.613846 # Cycle average of tags in use
+system.cpu.dcache.total_refs 4387 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 349 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 12.570201 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 210.613846 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.051419 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.051419 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 3369 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 3369 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 1018 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 1018 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 4387 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 4387 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 4387 # number of overall hits
+system.cpu.dcache.overall_hits::total 4387 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 712 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 712 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 1035 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 1035 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 1035 # number of overall misses
+system.cpu.dcache.overall_misses::total 1035 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 19559500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 19559500 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 33573958 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 33573958 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 53133458 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 53133458 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 53133458 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 53133458 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 3692 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 3692 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 5422 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 5422 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 5422 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 5422 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087486 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.087486 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.190889 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.190889 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.190889 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.190889 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60555.727554 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60555.727554 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47154.435393 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 47154.435393 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 51336.674396 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 51336.674396 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 51336.674396 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 3056 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 103 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 29.669903 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 685 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 685 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 685 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 685 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14127500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 14127500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8703496 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8703496 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22830996 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 22830996 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22830996 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 22830996 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055255 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055255 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.064552 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064552 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.064552 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69252.450980 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69252.450980 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59612.986301 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59612.986301 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65231.417143 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 65231.417143 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
+children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
+branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
cpu_id=0
-defer_registration=false
div16Latency=1
div16RepeatRate=1
div24Latency=1
fetchBuffSize=4
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
-instShiftAmt=2
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
multLatency=1
multRepeatRate=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
stageTracing=false
stageWidth=4
+switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest
+executable=tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:45:40
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:09:42
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 22838500 # Number of ticks simulated
final_tick 22838500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 15645 # Simulator instruction rate (inst/s)
-host_op_rate 15645 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 23565036 # Simulator tick rate (ticks/s)
-host_mem_usage 221420 # Number of bytes of host memory used
-host_seconds 0.97 # Real time elapsed on the host
+host_inst_rate 21741 # Simulator instruction rate (inst/s)
+host_op_rate 21740 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32746771 # Simulator tick rate (ticks/s)
+host_mem_usage 278448 # Number of bytes of host memory used
+host_seconds 0.70 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 2327934 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 11337934 # Sum of mem lat for all requests
+system.physmem.totQLat 2325934 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 11335934 # Sum of mem lat for all requests
system.physmem.totBusLat 1744000 # Total cycles spent in databus access
system.physmem.totBankLat 7266000 # Total cycles spent in bank access
-system.physmem.avgQLat 5339.30 # Average queueing delay per request
+system.physmem.avgQLat 5334.71 # Average queueing delay per request
system.physmem.avgBankLat 16665.14 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 26004.44 # Average memory access latency
+system.physmem.avgMemAccLat 25999.85 # Average memory access latency
system.physmem.avgRdBW 1221.80 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 1221.80 # Average consumed read bandwidth in MB/s
system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 52305.05 # Average gap between requests
+system.cpu.branchPred.lookups 5147 # Number of BP lookups
+system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 4101 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 2720 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 66.325287 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 45678 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.branch_predictor.lookups 5149 # Number of BP lookups
-system.cpu.branch_predictor.condPredicted 3529 # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect 2365 # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups 4104 # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits 2723 # Number of BTB hits
-system.cpu.branch_predictor.usedRAS 173 # Number of times the RAS was used to get a target.
-system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct 66.349903 # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken 2896 # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedTaken 2894 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 2253 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 14397 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File
system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 5052 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 3844 # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect 1540 # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedTakenIncorrect 1541 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 762 # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted 2302 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted 1056 # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct 68.552710 # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.mispredicted 2303 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted 1055 # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct 68.582490 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 11045 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.threadCycles 21901 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles 21903 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 502 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 28111 # Number of cycles cpu's stages were not processed
-system.cpu.runCycles 17567 # Number of cycles cpu stages are processed.
-system.cpu.activity 38.458339 # Percentage of cycles cpu is active
+system.cpu.idleCycles 28109 # Number of cycles cpu's stages were not processed
+system.cpu.runCycles 17569 # Number of cycles cpu stages are processed.
+system.cpu.activity 38.462717 # Percentage of cycles cpu is active
system.cpu.comLoads 2225 # Number of Load instructions committed
system.cpu.comStores 1448 # Number of Store instructions committed
system.cpu.comBranches 3358 # Number of Branches instructions committed
system.cpu.ipc 0.331932 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.331932 # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles 32253 # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles 13425 # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization 29.390516 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles 36325 # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization 20.475940 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles 36875 # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization 19.271860 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage0.idleCycles 32252 # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization 29.392705 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles 36324 # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles 9354 # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization 20.478130 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles 36874 # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles 8804 # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization 19.274049 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 42800 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 6.300626 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles 36370 # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles 9308 # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization 20.377425 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles 36369 # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization 20.379614 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.replacements 0 # number of replacements
-system.cpu.icache.tagsinuse 172.580385 # Cycle average of tags in use
-system.cpu.icache.total_refs 2999 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 172.574474 # Cycle average of tags in use
+system.cpu.icache.total_refs 3004 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 10.030100 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 10.046823 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 172.580385 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.084268 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.084268 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 2999 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 2999 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 2999 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 2999 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 2999 # number of overall hits
-system.cpu.icache.overall_hits::total 2999 # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst 172.574474 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.084265 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.084265 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 3004 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 3004 # number of overall hits
+system.cpu.icache.overall_hits::total 3004 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 381 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 381 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 381 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses
system.cpu.icache.overall_misses::total 381 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 18870500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 18870500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 18870500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 18870500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 18870500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 18870500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 3380 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 3380 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 3380 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 3380 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 3380 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 3380 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.112722 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.112722 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.112722 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.112722 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.112722 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.112722 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49528.871391 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 49528.871391 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 49528.871391 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 49528.871391 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 49528.871391 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 49528.871391 # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 18868500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 18868500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 18868500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 18868500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 18868500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 18868500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 3385 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 3385 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 3385 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.112555 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total 0.112555 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49523.622047 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 49523.622047 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 49523.622047 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 49523.622047 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 49523.622047 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 49523.622047 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15159500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 15159500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15159500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 15159500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15159500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 15159500 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.089053 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.089053 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.089053 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.089053 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.089053 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.089053 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50363.787375 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50363.787375 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50363.787375 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 50363.787375 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50363.787375 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 50363.787375 # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15157500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 15157500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15157500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 15157500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15157500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 15157500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50357.142857 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50357.142857 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50357.142857 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 50357.142857 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50357.142857 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 50357.142857 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.l2cache.replacements 0 # number of replacements
+system.cpu.l2cache.tagsinuse 204.083022 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::cpu.inst 171.933146 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 32.149876 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.005247 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.000981 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.006228 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 299 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 352 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 299 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 437 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
+system.cpu.l2cache.overall_misses::total 437 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14874500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2846000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 17720500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4426000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 4426000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 14874500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7272000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 22146500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 14874500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7272000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 22146500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 301 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
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+system.cpu.l2cache.overall_accesses::cpu.inst 301 # number of overall (read+write) accesses
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+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37142.076923 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38144.423341 # average overall mshr miss latency
+system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 99.521292 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 99.519804 # Cycle average of tags in use
system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 99.521292 # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data 99.519804 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.024297 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.024297 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53728.260870 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 53728.260870 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.tagsinuse 204.089765 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst 171.939057 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data 32.150708 # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst 0.005247 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data 0.000981 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total 0.006228 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst 299 # number of ReadReq misses
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-system.cpu.l2cache.overall_miss_latency::cpu.data 7272000 # number of overall miss cycles
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-system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52070.588235 # average ReadExReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::total 50683.066362 # average overall miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::total 50683.066362 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes 0 # number of fast writes performed
-system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses
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-system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 437 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11107481 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2181568 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13289049 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3382064 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3382064 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11107481 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5563632 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 16671113 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11107481 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5563632 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 16671113 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37148.765886 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41161.660377 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37752.980114 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39788.988235 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39788.988235 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37148.765886 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38149 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37148.765886 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38149 # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu.interrupts
isa=system.cpu.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
+[system.cpu.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/test-progs/insttest/bin/sparc/linux/insttest
+executable=tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:16:54
-gem5 started Jan 4 2013 21:59:36
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:08:16
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 23180500 # Number of ticks simulated
final_tick 23180500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 21899 # Simulator instruction rate (inst/s)
-host_op_rate 21897 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 35159544 # Simulator tick rate (ticks/s)
-host_mem_usage 223288 # Number of bytes of host memory used
-host_seconds 0.66 # Real time elapsed on the host
+host_inst_rate 20805 # Simulator instruction rate (inst/s)
+host_op_rate 20805 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33406458 # Simulator tick rate (ticks/s)
+host_mem_usage 278444 # Number of bytes of host memory used
+host_seconds 0.69 # Real time elapsed on the host
sim_insts 14436 # Number of instructions simulated
sim_ops 14436 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory
system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 47868.53 # Average gap between requests
+system.cpu.branchPred.lookups 6759 # Number of BP lookups
+system.cpu.branchPred.condPredicted 4517 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1074 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 4658 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 2448 # Number of BTB hits
+system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu.branchPred.BTBHitPct 52.554745 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 168 # Number of incorrect RAS predictions.
system.cpu.workload.num_syscalls 18 # Number of system calls
system.cpu.numCycles 46362 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 6759 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 4517 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1074 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 4658 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 2448 # Number of BTB hits
-system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS 442 # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 12203 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 31435 # Number of instructions fetch has processed
system.cpu.fetch.Branches 6759 # Number of branches that fetch encountered
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=AtomicSimpleCPU
-children=dtb interrupts itb tracer workload
+children=dtb interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu.tracer
width=1
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest
+executable=tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:46:06
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 15:49:34
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 7612000 # Number of ticks simulated
final_tick 7612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 19584 # Simulator instruction rate (inst/s)
-host_op_rate 19584 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9831731 # Simulator tick rate (ticks/s)
-host_mem_usage 212388 # Number of bytes of host memory used
-host_seconds 0.77 # Real time elapsed on the host
+host_inst_rate 30969 # Simulator instruction rate (inst/s)
+host_op_rate 30968 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 15546804 # Simulator tick rate (ticks/s)
+host_mem_usage 268968 # Number of bytes of host memory used
+host_seconds 0.49 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 60828 # Number of bytes read from this memory
init_param=0
kernel=
load_addr_mask=1099511627775
-mem_mode=atomic
+mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
+isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=262144
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=131072
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
[system.cpu.interrupts]
type=SparcInterrupts
+[system.cpu.isa]
+type=SparcISA
+
[system.cpu.itb]
type=SparcTLB
size=64
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=2097152
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest
+executable=tests/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:45:40
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 15:49:45
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 41368000 # Number of ticks simulated
final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 17560 # Simulator instruction rate (inst/s)
-host_op_rate 17560 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 47909450 # Simulator tick rate (ticks/s)
-host_mem_usage 220988 # Number of bytes of host memory used
-host_seconds 0.86 # Real time elapsed on the host
+host_inst_rate 26295 # Simulator instruction rate (inst/s)
+host_op_rate 26295 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 71739884 # Simulator tick rate (ticks/s)
+host_mem_usage 277420 # Number of bytes of host memory used
+host_seconds 0.58 # Real time elapsed on the host
sim_insts 15162 # Number of instructions simulated
sim_ops 15162 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 0 # number of replacements
-system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use
-system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
-system.cpu.dcache.overall_hits::total 3529 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
-system.cpu.dcache.overall_misses::total 138 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 184.632038 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.dcache.replacements 0 # number of replacements
+system.cpu.dcache.tagsinuse 97.994344 # Cycle average of tags in use
+system.cpu.dcache.total_refs 3535 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 25.615942 # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.023924 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits
+system.cpu.dcache.overall_hits::total 3529 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
+system.cpu.dcache.overall_misses::total 138 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu0]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb tracer workload
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb tracer workload
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu0.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu0.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu0.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
+[system.cpu0.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu0.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
env=
errout=cerr
euid=100
-executable=/gem5/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864
[system.cpu1]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu1.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu1.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu1.interrupts
isa=system.cpu1.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu1.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
+[system.cpu1.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu1.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
[system.cpu2]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu2.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu2.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu2.interrupts
isa=system.cpu2.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu2.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu2.dcache.cpu_side
icache_port=system.cpu2.icache.cpu_side
+[system.cpu2.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu2.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
[system.cpu3]
type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
-RASSize=16
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
+branchPred=system.cpu3.branchPred
cachePorts=200
checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
clock=500
commitToDecodeDelay=1
commitToFetchDelay=1
fuPool=system.cpu3.fuPool
function_trace=false
function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-instShiftAmt=2
interrupts=system.cpu3.interrupts
isa=system.cpu3.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu3.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
numROBEntries=192
numRobs=1
numThreads=1
-predType=tournament
profile=0
progress_interval=0
renameToDecodeDelay=1
dcache_port=system.cpu3.dcache.cpu_side
icache_port=system.cpu3.icache.cpu_side
+[system.cpu3.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
[system.cpu3.dcache]
type=BaseCache
addr_ranges=0:18446744073709551615
+Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 4 2013 21:16:54
-gem5 started Jan 4 2013 21:59:48
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:01:12
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 104832500 # Number of ticks simulated
final_tick 104832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 49068 # Simulator instruction rate (inst/s)
-host_op_rate 49068 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4970400 # Simulator tick rate (ticks/s)
-host_mem_usage 237836 # Number of bytes of host memory used
-host_seconds 21.09 # Real time elapsed on the host
+host_inst_rate 81452 # Simulator instruction rate (inst/s)
+host_op_rate 81452 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8250764 # Simulator tick rate (ticks/s)
+host_mem_usage 293492 # Number of bytes of host memory used
+host_seconds 12.71 # Real time elapsed on the host
sim_insts 1034907 # Number of instructions simulated
sim_ops 1034907 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory
system.physmem.readRowHitRate 76.78 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 159035.66 # Average gap between requests
+system.cpu0.branchPred.lookups 82004 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 79765 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 1218 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 79291 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 77227 # Number of BTB hits
+system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.branchPred.BTBHitPct 97.396930 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 516 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions.
system.cpu0.workload.num_syscalls 89 # Number of system calls
system.cpu0.numCycles 209666 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups 82004 # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted 79765 # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect 1218 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups 79291 # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits 77227 # Number of BTB hits
-system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS 516 # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
system.cpu0.fetch.icacheStallCycles 16910 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 486703 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 82004 # Number of branches that fetch encountered
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.branchPred.lookups 52905 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 50239 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 1268 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 46829 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 46139 # Number of BTB hits
+system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.branchPred.BTBHitPct 98.526554 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 659 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu1.numCycles 174086 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups 52905 # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted 50239 # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect 1268 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups 46829 # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits 46139 # Number of BTB hits
-system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS 659 # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu1.fetch.icacheStallCycles 27344 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 297404 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 52905 # Number of branches that fetch encountered
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu2.branchPred.lookups 43658 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 40905 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 1282 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 37514 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 36718 # Number of BTB hits
+system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu2.branchPred.BTBHitPct 97.878125 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 654 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu2.numCycles 173761 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.BPredUnit.lookups 43658 # Number of BP lookups
-system.cpu2.BPredUnit.condPredicted 40905 # Number of conditional branches predicted
-system.cpu2.BPredUnit.condIncorrect 1282 # Number of conditional branches incorrect
-system.cpu2.BPredUnit.BTBLookups 37514 # Number of BTB lookups
-system.cpu2.BPredUnit.BTBHits 36718 # Number of BTB hits
-system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.BPredUnit.usedRAS 654 # Number of times the RAS was used to get a target.
-system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu2.fetch.icacheStallCycles 33388 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 235313 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 43658 # Number of branches that fetch encountered
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu3.branchPred.lookups 53689 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 50963 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 1276 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 47522 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 46772 # Number of BTB hits
+system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+system.cpu3.branchPred.BTBHitPct 98.421784 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 661 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu3.numCycles 173451 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.BPredUnit.lookups 53689 # Number of BP lookups
-system.cpu3.BPredUnit.condPredicted 50963 # Number of conditional branches predicted
-system.cpu3.BPredUnit.condIncorrect 1276 # Number of conditional branches incorrect
-system.cpu3.BPredUnit.BTBLookups 47522 # Number of BTB lookups
-system.cpu3.BPredUnit.BTBHits 46772 # Number of BTB hits
-system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.BPredUnit.usedRAS 661 # Number of times the RAS was used to get a target.
-system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions.
system.cpu3.fetch.icacheStallCycles 27478 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.Insts 301364 # Number of instructions fetch has processed
system.cpu3.fetch.Branches 53689 # Number of branches that fetch encountered
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu0]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer workload
+children=dcache dtb icache interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu0.tracer
width=1
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
[system.cpu0.interrupts]
type=SparcInterrupts
+[system.cpu0.isa]
+type=SparcISA
+
[system.cpu0.itb]
type=SparcTLB
size=64
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864
[system.cpu1]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=1
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu1.tracer
width=1
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
[system.cpu1.interrupts]
type=SparcInterrupts
+[system.cpu1.isa]
+type=SparcISA
+
[system.cpu1.itb]
type=SparcTLB
size=64
[system.cpu2]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=2
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu2.interrupts
+isa=system.cpu2.isa
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu2.tracer
width=1
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.icache_port
[system.cpu2.interrupts]
type=SparcInterrupts
+[system.cpu2.isa]
+type=SparcISA
+
[system.cpu2.itb]
type=SparcTLB
size=64
[system.cpu3]
type=AtomicSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=3
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu3.interrupts
+isa=system.cpu3.isa
itb=system.cpu3.itb
max_insts_all_threads=0
max_insts_any_thread=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
+switched_out=false
system=system
tracer=system.cpu3.tracer
width=1
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.icache_port
[system.cpu3.interrupts]
type=SparcInterrupts
+[system.cpu3.isa]
+type=SparcISA
+
[system.cpu3.itb]
type=SparcTLB
size=64
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=4194304
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
+Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:45:52
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 16:09:53
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 87707000 # Number of ticks simulated
final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 174734 # Simulator instruction rate (inst/s)
-host_op_rate 174733 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 22625965 # Simulator tick rate (ticks/s)
-host_mem_usage 1150028 # Number of bytes of host memory used
-host_seconds 3.88 # Real time elapsed on the host
+host_inst_rate 205117 # Simulator instruction rate (inst/s)
+host_op_rate 205116 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26560282 # Simulator tick rate (ticks/s)
+host_mem_usage 1206900 # Number of bytes of host memory used
+host_seconds 3.30 # Real time elapsed on the host
sim_insts 677327 # Number of instructions simulated
sim_ops 677327 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory
kernel=
load_addr_mask=1099511627775
mem_mode=timing
+mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
[system.cpu0]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer workload
+children=dcache dtb icache interrupts isa itb tracer workload
+branchPred=Null
checker=Null
clock=500
cpu_id=0
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu0.interrupts
+isa=system.cpu0.isa
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu0.tracer
workload=system.cpu0.workload
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
[system.cpu0.interrupts]
type=SparcInterrupts
+[system.cpu0.isa]
+type=SparcISA
+
[system.cpu0.itb]
type=SparcTLB
size=64
env=
errout=cerr
euid=100
-executable=/projects/pd/randd/dist/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864
[system.cpu1]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=1
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu1.interrupts
+isa=system.cpu1.isa
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu1.tracer
workload=system.cpu0.workload
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
[system.cpu1.interrupts]
type=SparcInterrupts
+[system.cpu1.isa]
+type=SparcISA
+
[system.cpu1.itb]
type=SparcTLB
size=64
[system.cpu2]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=2
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu2.interrupts
+isa=system.cpu2.isa
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu2.tracer
workload=system.cpu0.workload
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu2.icache_port
[system.cpu2.interrupts]
type=SparcInterrupts
+[system.cpu2.isa]
+type=SparcISA
+
[system.cpu2.itb]
type=SparcTLB
size=64
[system.cpu3]
type=TimingSimpleCPU
-children=dcache dtb icache interrupts itb tracer
+children=dcache dtb icache interrupts isa itb tracer
+branchPred=Null
checker=Null
clock=500
cpu_id=3
-defer_registration=false
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
function_trace=false
function_trace_start=0
interrupts=system.cpu3.interrupts
+isa=system.cpu3.isa
itb=system.cpu3.itb
max_insts_all_threads=0
max_insts_any_thread=0
numThreads=1
profile=0
progress_interval=0
+switched_out=false
system=system
tracer=system.cpu3.tracer
workload=system.cpu0.workload
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.dcache_port
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=2
size=32768
-subblock_size=0
system=system
tgts_per_mshr=20
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.cpu3.icache_port
[system.cpu3.interrupts]
type=SparcInterrupts
+[system.cpu3.isa]
+type=SparcISA
+
[system.cpu3.itb]
type=SparcTLB
size=64
block_size=64
clock=500
forward_snoops=true
-hash_delay=1
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
response_latency=20
size=4194304
-subblock_size=0
system=system
tgts_per_mshr=12
-trace_addr=0
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
+Redirecting stdout to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simout
+Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 2 2012 11:45:16
-gem5 started Nov 2 2012 11:46:01
-gem5 executing on u200540-lin
+gem5 compiled Jan 23 2013 15:49:24
+gem5 started Jan 23 2013 15:51:52
+gem5 executing on ribera.cs.wisc.edu
command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 261623500 # Number of ticks simulated
final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 114971 # Simulator instruction rate (inst/s)
-host_op_rate 114971 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 45557694 # Simulator tick rate (ticks/s)
-host_mem_usage 232524 # Number of bytes of host memory used
-host_seconds 5.74 # Real time elapsed on the host
+host_inst_rate 226128 # Simulator instruction rate (inst/s)
+host_op_rate 226126 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 89603226 # Simulator tick rate (ticks/s)
+host_mem_usage 289396 # Number of bytes of host memory used
+host_seconds 2.92 # Real time elapsed on the host
sim_insts 660239 # Number of instructions simulated
sim_ops 660239 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=
-memories=system.funcmem system.physmem
+memories=system.physmem system.funcmem
num_work_ids=16
readfile=
symbolfile=
-Real time: Jan/14/2013 08:13:32
+Real time: Jan/23/2013 14:04:13
Profiler Stats
--------------
-Elapsed_time_in_seconds: 46
-Elapsed_time_in_minutes: 0.766667
-Elapsed_time_in_hours: 0.0127778
-Elapsed_time_in_days: 0.000532407
+Elapsed_time_in_seconds: 79
+Elapsed_time_in_minutes: 1.31667
+Elapsed_time_in_hours: 0.0219444
+Elapsed_time_in_days: 0.000914352
-Virtual_time_in_seconds: 46.4
-Virtual_time_in_minutes: 0.773333
-Virtual_time_in_hours: 0.0128889
-Virtual_time_in_days: 0.000537037
+Virtual_time_in_seconds: 47.52
+Virtual_time_in_minutes: 0.792
+Virtual_time_in_hours: 0.0132
+Virtual_time_in_days: 0.00055
Ruby_current_time: 8664886
Ruby_start_time: 0
Ruby_cycles: 8664886
-mbytes_resident: 70.9336
-mbytes_total: 415.473
-resident_ratio: 0.170758
+mbytes_resident: 71.0234
+mbytes_total: 415.48
+resident_ratio: 0.170971
ruby_cycles_executed: [ 8664887 8664887 8664887 8664887 8664887 8664887 8664887 8664887 ]
Resource Usage
--------------
page_size: 4096
-user_time: 46
+user_time: 47
system_time: 0
-page_reclaims: 10183
+page_reclaims: 10782
page_faults: 0
swaps: 0
-block_inputs: 0
-block_outputs: 200
+block_inputs: 16
+block_outputs: 720
Network Stats
-------------
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 10 2012 16:31:57
-gem5 started Nov 10 2012 16:32:41
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:02:54
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby
Global frequency set at 1000000000 ticks per second
sim_ticks 8664886 # Number of ticks simulated
final_tick 8664886 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 187879 # Simulator tick rate (ticks/s)
-host_mem_usage 425448 # Number of bytes of host memory used
-host_seconds 46.12 # Real time elapsed on the host
+host_tick_rate 109516 # Simulator tick rate (ticks/s)
+host_mem_usage 425456 # Number of bytes of host memory used
+host_seconds 79.12 # Real time elapsed on the host
system.ruby.l1_cntrl4.cacheMemory.num_data_array_reads 0 # number of data array reads
system.ruby.l1_cntrl4.cacheMemory.num_data_array_writes 0 # number of data array writes
system.ruby.l1_cntrl4.cacheMemory.num_tag_array_reads 0 # number of tag array reads
type=System
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcbus funcmem l2c membus physmem toL2Bus
boot_osflags=a
-clock=1
+clock=1000
init_param=0
kernel=
load_addr_mask=1099511627775
mem_mode=timing
+mem_ranges=
memories=system.physmem system.funcmem
num_work_ids=16
readfile=
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.test
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.test
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu2.test
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu3.test
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu4.test
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu5.test
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu6.test
type=MemTest
children=l1c
atomic=false
-clock=1
+clock=500
issue_dmas=false
max_loads=100000
memory_size=65536
addr_ranges=0:18446744073709551615
assoc=4
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=1000
+hit_latency=2
is_top_level=true
max_miss_count=0
-mshrs=12
+mshrs=4
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=1000
+response_latency=2
size=32768
-subblock_size=0
system=system
-tgts_per_mshr=8
-trace_addr=0
+tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu7.test
[system.funcmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=false
latency=30000
addr_ranges=0:18446744073709551615
assoc=8
block_size=64
-clock=1
+clock=500
forward_snoops=true
-hash_delay=1
-hit_latency=10000
+hit_latency=20
is_top_level=false
max_miss_count=0
-mshrs=92
+mshrs=20
prefetch_on_access=false
prefetcher=Null
-prioritizeRequests=false
-repl=Null
-response_latency=10000
+response_latency=20
size=65536
-subblock_size=0
system=system
-tgts_per_mshr=16
-trace_addr=0
+tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
[system.membus]
type=CoherentBus
block_size=64
-clock=2
+clock=1000
header_cycles=1
use_default_range=false
width=16
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
-clock=1
+clock=1000
conf_table_reported=false
in_addr_map=true
latency=30000
[system.toL2Bus]
type=CoherentBus
block_size=64
-clock=2
+clock=500
header_cycles=1
use_default_range=false
width=16
-system.cpu0: completed 10000 read, 5290 write accesses @74885500
-system.cpu7: completed 10000 read, 5447 write accesses @78072500
-system.cpu2: completed 10000 read, 5330 write accesses @78536500
-system.cpu5: completed 10000 read, 5401 write accesses @79479500
-system.cpu3: completed 10000 read, 5406 write accesses @80479500
-system.cpu1: completed 10000 read, 5452 write accesses @80823500
-system.cpu4: completed 10000 read, 5330 write accesses @82914500
-system.cpu6: completed 10000 read, 5363 write accesses @83627000
-system.cpu7: completed 20000 read, 10668 write accesses @150917000
-system.cpu0: completed 20000 read, 10683 write accesses @151253500
-system.cpu5: completed 20000 read, 10718 write accesses @151911500
-system.cpu2: completed 20000 read, 10688 write accesses @152119000
-system.cpu3: completed 20000 read, 10954 write accesses @159391000
-system.cpu6: completed 20000 read, 10780 write accesses @160278500
-system.cpu1: completed 20000 read, 10888 write accesses @160835000
-system.cpu4: completed 20000 read, 10745 write accesses @162137000
-system.cpu2: completed 30000 read, 16060 write accesses @225600500
-system.cpu0: completed 30000 read, 16073 write accesses @226217000
-system.cpu7: completed 30000 read, 15898 write accesses @227550500
-system.cpu5: completed 30000 read, 16102 write accesses @230201000
-system.cpu3: completed 30000 read, 16375 write accesses @233880500
-system.cpu1: completed 30000 read, 16184 write accesses @234964500
-system.cpu6: completed 30000 read, 16132 write accesses @236785500
-system.cpu4: completed 30000 read, 16103 write accesses @242571500
-system.cpu7: completed 40000 read, 21206 write accesses @298942500
-system.cpu2: completed 40000 read, 21441 write accesses @299465500
-system.cpu0: completed 40000 read, 21388 write accesses @302202500
-system.cpu5: completed 40000 read, 21578 write accesses @308632000
-system.cpu6: completed 40000 read, 21492 write accesses @314697500
-system.cpu3: completed 40000 read, 22088 write accesses @315960000
-system.cpu4: completed 40000 read, 21590 write accesses @317147500
-system.cpu1: completed 40000 read, 21566 write accesses @317423500
-system.cpu7: completed 50000 read, 26570 write accesses @373251000
-system.cpu2: completed 50000 read, 26788 write accesses @373919000
-system.cpu0: completed 50000 read, 26897 write accesses @382805000
-system.cpu5: completed 50000 read, 27003 write accesses @384437500
-system.cpu3: completed 50000 read, 27349 write accesses @389623000
-system.cpu4: completed 50000 read, 26792 write accesses @389830500
-system.cpu6: completed 50000 read, 27002 write accesses @392270000
-system.cpu1: completed 50000 read, 26853 write accesses @392392000
-system.cpu7: completed 60000 read, 31855 write accesses @449936000
-system.cpu2: completed 60000 read, 32201 write accesses @452901500
-system.cpu0: completed 60000 read, 32209 write accesses @457331000
-system.cpu5: completed 60000 read, 32356 write accesses @458864500
-system.cpu4: completed 60000 read, 32204 write accesses @464577500
-system.cpu3: completed 60000 read, 32813 write accesses @468126500
-system.cpu6: completed 60000 read, 32463 write accesses @469913500
-system.cpu1: completed 60000 read, 32376 write accesses @472262000
-system.cpu7: completed 70000 read, 37203 write accesses @526760000
-system.cpu2: completed 70000 read, 37525 write accesses @530661000
-system.cpu5: completed 70000 read, 37749 write accesses @533141500
-system.cpu0: completed 70000 read, 37615 write accesses @537691500
-system.cpu3: completed 70000 read, 38216 write accesses @538787500
-system.cpu4: completed 70000 read, 37614 write accesses @545810500
-system.cpu6: completed 70000 read, 37722 write accesses @546307000
-system.cpu1: completed 70000 read, 37746 write accesses @546660500
-system.cpu7: completed 80000 read, 42460 write accesses @600681000
-system.cpu5: completed 80000 read, 42949 write accesses @604308500
-system.cpu2: completed 80000 read, 42841 write accesses @606628000
-system.cpu0: completed 80000 read, 43072 write accesses @615043500
-system.cpu3: completed 80000 read, 43808 write accesses @615907000
-system.cpu4: completed 80000 read, 43047 write accesses @622672500
-system.cpu6: completed 80000 read, 43213 write accesses @622720000
-system.cpu1: completed 80000 read, 43140 write accesses @626035000
-system.cpu2: completed 90000 read, 48140 write accesses @675974000
-system.cpu7: completed 90000 read, 48058 write accesses @680921000
-system.cpu5: completed 90000 read, 48486 write accesses @683376500
-system.cpu3: completed 90000 read, 49174 write accesses @687533500
-system.cpu0: completed 90000 read, 48447 write accesses @690023000
-system.cpu6: completed 90000 read, 48621 write accesses @702298000
-system.cpu4: completed 90000 read, 48429 write accesses @703717000
-system.cpu1: completed 90000 read, 48600 write accesses @705675000
-system.cpu2: completed 100000 read, 53454 write accesses @753126500
+system.cpu4: completed 10000 read, 5213 write accesses @76807500
+system.cpu7: completed 10000 read, 5302 write accesses @79251000
+system.cpu3: completed 10000 read, 5351 write accesses @81062000
+system.cpu5: completed 10000 read, 5541 write accesses @82066500
+system.cpu1: completed 10000 read, 5479 write accesses @82140500
+system.cpu2: completed 10000 read, 5270 write accesses @82209500
+system.cpu6: completed 10000 read, 5352 write accesses @82224000
+system.cpu0: completed 10000 read, 5437 write accesses @83502000
+system.cpu4: completed 20000 read, 10638 write accesses @152852500
+system.cpu7: completed 20000 read, 10671 write accesses @153245500
+system.cpu5: completed 20000 read, 10802 write accesses @155921500
+system.cpu1: completed 20000 read, 10780 write accesses @157898500
+system.cpu3: completed 20000 read, 10762 write accesses @158207000
+system.cpu2: completed 20000 read, 10562 write accesses @158441500
+system.cpu6: completed 20000 read, 10817 write accesses @160812000
+system.cpu0: completed 20000 read, 10942 write accesses @162138000
+system.cpu4: completed 30000 read, 15885 write accesses @226882500
+system.cpu7: completed 30000 read, 16162 write accesses @230488000
+system.cpu1: completed 30000 read, 15996 write accesses @231220000
+system.cpu5: completed 30000 read, 16227 write accesses @232272500
+system.cpu3: completed 30000 read, 16181 write accesses @234012000
+system.cpu6: completed 30000 read, 16285 write accesses @236458500
+system.cpu2: completed 30000 read, 16117 write accesses @236552000
+system.cpu0: completed 30000 read, 16426 write accesses @240306500
+system.cpu4: completed 40000 read, 21151 write accesses @301825500
+system.cpu7: completed 40000 read, 21649 write accesses @305825500
+system.cpu1: completed 40000 read, 21293 write accesses @308437500
+system.cpu3: completed 40000 read, 21436 write accesses @308497500
+system.cpu5: completed 40000 read, 21614 write accesses @310554000
+system.cpu2: completed 40000 read, 21323 write accesses @312243500
+system.cpu6: completed 40000 read, 21541 write accesses @312536000
+system.cpu0: completed 40000 read, 21919 write accesses @320331000
+system.cpu4: completed 50000 read, 26446 write accesses @376676500
+system.cpu7: completed 50000 read, 26971 write accesses @382643500
+system.cpu1: completed 50000 read, 26742 write accesses @382692500
+system.cpu3: completed 50000 read, 26868 write accesses @383729000
+system.cpu5: completed 50000 read, 26982 write accesses @388892000
+system.cpu2: completed 50000 read, 26690 write accesses @389746500
+system.cpu6: completed 50000 read, 26890 write accesses @390639500
+system.cpu0: completed 50000 read, 27239 write accesses @394395001
+system.cpu4: completed 60000 read, 31859 write accesses @454814000
+system.cpu3: completed 60000 read, 32157 write accesses @455574000
+system.cpu1: completed 60000 read, 32039 write accesses @458833000
+system.cpu7: completed 60000 read, 32494 write accesses @460248000
+system.cpu2: completed 60000 read, 32094 write accesses @465749500
+system.cpu5: completed 60000 read, 32378 write accesses @466634000
+system.cpu6: completed 60000 read, 32333 write accesses @468161500
+system.cpu0: completed 60000 read, 32569 write accesses @469644500
+system.cpu3: completed 70000 read, 37524 write accesses @531095000
+system.cpu4: completed 70000 read, 37387 write accesses @531724000
+system.cpu1: completed 70000 read, 37455 write accesses @534864500
+system.cpu2: completed 70000 read, 37386 write accesses @539742500
+system.cpu7: completed 70000 read, 38025 write accesses @540171500
+system.cpu5: completed 70000 read, 37779 write accesses @540661000
+system.cpu0: completed 70000 read, 37912 write accesses @543002000
+system.cpu6: completed 70000 read, 37876 write accesses @544926000
+system.cpu4: completed 80000 read, 42765 write accesses @607648000
+system.cpu3: completed 80000 read, 42947 write accesses @608627500
+system.cpu1: completed 80000 read, 42804 write accesses @612176500
+system.cpu5: completed 80000 read, 43215 write accesses @614679500
+system.cpu2: completed 80000 read, 42837 write accesses @616130500
+system.cpu7: completed 80000 read, 43372 write accesses @618251000
+system.cpu0: completed 80000 read, 43388 write accesses @620992000
+system.cpu6: completed 80000 read, 43420 write accesses @622851000
+system.cpu4: completed 90000 read, 48066 write accesses @681361000
+system.cpu3: completed 90000 read, 48251 write accesses @683201500
+system.cpu1: completed 90000 read, 48377 write accesses @690035500
+system.cpu5: completed 90000 read, 48546 write accesses @692142000
+system.cpu2: completed 90000 read, 48240 write accesses @693946000
+system.cpu7: completed 90000 read, 48816 write accesses @696757000
+system.cpu0: completed 90000 read, 48758 write accesses @697163500
+system.cpu6: completed 90000 read, 48649 write accesses @698059000
+system.cpu4: completed 100000 read, 53418 write accesses @758619000
hack: be nice to actually delete the event here
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 15 2012 19:23:25
-gem5 started Oct 15 2012 19:23:52
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 13:46:00
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 753126500 because maximum number of loads reached
+Exiting @ tick 758619000 because maximum number of loads reached
sim_ticks 758619000 # Number of ticks simulated
final_tick 758619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 151805189 # Simulator tick rate (ticks/s)
-host_mem_usage 345224 # Number of bytes of host memory used
-host_seconds 5.00 # Real time elapsed on the host
+host_tick_rate 45315591 # Simulator tick rate (ticks/s)
+host_mem_usage 399988 # Number of bytes of host memory used
+host_seconds 16.74 # Real time elapsed on the host
system.physmem.bytes_read::cpu0 93443 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1 93419 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2 89535 # Number of bytes read from this memory
-Real time: Jan/14/2013 08:13:02
+Real time: Jan/23/2013 14:07:36
Profiler Stats
--------------
Elapsed_time_in_hours: 0
Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.43
-Virtual_time_in_minutes: 0.00716667
-Virtual_time_in_hours: 0.000119444
-Virtual_time_in_days: 4.97685e-06
+Virtual_time_in_seconds: 0.44
+Virtual_time_in_minutes: 0.00733333
+Virtual_time_in_hours: 0.000122222
+Virtual_time_in_days: 5.09259e-06
Ruby_current_time: 221941
Ruby_start_time: 0
Ruby_cycles: 221941
-mbytes_resident: 49.6133
-mbytes_total: 270.469
-resident_ratio: 0.183478
+mbytes_resident: 49.4375
+mbytes_total: 270.48
+resident_ratio: 0.18282
ruby_cycles_executed: [ 221942 ]
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 9333
+page_reclaims: 10370
page_faults: 0
swaps: 0
-block_inputs: 0
+block_inputs: 24
block_outputs: 80
Network Stats
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
+Warning: rounding error > tolerance
+ 0.072760 rounded to 0
hack: be nice to actually delete the event here
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 1 2012 13:41:29
-gem5 started Sep 1 2012 13:48:35
-gem5 executing on doudou.cs.wisc.edu
+gem5 compiled Jan 23 2013 13:29:14
+gem5 started Jan 23 2013 14:07:36
+gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 221941 # Number of ticks simulated
final_tick 221941 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 2209832 # Simulator tick rate (ticks/s)
-host_mem_usage 276964 # Number of bytes of host memory used
+host_tick_rate 2209091 # Simulator tick rate (ticks/s)
+host_mem_usage 276976 # Number of bytes of host memory used
host_seconds 0.10 # Real time elapsed on the host
system.ruby.l1_cntrl0.cacheMemory.num_data_array_reads 0 # number of data array reads
system.ruby.l1_cntrl0.cacheMemory.num_data_array_writes 0 # number of data array writes
projects / gem5.git / commitdiff