rename sdram mapping to main_ram
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Sat, 21 Mar 2015 20:00:12 +0000 (21:00 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Sat, 21 Mar 2015 20:01:46 +0000 (21:01 +0100)
misoclib/soc/__init__.py
misoclib/soc/sdram.py
software/bios/boot.c
software/bios/sdram.c
software/libbase/system.c

index 80b26d42503ff894d83ded5997cd02bc11e9f6df..2e2a1f2307657c1e8fafb73527a8bbcf87953f95 100644 (file)
@@ -31,7 +31,7 @@ class SoC(Module):
        mem_map = {
                "rom":          0x00000000, # (shadow @0x80000000)
                "sram":         0x10000000, # (shadow @0x90000000)
-               "sdram":        0x40000000, # (shadow @0xc0000000)
+               "main_ram":     0x40000000, # (shadow @0xc0000000)
                "csr":          0x60000000, # (shadow @0xe0000000)
        }
        def __init__(self, platform, clk_freq, cpu_or_bridge=None,
@@ -101,7 +101,7 @@ class SoC(Module):
                        # Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
                        if with_integrated_main_ram:
                                self.submodules.main_ram = wishbone.SRAM(main_ram_size)
-                               self.register_mem("sdram", self.mem_map["sdram"], self.main_ram.bus, main_ram_size)
+                               self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, main_ram_size)
 
                elif cpu_or_bridge is not None and not isinstance(cpu_or_bridge, CPU):
                        self._wb_masters += [cpu_or_bridge.wishbone]
index 5ead08d6bf949c7cb4c3ee577e7b896c7adbd513..5ddf976ed18f13dfda249a0d4043b9b062e98ae6 100644 (file)
@@ -63,7 +63,7 @@ class SDRAMSoC(SoC):
                                        self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())
                                lasmic = self.sdram.controller.lasmic
                                main_ram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8
-                               self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, main_ram_size)
+                               self.register_mem("main_ram", self.mem_map["main_ram"], self.wishbone2lasmi.wishbone, main_ram_size)
 
                # MINICON frontend
                elif self.ramcon_type == "minicon":
@@ -71,11 +71,11 @@ class SDRAMSoC(SoC):
                        main_ram_size = 2**(geom_settings.bank_a+geom_settings.row_a+geom_settings.col_a)*sdram_width//8
 
                        if sdram_width == 32:
-                               self.register_mem("sdram", self.mem_map["sdram"], self.sdram.controller.bus, main_ram_size)
+                               self.register_mem("main_ram", self.mem_map["main_ram"], self.sdram.controller.bus, main_ram_size)
                        elif sdram_width < 32:
                                self.submodules.downconverter = downconverter = wishbone.DownConverter(32, sdram_width)
                                self.comb += Record.connect(downconverter.wishbone_o, self.sdram.controller.bus)
-                               self.register_mem("sdram", self.mem_map["sdram"], downconverter.wishbone_i, main_ram_size)
+                               self.register_mem("main_ram", self.mem_map["main_ram"], downconverter.wishbone_i, main_ram_size)
                        else:
                                raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
 
index 210937e686cdfe10776193bd122e3d5ccb1fdb74..b40e659834a7eff791000393158467cb3ef3b35d 100644 (file)
@@ -215,12 +215,12 @@ void netboot(void)
 
        microudp_start(macadr, IPTOINT(LOCALIP1, LOCALIP2, LOCALIP3, LOCALIP4));
 
-       if(tftp_get_v(ip, "boot.bin", (void *)SDRAM_BASE) <= 0) {
+       if(tftp_get_v(ip, "boot.bin", (void *)MAIN_RAM_BASE) <= 0) {
                printf("Network boot failed\n");
                return;
        }
 
-       cmdline_adr = SDRAM_BASE+0x1000000;
+       cmdline_adr = MAIN_RAM_BASE+0x1000000;
        size = tftp_get_v(ip, "cmdline.txt", (void *)cmdline_adr);
        if(size <= 0) {
                printf("No command line parameters found\n");
@@ -228,7 +228,7 @@ void netboot(void)
        } else
                *((char *)(cmdline_adr+size)) = 0x00;
 
-       initrdstart_adr = SDRAM_BASE+0x1002000;
+       initrdstart_adr = MAIN_RAM_BASE+0x1002000;
        size = tftp_get_v(ip, "initrd.bin", (void *)initrdstart_adr);
        if(size <= 0) {
                printf("No initial ramdisk found\n");
@@ -237,7 +237,7 @@ void netboot(void)
        } else
                initrdend_adr = initrdstart_adr + size;
 
-       boot(cmdline_adr, initrdstart_adr, initrdend_adr, SDRAM_BASE);
+       boot(cmdline_adr, initrdstart_adr, initrdend_adr, MAIN_RAM_BASE);
 }
 
 #endif
@@ -260,12 +260,12 @@ void flashboot(void)
        }
 
        printf("Loading %d bytes from flash...\n", length);
-       memcpy((void *)SDRAM_BASE, flashbase, length);
-       got_crc = crc32((unsigned char *)SDRAM_BASE, length);
+       memcpy((void *)MAIN_RAM_BASE, flashbase, length);
+       got_crc = crc32((unsigned char *)MAIN_RAM_BASE, length);
        if(crc != got_crc) {
                printf("CRC failed (expected %08x, got %08x)\n", crc, got_crc);
                return;
        }
-       boot(0, 0, 0, SDRAM_BASE);
+       boot(0, 0, 0, MAIN_RAM_BASE);
 }
 #endif
index 2ca55da6e26b0ce84d5a77aba4aa2a7a20ee3c8c..d374e9d37d0edbf29732f6177fc49a9ae7b4cfa4 100644 (file)
@@ -429,7 +429,7 @@ int sdrlevel(void)
 
 int memtest_silent(void)
 {
-       volatile unsigned int *array = (unsigned int *)SDRAM_BASE;
+       volatile unsigned int *array = (unsigned int *)MAIN_RAM_BASE;
        int i;
        unsigned int prv;
        unsigned int error_cnt;
index ca61850472fea40c9e0554937977fdb54839acf3..f0ea28fae914b163cd7fd754d2a88e55acb36227 100644 (file)
@@ -77,7 +77,7 @@ void flush_l2_cache(void)
 
        l2_nwords = 1 << wishbone2lasmi_cachesize_read();
        for(i=0;i<2*l2_nwords;i++) {
-               addr = SDRAM_BASE + i*4;
+               addr = MAIN_RAM_BASE + i*4;
 #ifdef __lm32__
                __asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
 #else