Unify verilog style

diff --git a/tests/arch/common/add_sub.v b/tests/arch/common/add_sub.v
index 177c32e3085bdb68cf8ee2449c6a3da588a1dd06..77e5f57457c5e02d64c32ef9be3638c233f696f3 100644 (file)
--- a/tests/arch/common/add_sub.v
+++ b/tests/arch/common/add_sub.v
@@ -1,13 +1,12 @@
 module top
 (
- input [3:0] x,
- input [3:0] y,
+    input [3:0] x,
+    input [3:0] y,
 
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
+    output [3:0] A,
+    output [3:0] B
+);
 
+    assign A =  x + y;
+    assign B =  x - y;
 endmodule

diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v
index 223b52d21965c30861549fb802fdae34b8c275c9..576bd81a6521ee26a2a04ac52ec0640db2cd9e61 100644 (file)
--- a/tests/arch/common/adffs.v
+++ b/tests/arch/common/adffs.v
@@ -1,47 +1,43 @@
-module adff
-    ( input d, clk, clr, output reg q );
+module adff( input d, clk, clr, output reg q );
     initial begin
-      q = 0;
+        q = 0;
     end
-       always @( posedge clk, posedge clr )
-               if ( clr )
-                       q <= 1'b0;
-               else
-            q <= d;
+         always @( posedge clk, posedge clr )
+      if ( clr )
+        q <= 1'b0;
+      else
+        q <= d;
 endmodule
 
-module adffn
-    ( input d, clk, clr, output reg q );
+module adffn( input d, clk, clr, output reg q );
     initial begin
       q = 0;
     end
-       always @( posedge clk, negedge clr )
-               if ( !clr )
-                       q <= 1'b0;
-               else
-            q <= d;
+         always @( posedge clk, negedge clr )
+                 if ( !clr )
+                         q <= 1'b0;
+               else
+        q <= d;
 endmodule
 
-module dffs
-    ( input d, clk, pre, clr, output reg q );
+module dffs( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-       always @( posedge clk )
-               if ( pre )
-                       q <= 1'b1;
-               else
-            q <= d;
+    always @( posedge clk )
+      if ( pre )
+        q <= 1'b1;
+      else
+        q <= d;
 endmodule
 
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
+module ndffnr( input d, clk, pre, clr, output reg q );
     initial begin
       q = 0;
     end
-       always @( negedge clk )
-               if ( !clr )
-                       q <= 1'b0;
-               else
-            q <= d;
+    always @( negedge clk )
+      if ( !clr )
+        q <= 1'b0;
+      else
+        q <= d;
 endmodule

diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v
index 52852f8aca90fdb3a7eb6495c059aade4320f08d..97604d3d886ac1cda855b331c661adb1b6af0299 100644 (file)
--- a/tests/arch/common/counter.v
+++ b/tests/arch/common/counter.v
@@ -1,17 +1,11 @@
-module top    (\r
-out,\r
-clk,\r
-reset\r
-);\r
+module top ( out, clk, reset );\r
     output [7:0] out;\r
     input clk, reset;\r
     reg [7:0] out;\r
 \r
     always @(posedge clk, posedge reset)\r
-               if (reset) begin\r
-                       out <= 8'b0 ;\r
-               end else\r
-                       out <= out + 1;\r
-\r
-\r
+      if (reset)\r
+          out <= 8'b0;\r
+      end\r
+          out <= out + 1;\r
 endmodule\r

diff --git a/tests/arch/common/dffs.v b/tests/arch/common/dffs.v
index 3418787c9fbf25125d0e79cf11065d279df064a6..636252d16374d7d36ee8ce84ff66c2c7981475b0 100644 (file)
--- a/tests/arch/common/dffs.v
+++ b/tests/arch/common/dffs.v
@@ -1,15 +1,13 @@
-module dff
-    ( input d, clk, output reg q );
-       always @( posedge clk )
-            q <= d;
+module dff ( input d, clk, output reg q );
+         always @( posedge clk )
+        q <= d;
 endmodule
 
-module dffe
-    ( input d, clk, en, output reg q );
+module dffe( input d, clk, en, output reg q );
     initial begin
-      q = 0;
+        q = 0;
     end
-       always @( posedge clk )
-               if ( en )
-                       q <= d;
+         always @( posedge clk )
+        if ( en )
+              q <= d;
 endmodule

diff --git a/tests/arch/common/fsm.v b/tests/arch/common/fsm.v
index 368fbaace5e8a1e87b98b937646cc700f049c241..9d3fbb64aef7af55c9c58ce11aef838d7c694094 100644 (file)
--- a/tests/arch/common/fsm.v
+++ b/tests/arch/common/fsm.v
@@ -1,55 +1,51 @@
- module fsm (\r
- clock,\r
- reset,\r
- req_0,\r
- req_1,\r
- gnt_0,\r
- gnt_1\r
- );\r
- input   clock,reset,req_0,req_1;\r
- output  gnt_0,gnt_1;\r
- wire    clock,reset,req_0,req_1;\r
- reg     gnt_0,gnt_1;\r
+ module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );\r
+    input   clock,reset,req_0,req_1;\r
+    output  gnt_0,gnt_1;\r
+    wire    clock,reset,req_0,req_1;\r
+    reg     gnt_0,gnt_1;\r
 \r
- parameter SIZE = 3           ;\r
- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;\r
+    parameter SIZE = 3;\r
+    parameter IDLE = 3'b001;\r
+    parameter GNT0 = 3'b010;\r
+    parameter GNT1 = 3'b100;\r
+    parameter GNT2 = 3'b101;\r
 \r
- reg [SIZE-1:0] state;\r
- reg [SIZE-1:0] next_state;\r
-\r
- always @ (posedge clock)\r
- begin : FSM\r
- if (reset == 1'b1) begin\r
-   state <=  #1  IDLE;\r
-   gnt_0 <= 0;\r
-   gnt_1 <= 0;\r
- end else\r
-  case(state)\r
-    IDLE : if (req_0 == 1'b1) begin\r
-                 state <=  #1  GNT0;\r
-                 gnt_0 <= 1;\r
-               end else if (req_1 == 1'b1) begin\r
-                 gnt_1 <= 1;\r
-                 state <=  #1  GNT0;\r
-               end else begin\r
-                 state <=  #1  IDLE;\r
-               end\r
-    GNT0 : if (req_0 == 1'b1) begin\r
-                 state <=  #1  GNT0;\r
-               end else begin\r
-                 gnt_0 <= 0;\r
-                 state <=  #1  IDLE;\r
-               end\r
-    GNT1 : if (req_1 == 1'b1) begin\r
-                 state <=  #1  GNT2;\r
-                                gnt_1 <= req_0;\r
-               end\r
-    GNT2 : if (req_0 == 1'b1) begin\r
-                 state <=  #1  GNT1;\r
-                                gnt_1 <= req_1;\r
-               end\r
-    default : state <=  #1  IDLE;\r
- endcase\r
- end\r
+    reg [SIZE-1:0] state;\r
+    reg [SIZE-1:0] next_state;\r
 \r
+    always @ (posedge clock)\r
+        begin : FSM\r
+          if (reset == 1'b1) begin\r
+            state <=  #1  IDLE;\r
+            gnt_0 <= 0;\r
+            gnt_1 <= 0;\r
+          end \r
+          else\r
+            case(state)\r
+              IDLE :  if (req_0 == 1'b1) begin\r
+                          state <=  #1  GNT0;\r
+                          gnt_0 <= 1;\r
+                      end else if (req_1 == 1'b1) begin\r
+                          gnt_1 <= 1;\r
+                          state <=  #1  GNT0;\r
+                      end else begin\r
+                          state <=  #1  IDLE;\r
+                      end\r
+              GNT0 :  if (req_0 == 1'b1) begin\r
+                          state <=  #1  GNT0;\r
+                      end else begin\r
+                          gnt_0 <= 0;\r
+                          state <=  #1  IDLE;\r
+                      end\r
+              GNT1 :  if (req_1 == 1'b1) begin\r
+                          state <=  #1  GNT2;\r
+                          gnt_1 <= req_0;\r
+                      end\r
+              GNT2 :  if (req_0 == 1'b1) begin\r
+                          state <=  #1  GNT1;\r
+                          gnt_1 <= req_1;\r
+                      end\r
+              default : state <=  #1  IDLE;\r
+            endcase\r
+        end\r
 endmodule\r

diff --git a/tests/arch/common/latches.v b/tests/arch/common/latches.v
index adb5d5319fd57e35366e2bb013fd0ff57d414bb5..60b7571030d91f531f1e9bd892643bdc690581ad 100644 (file)
--- a/tests/arch/common/latches.v
+++ b/tests/arch/common/latches.v
@@ -1,19 +1,16 @@
-module latchp
-    ( input d, clk, en, output reg q );
+module latchp ( input d, clk, en, output reg q );
        always @*
                if ( en )
                        q <= d;
 endmodule
 
-module latchn
-    ( input d, clk, en, output reg q );
+module latchn ( input d, clk, en, output reg q );
        always @*
                if ( !en )
                        q <= d;
 endmodule
 
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
+module latchsr ( input d, clk, en, clr, pre, output reg q );
        always @*
                if ( clr )
                        q <= 1'b0;

diff --git a/tests/arch/common/logic.v b/tests/arch/common/logic.v
index e5343cae08447263d00639bc95337ae6d8a6aed7..c17899fa0e123395f05a8359bbb4423da17565b5 100644 (file)
--- a/tests/arch/common/logic.v
+++ b/tests/arch/common/logic.v
@@ -1,18 +1,16 @@
 module top
 (
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
-   assign     B1 =  in[0] & in[1];
-   assign     B2 =  in[0] | in[1];
-   assign     B3 =  in[0] ~& in[1];
-   assign     B4 =  in[0] ~| in[1];
-   assign     B5 =  in[0] ^ in[1];
-   assign     B6 =  in[0] ~^ in[1];
-   assign     B7 =  ~in[0];
-   assign     B8 =  in[0];
-   assign     B9 =  in[0:1] && in [2:3];
-   assign     B10 =  in[0:1] || in [2:3];
-
+    input [0:7] in,
+    output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
+);
+    assign B1 =  in[0] & in[1];
+    assign B2 =  in[0] | in[1];
+    assign B3 =  in[0] ~& in[1];
+    assign B4 =  in[0] ~| in[1];
+    assign B5 =  in[0] ^ in[1];
+    assign B6 =  in[0] ~^ in[1];
+    assign B7 =  ~in[0];
+    assign B8 =  in[0];
+    assign B9 =  in[0:1] && in [2:3];
+    assign B10 =  in[0:1] || in [2:3];
 endmodule

diff --git a/tests/arch/common/mul.v b/tests/arch/common/mul.v
index d5b48b1d7721790eeb2028641875cdf0115a2b0b..437a91cfcfd6b39f9756693e11d357d5f580d0c4 100644 (file)
--- a/tests/arch/common/mul.v
+++ b/tests/arch/common/mul.v
@@ -1,11 +1,9 @@
 module top
 (
- input [5:0] x,
- input [5:0] y,
-
- output [11:0] A,
- );
-
-assign A =  x * y;
+    input [5:0] x,
+    input [5:0] y,
 
+    output [11:0] A,
+);
+    assign A =  x * y;
 endmodule

diff --git a/tests/arch/common/mux.v b/tests/arch/common/mux.v
index 27bc0bf0b29484caa56e248ac706355bedee32b3..71c1ac7f2e21a140a792e96733137ef641b3feba 100644 (file)
--- a/tests/arch/common/mux.v
+++ b/tests/arch/common/mux.v
@@ -8,51 +8,47 @@ module mux2 (S,A,B,Y);
 endmodule
 
 module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
+    input[1:0] S;
+    input[3:0] D;
+    output Y;
+
+    reg Y;
+    wire[1:0] S;
+    wire[3:0] D;
+
+    always @*
+    begin
+        case( S )
+            0 : Y = D[0];
+            1 : Y = D[1];
+            2 : Y = D[2];
+            3 : Y = D[3];
+        endcase
+    end
 endmodule
 
 module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
+    input[2:0] S;
+    input[7:0] D;
+    output Y;
+
+    reg Y;
+    wire[2:0] S;
+    wire[7:0] D;
+
+    always @*
+    begin
+        case( S )
+            0 : Y = D[0];
+            1 : Y = D[1];
+            2 : Y = D[2];
+            3 : Y = D[3];
+            4 : Y = D[4];
+            5 : Y = D[5];
+            6 : Y = D[6];
+            7 : Y = D[7];
+        endcase
+    end
 endmodule
 
 module mux16 (D, S, Y);
@@ -60,6 +56,5 @@ module mux16 (D, S, Y);
        input  [3:0] S;
        output Y;
 
-assign Y = D[S];
-
+    assign Y = D[S];
 endmodule

diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v
index 04ae49d831f89b11863e1a6cde708b0b6d8a638e..cace3b5889ad49d3eb9157322169b2087a991bf3 100644 (file)
--- a/tests/arch/common/shifter.v
+++ b/tests/arch/common/shifter.v
@@ -1,8 +1,4 @@
-module top    (\r
-out,\r
-clk,\r
-in\r
-);\r
+module top(out, clk, in);\r
     output [7:0] out;\r
     input signed clk, in;\r
     reg signed [7:0] out = 0;\r
@@ -11,6 +7,5 @@ in
        begin\r
                out    <= out >> 1;\r
                out[7] <= in;\r
-       end\r
-\r
+       end    \r
 endmodule\r

diff --git a/tests/arch/common/tribuf.v b/tests/arch/common/tribuf.v
index c6446825342680e9b587ad1453b53aad4cbff0a4..e1d701611eb579a17e04f12e1aea970e3cb47fa6 100644 (file)
--- a/tests/arch/common/tribuf.v
+++ b/tests/arch/common/tribuf.v
@@ -1,8 +1,8 @@
-module tristate (en, i, o);
+module tristate(en, i, o);
     input en;
     input i;
     output reg o;
-    
+
     always @(en or i)
-               o <= (en)? i : 1'bZ;
+        o <= (en)? i : 1'bZ;
 endmodule