RISC-V: Fix SLTI disassembly

2017-06-23  Andrew Waterman  <andrew@sifive.com>

	* riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
	alias; do not mark SLTI instruction as an alias.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b2e772902419c450454bb0f4f985cc7f2f5ae21d..5371bbb57b3b59cc2740f60787c0f3af8cce41df 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-06-23  Andrew Waterman  <andrew@sifive.com>
+
+       * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
+       alias; do not mark SLTI instruction as an alias.
+
 2017-06-21  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-dis.c (RM_0FAE_REG_5): Removed.

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 0188a653f20be00d1b0b657ff3d86e631c430865..9914c44744295a31344b88c78884708ede0d0f21 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -245,9 +245,9 @@ const struct riscv_opcode riscv_opcodes[] =
 {"snez",      "I",   "d,t",  MATCH_SLTU, MASK_SLTU | MASK_RS1, match_opcode, INSN_ALIAS },
 {"sltz",      "I",   "d,s",  MATCH_SLT, MASK_SLT | MASK_RS2, match_opcode, INSN_ALIAS },
 {"sgtz",      "I",   "d,t",  MATCH_SLT, MASK_SLT | MASK_RS1, match_opcode, INSN_ALIAS },
-{"slti",      "I",   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS },
+{"slti",      "I",   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
 {"slt",       "I",   "d,s,t",  MATCH_SLT, MASK_SLT, match_opcode, 0 },
-{"slt",       "I",   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode, 0 },
+{"slt",       "I",   "d,s,j",  MATCH_SLTI, MASK_SLTI, match_opcode, INSN_ALIAS },
 {"sltiu",     "I",   "d,s,j",  MATCH_SLTIU, MASK_SLTIU, match_opcode, 0 },
 {"sltu",      "I",   "d,s,t",  MATCH_SLTU, MASK_SLTU, match_opcode, 0 },
 {"sltu",      "I",   "d,s,j",  MATCH_SLTIU, MASK_SLTIU, match_opcode, INSN_ALIAS },