cpu/microwatt: fix integration/crt0.S (thanks Benjamin Herrenschmidt).

Tested on Arty A7:

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      / /__/ / __/ -_)>  <
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   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on May  4 2020 17:15:13
 BIOS CRC passed (0adc4193)

 Migen git sha1: 5b5e4fd
 LiteX git sha1: 6f24d46d

--=============== SoC ==================--
CPU:       Microwatt @ 100MHz
ROM:       32KB
SRAM:      4KB
L2:        8KB
MAIN-RAM:  262144KB

--========== Initialization ============--
Initializing SDRAM...
SDRAM now under software control
Read leveling:
m0, b0: |00000000000000000000000000000000| delays: -
m0, b1: |00000000000000000000000000000000| delays: -
m0, b2: |00000000000000000000000000000000| delays: -
m0, b3: |00000000000000000000000000000000| delays: -
m0, b4: |00000000000000000000000000000000| delays: -
m0, b5: |00000000000000000000000000000000| delays: -
m0, b6: |00000111111111111100000000000000| delays: 11+-06
m0, b7: |00000000000000000000000000000000| delays: -
best: m0, b6 delays: 11+-06
m1, b0: |00000000000000000000000000000000| delays: -
m1, b1: |00000000000000000000000000000000| delays: -
m1, b2: |00000000000000000000000000000000| delays: -
m1, b3: |00000000000000000000000000000000| delays: -
m1, b4: |00000000000000000000000000000000| delays: -
m1, b5: |10000000000000000000000000000000| delays: 00+-00
m1, b6: |00000011111111111100000000000000| delays: 12+-06
m1, b7: |00000000000000000000000000000000| delays: -
best: m1, b6 delays: 12+-06
SDRAM now under hardware control
Memtest OK
Memspeed Writes: 129Mbps Reads: 215Mbps

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>

diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index ca4aae2bcedbc693a556cd30150a49f4b78a31a9..81802f345df5111f4c5fb67a3448b34c56dd2806 100644 (file)
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -47,8 +47,8 @@ class Microwatt(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
-        self.wb_insn      = wb_insn = wishbone.Interface(data_width=64, adr_width=28)
-        self.wb_data      = wb_data = wishbone.Interface(data_width=64, adr_width=28)
+        self.wb_insn      = wb_insn = wishbone.Interface(data_width=64, adr_width=29)
+        self.wb_data      = wb_data = wishbone.Interface(data_width=64, adr_width=29)
         self.periph_buses = [wb_insn, wb_data]
         self.memory_buses = []
 
@@ -64,7 +64,7 @@ class Microwatt(CPU):
             i_wishbone_insn_ack   = wb_insn.ack,
             i_wishbone_insn_stall = wb_insn.cyc & ~wb_insn.ack, # No burst support
 
-            o_wishbone_insn_adr   = Cat(Signal(4), wb_insn.adr),
+            o_wishbone_insn_adr   = Cat(Signal(3), wb_insn.adr),
             o_wishbone_insn_dat_w = wb_insn.dat_w,
             o_wishbone_insn_cyc   = wb_insn.cyc,
             o_wishbone_insn_stb   = wb_insn.stb,
@@ -76,7 +76,7 @@ class Microwatt(CPU):
             i_wishbone_data_ack   = wb_data.ack,
             i_wishbone_data_stall = wb_data.cyc & ~wb_data.ack, # No burst support
 
-            o_wishbone_data_adr   = Cat(Signal(4), wb_data.adr),
+            o_wishbone_data_adr   = Cat(Signal(3), wb_data.adr),
             o_wishbone_data_dat_w = wb_data.dat_w,
             o_wishbone_data_cyc   = wb_data.cyc,
             o_wishbone_data_stb   = wb_data.stb,

diff --git a/litex/soc/cores/cpu/microwatt/crt0.S b/litex/soc/cores/cpu/microwatt/crt0.S
index 0dd6f343b5d6bee309572af68e8ed9b4cdbcdd01..e03ac0bb4be6e07239efb0cbb9c7724c3badf3c2 100644 (file)
--- a/litex/soc/cores/cpu/microwatt/crt0.S
+++ b/litex/soc/cores/cpu/microwatt/crt0.S
@@ -14,8 +14,6 @@
  * limitations under the License.
  */
 
-#define STACK_TOP      0xffff4000
-
 #define FIXUP_ENDIAN                                              \
        tdi   0,0,0x48;   /* Reverse endian of b . + 8          */ \
        b     191f;       /* Skip trampoline if endian is good  */ \
@@ -38,24 +36,17 @@
        oris    r,r, (e)@h;                     \
        ori     r,r, (e)@l;
 
-       .section ".head","ax"
-
        . = 0
 .global _start
 _start:
        FIXUP_ENDIAN
 
        /* setup stack */
-       LOAD_IMM64(%r1, STACK_TOP - 0x100)
+       LOAD_IMM64(%r1, _fstack - 0x100)
        LOAD_IMM64(%r12, main)
        mtctr   %r12,
        bctrl
-       ba      0
-
-       /* XXX: litedram init should not take exceptions, maybe we could get
-        *      rid of these to save space, along with a core tweak to suppress
-        *      exceptions in case they happen (just terminate ?)
-        */
+       b .
 
 #define EXCEPTION(nr)          \
        .=  nr;      \