Handle __dummy_o__ and __const[01]__ in read_aiger not abc

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 7e91c8cac97b1d178f2805d14b37d4363d6ac536..e35a8ad62cfcb32d58f370d30fca1563d59b6f25 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -477,6 +477,10 @@ next_line:
                 RTLIL::Wire* wire = outputs[variable];
                 log_assert(wire);
                 log_assert(wire->port_output);
+                if (escaped_s.in("__dummy_o__", "__const0__", "__const1__")) {
+                    wire->port_output = false;
+                    continue;
+                }
 
                 if (index == 0) {
                     // Cope with the fact that a CO might be identical

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 52b1b6d35c7878bc982554e27522fb52578a429a..edc07092b4c51ffad9acde0fe5165707d5359558 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -546,11 +546,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                                                output_bits.insert({wire, i});
                                }
                                else {
-                                       if (w->name.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) {
-                                               //log("Don't call ABC as there is nothing to map.\n");
-                                               //goto cleanup;
-                                               continue;
-                                       }
+                                       //if (w->name == "\\__dummy_o__") {
+                                       //      log("Don't call ABC as there is nothing to map.\n");
+                                       //      goto cleanup;
+                                       //}
 
                                        // Attempt another wideports_split here because there
                                        // exists the possibility that different bits of a port
@@ -875,19 +874,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                        RTLIL::Wire *w = it.second;
                        if (!w->port_input && !w->port_output)
                                continue;
-                       if (w->name == "\\__const0__") {
-                               log_assert(w->port_output);
-                               module->connect(w, RTLIL::S0);
-                               continue;
-                       }
-                       if (w->name == "\\__const1__") {
-                               log_assert(w->port_output);
-                               module->connect(w, RTLIL::S1);
-                               continue;
-                       }
-                       if (w->name == "\\__dummy_o__")
-                               continue;
-
                        RTLIL::Wire *wire = module->wire(w->name);
                        RTLIL::Wire *remap_wire = module->wire(remap_name(w->name));
                        RTLIL::SigSpec signal;