i965/icl: Add assertions to check dispatch mode is SIMD8
authorAnuj Phogat <anuj.phogat@gmail.com>
Wed, 7 Feb 2018 00:47:04 +0000 (16:47 -0800)
committerAnuj Phogat <anuj.phogat@gmail.com>
Fri, 16 Feb 2018 00:14:56 +0000 (16:14 -0800)
SIMD4x2 dispatch mode has been removed in GEN11. We're not using
it anyways in Mesa. Adding few asserts to make it explicit.

Use GEN_GEN macro in place of devinfo->gen (Ken)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
src/intel/blorp/blorp_genX_exec.h
src/mesa/drivers/dri/i965/genX_state_upload.c

index 0fcb94f1c5d814a0e9dcfae5810afa9d98f13a80..737720a70c9d1b1819a781bc290cd93aa1f966d4 100644 (file)
@@ -572,6 +572,8 @@ blorp_emit_vs_config(struct blorp_batch *batch,
                      const struct blorp_params *params)
 {
    struct brw_vs_prog_data *vs_prog_data = params->vs_prog_data;
+   assert(!vs_prog_data || GEN_GEN < 11 ||
+          vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
 
    blorp_emit(batch, GENX(3DSTATE_VS), vs) {
       if (vs_prog_data) {
index b171c4f171cb26cb0ee94b3afcc7851a2492ae00..8668abd591f94f0de0203c64b73374101b92403d 100644 (file)
@@ -2050,6 +2050,8 @@ genX(upload_vs_state)(struct brw_context *brw)
 
    assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8 ||
           vue_prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT);
+   assert(GEN_GEN < 11 ||
+          vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
 
 #if GEN_GEN == 6
    /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
@@ -3967,6 +3969,9 @@ genX(upload_ds_state)(struct brw_context *brw)
    if (!tes_prog_data) {
       brw_batch_emit(brw, GENX(3DSTATE_DS), ds);
    } else {
+      assert(GEN_GEN < 11 ||
+             vue_prog_data->dispatch_mode == DISPATCH_MODE_SIMD8);
+
       brw_batch_emit(brw, GENX(3DSTATE_DS), ds) {
          INIT_THREAD_DISPATCH_FIELDS(ds, Patch);