single-cycle mode fix on wb "wen" signal, must hold fully until ACKed

diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py
index 1197e38f65c347501f10cb7cfc1fcd7cdc03d92a..1f3d424cbd7451c0434e0c71168f5aa0935af860 100755 (executable)
--- a/c4m/nmigen/jtag/tap.py
+++ b/c4m/nmigen/jtag/tap.py
@@ -800,6 +800,7 @@ class TAP(Elaboratable):
                 if hasattr(wb, "stall"):
                     m.d.comb += wb.stb.eq(fsm.ongoing("READ") |
                                           fsm.ongoing("WRITEREAD"))
+                    m.d.comb += wb.we.eq(fsm.ongoing("WRITEREAD"))
                 else:
                     # non-stall is single-cycle (litex), must assert stb
                     # until ack is sent
@@ -807,7 +808,6 @@ class TAP(Elaboratable):
                                           fsm.ongoing("WRITEREAD") |
                                           fsm.ongoing("READACK") |
                                           fsm.ongoing("WRITEREADACK"))
-                m.d.comb += [
-                    wb.cyc.eq(~fsm.ongoing("IDLE")),
-                    wb.we.eq(fsm.ongoing("WRITEREAD")),
-                ]
+                    m.d.comb += wb.we.eq(fsm.ongoing("WRITEREAD") |
+                                         fsm.ongoing("WRITEREADACK"))
+                m.d.comb += wb.cyc.eq(~fsm.ongoing("IDLE"))