It doesn't make sense to have nonlinear layouts for a buffer that can be
accessed as direct memory for a compute kernel. Turn that off so things
work as expected.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
bool is_texture = (res->bind & PIPE_BIND_SAMPLER_VIEW);
bool is_2d = res->depth0 == 1 && res->array_size == 1;
bool is_streaming = (res->usage != PIPE_USAGE_STREAM);
+ bool is_global = res->bind & PIPE_BIND_GLOBAL;
- bool should_tile = is_streaming && is_texture && is_2d;
+ bool should_tile = is_streaming && is_texture && is_2d && !is_global;
/* Depth/stencil can't be tiled, only linear or AFBC */
should_tile &= !(res->bind & PIPE_BIND_DEPTH_STENCIL);