radeon/vcn2: enable rate control for hevc encoding

Based on b0626c1f306 ("radeon/vcn: enable rate control for hevc encoding").

Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2225
Fixes: 587b9c5dae6 ("radeon/vcn: implement vcn 2.0 encode")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3134>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3134>

diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c b/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c
index d2c6378a055543c81aaf55b8dff86e502fa833d7..580a084a1c1764f8d3617dd634dd999d84e59ea1 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_2_0.c
@@ -196,7 +196,13 @@ static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
        radeon_enc_code_se(enc, 0x0);
        radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
        radeon_enc_code_fixed_bits(enc, 0x0, 1);
-       radeon_enc_code_fixed_bits(enc, 0x0, 1);
+       if (enc->enc_pic.rc_session_init.rate_control_method ==
+               RENCODE_RATE_CONTROL_METHOD_NONE)
+               radeon_enc_code_fixed_bits(enc, 0x0, 1);
+       else {
+               radeon_enc_code_fixed_bits(enc, 0x1, 1);
+               radeon_enc_code_ue(enc, 0x0);
+       }
        radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
        radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
        radeon_enc_code_fixed_bits(enc, 0x0, 1);