struct r300_capabilities* caps = r300_screen(r300->context.screen)->caps;
CS_LOCALS(r300);
- BEGIN_CS(14);
+ BEGIN_CS(16);
/* Amount of time to wait for vertex fetches in PVS */
OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff);
/* Various GB enables */
OUT_CS_REG(R300_GB_SELECT, R300_GB_FOG_SELECT_1_1_W);
/* AA enable */
OUT_CS_REG(R300_GB_AA_CONFIG, 0x0);
+ /* GA errata fixes. */
+ if (caps->is_r500) {
+ OUT_CS_REG(R300_GA_ENHANCE,
+ R300_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL |
+ R300_GA_ENHANCE_FASTSYNC_CNTL_ENABLE |
+ R500_GA_ENHANCE_REG_READWRITE_ENABLE |
+ R500_GA_ENHANCE_REG_NOSTALL_ENABLE);
+ } else {
+ OUT_CS_REG(R300_GA_ENHANCE,
+ R300_GA_ENHANCE_DEADLOCK_CNTL_PREVENT_TCL |
+ R300_GA_ENHANCE_FASTSYNC_CNTL_ENABLE);
+ }
END_CS;
}
r300_emit_rs_block_state(r300, &r300_rs_block_clear_state);
}
- BEGIN_CS(124 + (caps->has_tcl ? 2 : 0));
+ BEGIN_CS(122 + (caps->has_tcl ? 2 : 0));
/* Flush PVS. */
OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0x0);
/* XXX this big chunk should be refactored into rs_state */
OUT_CS_REG(R300_GA_LINE_S0, 0x00000000);
OUT_CS_REG(R300_GA_LINE_S1, 0x3F800000);
- OUT_CS_REG(R300_GA_ENHANCE, 0x00000002);
OUT_CS_REG(R300_GA_SOLID_RG, 0x00000000);
OUT_CS_REG(R300_GA_SOLID_BA, 0x00000000);
OUT_CS_REG(R300_GA_POLY_MODE, 0x00000000);