--- /dev/null
+//===-- AMDGPUCodeEmitter.h - AMDGPU Code Emitter interface -----------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// CodeEmitter interface for R600 and SI codegen.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef AMDGPUCODEEMITTER_H
+#define AMDGPUCODEEMITTER_H
+
+namespace llvm {
+
+ class AMDGPUCodeEmitter {
+ public:
+ uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
+ virtual uint64_t getMachineOpValue(const MachineInstr &MI,
+ const MachineOperand &MO) const { return 0; }
+ virtual unsigned GPR4AlignEncode(const MachineInstr &MI,
+ unsigned OpNo) const {
+ return 0;
+ }
+ virtual unsigned GPR2AlignEncode(const MachineInstr &MI,
+ unsigned OpNo) const {
+ return 0;
+ }
+ virtual uint64_t VOPPostEncode(const MachineInstr &MI,
+ uint64_t Value) const {
+ return Value;
+ }
+ virtual uint64_t i32LiteralEncode(const MachineInstr &MI,
+ unsigned OpNo) const {
+ return 0;
+ }
+ virtual uint32_t SMRDmemriEncode(const MachineInstr &MI, unsigned OpNo)
+ const {
+ return 0;
+ }
+ };
+
+} // End namespace llvm
+
+#endif // AMDGPUCODEEMITTER_H
--- /dev/null
+
+#include "AMDGPUSubtarget.h"
+
+using namespace llvm;
+
+#define GET_SUBTARGETINFO_ENUM
+#define GET_SUBTARGETINFO_TARGET_DESC
+#include "AMDGPUGenSubtargetInfo.inc"
+
+AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
+ AMDILSubtarget(TT, CPU, FS) {
+ InstrItins = getInstrItineraryForCPU(CPU);
+
+ memset(CapsOverride, 0, sizeof(*CapsOverride)
+ * AMDILDeviceInfo::MaxNumberCapabilities);
+ // Default card
+ std::string GPU = "rv770";
+ GPU = CPU;
+ mIs64bit = false;
+ mVersion = 0;
+ SmallVector<StringRef, DEFAULT_VEC_SLOTS> Features;
+ SplitString(FS, Features, ",");
+ mDefaultSize[0] = 64;
+ mDefaultSize[1] = 1;
+ mDefaultSize[2] = 1;
+ std::string newFeatures = "";
+#if defined(_DEBUG) || defined(DEBUG)
+ bool useTest = false;
+#endif
+ for (size_t x = 0; x < Features.size(); ++x) {
+ if (Features[x].startswith("+mwgs")) {
+ SmallVector<StringRef, DEFAULT_VEC_SLOTS> sizes;
+ SplitString(Features[x], sizes, "-");
+ size_t mDim = ::atoi(sizes[1].data());
+ if (mDim > 3) {
+ mDim = 3;
+ }
+ for (size_t y = 0; y < mDim; ++y) {
+ mDefaultSize[y] = ::atoi(sizes[y+2].data());
+ }
+#if defined(_DEBUG) || defined(DEBUG)
+ } else if (!Features[x].compare("test")) {
+ useTest = true;
+#endif
+ } else if (Features[x].startswith("+cal")) {
+ SmallVector<StringRef, DEFAULT_VEC_SLOTS> version;
+ SplitString(Features[x], version, "=");
+ mVersion = ::atoi(version[1].data());
+ } else {
+ GPU = CPU;
+ if (x > 0) newFeatures += ',';
+ newFeatures += Features[x];
+ }
+ }
+ // If we don't have a version then set it to
+ // -1 which enables everything. This is for
+ // offline devices.
+ if (!mVersion) {
+ mVersion = (uint32_t)-1;
+ }
+ for (int x = 0; x < 3; ++x) {
+ if (!mDefaultSize[x]) {
+ mDefaultSize[x] = 1;
+ }
+ }
+#if defined(_DEBUG) || defined(DEBUG)
+ if (useTest) {
+ GPU = "kauai";
+ }
+#endif
+ ParseSubtargetFeatures(GPU, newFeatures);
+#if defined(_DEBUG) || defined(DEBUG)
+ if (useTest) {
+ GPU = "test";
+ }
+#endif
+ mDevName = GPU;
+ mDevice = AMDILDeviceInfo::getDeviceFromName(mDevName, this, mIs64bit);
+}
#ifndef _AMDGPUSUBTARGET_H_
#define _AMDGPUSUBTARGET_H_
#include "AMDILSubtarget.h"
+#include "llvm/ADT/StringExtras.h"
+#include "llvm/ADT/StringRef.h"
namespace llvm {
InstrItineraryData InstrItins;
public:
- AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS) :
- AMDILSubtarget(TT, CPU, FS)
- {
- InstrItins = getInstrItineraryForCPU(CPU);
- }
+ AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS);
const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
+ virtual void ParseSubtargetFeatures(llvm::StringRef CPU, llvm::StringRef FS);
+
};
} // End namespace llvm
//===----------------------------------------------------------------------===//
// Declare the target which we are implementing
//===----------------------------------------------------------------------===//
-def AMDILAsmWriter : AsmWriter {
- string AsmWriterClassName = "AsmPrinter";
+def AMDGPUAsmWriter : AsmWriter {
+ string AsmWriterClassName = "InstPrinter";
int Variant = 0;
+ bit isMCAsmWriter = 1;
}
def AMDILAsmParser : AsmParser {
}
-def AMDIL : Target {
+def AMDGPU : Target {
// Pull in Instruction Info:
let InstructionSet = AMDILInstrInfo;
- let AssemblyWriters = [AMDILAsmWriter];
+ let AssemblyWriters = [AMDGPUAsmWriter];
let AssemblyParsers = [AMDILAsmParser];
}
+++ /dev/null
-//===-- AMDILCodeEmitter.h - AMDIL Code Emitter interface -----------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// CodeEmitter interface for R600 and SI codegen.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef AMDILCODEEMITTER_H
-#define AMDILCODEEMITTER_H
-
-namespace llvm {
-
- class AMDILCodeEmitter {
- public:
- uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
- virtual uint64_t getMachineOpValue(const MachineInstr &MI,
- const MachineOperand &MO) const { return 0; }
- virtual unsigned GPR4AlignEncode(const MachineInstr &MI,
- unsigned OpNo) const {
- return 0;
- }
- virtual unsigned GPR2AlignEncode(const MachineInstr &MI,
- unsigned OpNo) const {
- return 0;
- }
- virtual uint64_t VOPPostEncode(const MachineInstr &MI,
- uint64_t Value) const {
- return Value;
- }
- virtual uint64_t i32LiteralEncode(const MachineInstr &MI,
- unsigned OpNo) const {
- return 0;
- }
- virtual uint32_t SMRDmemriEncode(const MachineInstr &MI, unsigned OpNo)
- const {
- return 0;
- }
- };
-
-} // End namespace llvm
-
-#endif // AMDILCODEEMITTER_H
using namespace llvm;
AMDILInstrInfo::AMDILInstrInfo(TargetMachine &tm)
- : AMDILGenInstrInfo(),
+ : AMDGPUGenInstrInfo(),
RI(tm, *this),
TM(tm) {
}
// instruction info tracks.
//
//class AMDILTargetMachine;
-class AMDILInstrInfo : public AMDILGenInstrInfo {
+class AMDILInstrInfo : public AMDGPUGenInstrInfo {
private:
const AMDILRegisterInfo RI;
TargetMachine &TM;
AMDILRegisterInfo::AMDILRegisterInfo(TargetMachine &tm,
const TargetInstrInfo &tii)
-: AMDILGenRegisterInfo(0), // RA???
+: AMDGPUGenRegisterInfo(0), // RA???
TM(tm), TII(tii)
{
baseOffset = 0;
};
}
- struct AMDILRegisterInfo : public AMDILGenRegisterInfo
+ struct AMDILRegisterInfo : public AMDGPUGenRegisterInfo
{
TargetMachine &TM;
const TargetInstrInfo &TII;
#include "AMDILDevices.h"
#include "AMDILUtilityFunctions.h"
#include "llvm/ADT/SmallVector.h"
-#include "llvm/ADT/StringExtras.h"
-#include "llvm/ADT/StringRef.h"
#include "llvm/MC/SubtargetFeature.h"
using namespace llvm;
-#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_CTOR
-#define GET_SUBTARGETINFO_TARGET_DESC
#include "AMDGPUGenSubtargetInfo.inc"
-AMDILSubtarget::AMDILSubtarget(llvm::StringRef TT, llvm::StringRef CPU, llvm::StringRef FS) : AMDILGenSubtargetInfo( TT, CPU, FS ),
+AMDILSubtarget::AMDILSubtarget(llvm::StringRef TT, llvm::StringRef CPU, llvm::StringRef FS) : AMDGPUGenSubtargetInfo( TT, CPU, FS ),
mDumpCode(false)
{
- memset(CapsOverride, 0, sizeof(*CapsOverride)
- * AMDILDeviceInfo::MaxNumberCapabilities);
- // Default card
- std::string GPU = "rv770";
- GPU = CPU;
- mIs64bit = false;
- mVersion = 0;
- SmallVector<StringRef, DEFAULT_VEC_SLOTS> Features;
- SplitString(FS, Features, ",");
- mDefaultSize[0] = 64;
- mDefaultSize[1] = 1;
- mDefaultSize[2] = 1;
- std::string newFeatures = "";
-#if defined(_DEBUG) || defined(DEBUG)
- bool useTest = false;
-#endif
- for (size_t x = 0; x < Features.size(); ++x) {
- if (Features[x].startswith("+mwgs")) {
- SmallVector<StringRef, DEFAULT_VEC_SLOTS> sizes;
- SplitString(Features[x], sizes, "-");
- size_t mDim = ::atoi(sizes[1].data());
- if (mDim > 3) {
- mDim = 3;
- }
- for (size_t y = 0; y < mDim; ++y) {
- mDefaultSize[y] = ::atoi(sizes[y+2].data());
- }
-#if defined(_DEBUG) || defined(DEBUG)
- } else if (!Features[x].compare("test")) {
- useTest = true;
-#endif
- } else if (Features[x].startswith("+cal")) {
- SmallVector<StringRef, DEFAULT_VEC_SLOTS> version;
- SplitString(Features[x], version, "=");
- mVersion = ::atoi(version[1].data());
- } else {
- GPU = CPU;
- if (x > 0) newFeatures += ',';
- newFeatures += Features[x];
- }
- }
- // If we don't have a version then set it to
- // -1 which enables everything. This is for
- // offline devices.
- if (!mVersion) {
- mVersion = (uint32_t)-1;
- }
- for (int x = 0; x < 3; ++x) {
- if (!mDefaultSize[x]) {
- mDefaultSize[x] = 1;
- }
- }
-#if defined(_DEBUG) || defined(DEBUG)
- if (useTest) {
- GPU = "kauai";
- }
-#endif
- ParseSubtargetFeatures(GPU, newFeatures);
-#if defined(_DEBUG) || defined(DEBUG)
- if (useTest) {
- GPU = "test";
- }
-#endif
- mDevName = GPU;
- mDevice = AMDILDeviceInfo::getDeviceFromName(mDevName, this, mIs64bit);
}
AMDILSubtarget::~AMDILSubtarget()
{
class AMDILKernelManager;
class AMDILGlobalManager;
class AMDILDevice;
- class AMDILSubtarget : public AMDILGenSubtargetInfo {
- private:
+ class AMDILSubtarget : public AMDGPUGenSubtargetInfo {
+ protected:
bool CapsOverride[AMDILDeviceInfo::MaxNumberCapabilities];
mutable AMDILGlobalManager *mGM;
mutable AMDILKernelManager *mKM;
// ParseSubtargetFeatures - Parses features string setting specified
// subtarget options. Definition of function is
//auto generated by tblgen.
- void
+ virtual void
ParseSubtargetFeatures(
llvm::StringRef CPU,
- llvm::StringRef FS);
+ llvm::StringRef FS) { assert(!"Unimplemented"); }
bool dumpCode() const { return mDumpCode; }
};
using namespace llvm;
-static MCInstrInfo *createAMDILMCInstrInfo() {
+static MCInstrInfo *createAMDGPUMCInstrInfo() {
MCInstrInfo *X = new MCInstrInfo();
- InitAMDILMCInstrInfo(X);
+ InitAMDGPUMCInstrInfo(X);
return X;
}
-static MCRegisterInfo *createAMDILMCRegisterInfo(StringRef TT) {
+static MCRegisterInfo *createAMDGPUMCRegisterInfo(StringRef TT) {
MCRegisterInfo *X = new MCRegisterInfo();
- InitAMDILMCRegisterInfo(X, 0);
+ InitAMDGPUMCRegisterInfo(X, 0);
return X;
}
-static MCSubtargetInfo *createAMDILMCSubtargetInfo(StringRef TT, StringRef CPU,
+static MCSubtargetInfo *createAMDGPUMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) {
MCSubtargetInfo * X = new MCSubtargetInfo();
- InitAMDILMCSubtargetInfo(X, TT, CPU, FS);
+ InitAMDGPUMCSubtargetInfo(X, TT, CPU, FS);
return X;
}
-static MCCodeGenInfo *createAMDILMCCodeGenInfo(StringRef TT, Reloc::Model RM,
+static MCCodeGenInfo *createAMDGPUMCCodeGenInfo(StringRef TT, Reloc::Model RM,
CodeModel::Model CM,
CodeGenOpt::Level OL) {
MCCodeGenInfo *X = new MCCodeGenInfo();
RegisterMCAsmInfo<AMDILMCAsmInfo> Y(TheAMDGPUTarget);
- TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDILMCCodeGenInfo);
+ TargetRegistry::RegisterMCCodeGenInfo(TheAMDGPUTarget, createAMDGPUMCCodeGenInfo);
- TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDILMCInstrInfo);
+ TargetRegistry::RegisterMCInstrInfo(TheAMDGPUTarget, createAMDGPUMCInstrInfo);
- TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDILMCRegisterInfo);
+ TargetRegistry::RegisterMCRegInfo(TheAMDGPUTarget, createAMDGPUMCRegisterInfo);
- TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDILMCSubtargetInfo);
+ TargetRegistry::RegisterMCSubtargetInfo(TheAMDGPUTarget, createAMDGPUMCSubtargetInfo);
}
AMDILRegisterInfo.cpp \
AMDILSIDevice.cpp \
AMDILSubtarget.cpp \
+ AMDGPUSubtarget.cpp \
AMDGPUTargetMachine.cpp \
AMDGPUISelLowering.cpp \
AMDGPUConvertToISA.cpp \
//===----------------------------------------------------------------------===//
#include "AMDGPU.h"
+#include "AMDGPUCodeEmitter.h"
#include "AMDGPUUtil.h"
-#include "AMDILCodeEmitter.h"
#include "AMDILInstrInfo.h"
#include "AMDILUtilityFunctions.h"
#include "R600InstrInfo.h"
namespace {
-class R600CodeEmitter : public MachineFunctionPass, public AMDILCodeEmitter {
+class R600CodeEmitter : public MachineFunctionPass, public AMDGPUCodeEmitter {
private:
#include "AMDGPU.h"
+#include "AMDGPUCodeEmitter.h"
#include "AMDGPUUtil.h"
-#include "AMDILCodeEmitter.h"
#include "SIInstrInfo.h"
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
namespace {
- class SICodeEmitter : public MachineFunctionPass, public AMDILCodeEmitter {
+ class SICodeEmitter : public MachineFunctionPass, public AMDGPUCodeEmitter {
private:
static char ID;
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