**1) A set of general-purpose scalar instructions suitable for cryptographic applications as well as many other purposes**
-See [Big integer arithmetic](/openpower/sv/biginteger) and [Bit manipulation](/openpower/sv/bitmanip) for rationale, instruction list and definition in
-pseudo-code.
+See [Big integer arithmetic (bigint)](/openpower/sv/biginteger) and
+[Bit manipulation (bitmanip)](/openpower/sv/bitmanip) for rationale, instruction
+list and definition in pseudo-code.
-**2) Implementation and validation of the above instructions on the simulator**
+**2) Implementation and validation of the above instructions on the ISA simulator**
The implementation is scattered within the simulator code, which is available at:
<https://git.libre-soc.org/?p=openpower-isa.git;a=tree;hb=HEAD>
* [Test cases for bitmanip instructions](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/bitmanip/bitmanip_cases.py;h=93476025fc31dc5d42d4a86a27d4b826810436e2;hb=HEAD)
* [Test cases for bigint instructions](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/bigint/bigint_cases.py;h=2944ad431e586dca1b572f4be4c1a9c7a3e82e89;hb=HEAD)
+The above uses the ISA Simulator (see [Simulator Test API](/docs/testapi)).
+
+To run the above tests cases,
+[install the developer environment](/HDL_workflow/devscripts), go to the
+`~/src/openpower-isa/src/openpower/decoder/isa` directory, and run
+`python3 test_caller_bigint.py` and `python3 test_caller_bitmanip.py`.
+
**3) Reference HDL implementation of some instructions**
(full implemention was not possible within limited 2021-02-051 budget [[nlnet_2021_crypto_router]])
Code and tests are available:
-* [HDL Implementation of Galois Field instructions](https://git.libre-soc.org/?p=nmigen-gf.git;a=tree;f=src/nmigen_gf/hdl;hb=bc0c03b3df2fa19189aaa2b61a101cdc8ebf1beb)
-* [Unit test and formal verification for the HDL implementation of Galois Field instructions](https://git.libre-soc.org/?p=nmigen-gf.git;a=tree;f=src/nmigen_gf/hdl/test;hb=bc0c03b3df2fa19189aaa2b61a101cdc8ebf1beb)
* [HDL implementation of Ternlogi bitmanip instruction](https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/lut.py;h=755747ab2073dbf1a7620f9ac31e592b2bf63a44;hb=HEAD)
* [HDL implementation of Grev bitmanip instruction](https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/grev.py;h=2b22fe1bf35ba3e5f2787b62bbf36c329a444787;hb=HEAD)
+* [HDL Implementation of Galois Field instructions](https://git.libre-soc.org/?p=nmigen-gf.git;a=tree;f=src/nmigen_gf/hdl;hb=bc0c03b3df2fa19189aaa2b61a101cdc8ebf1beb)
* [Unit test for the HDL implementation of Ternlogi](https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/test/test_lut.py;h=e0a98099460ded8912299b05c513dc0f924005d7;hb=HEAD)
* [Unit test for the HDL implementation of Grev](https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/test/test_grev.py;h=780239d8a13b2954a7953d5d2e312dd517a80347;hb=HEAD)
* [Formal verification for the HDL implementation of Ternlogi](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/shift_rot/formal/proof_main_stage.py;h=379211d623a01259f77c90229cae0d57f40228a7;hb=HEAD#l311)
* [Formal verification for the HDL implementation of Grev](https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/shift_rot/formal/proof_main_stage.py;h=379211d623a01259f77c90229cae0d57f40228a7;hb=HEAD#l321)
+* [Unit test and formal verification for the HDL implementation of Galois Field instructions](https://git.libre-soc.org/?p=nmigen-gf.git;a=tree;f=src/nmigen_gf/hdl/test;hb=bc0c03b3df2fa19189aaa2b61a101cdc8ebf1beb)
+
+To run the HDL tests, just [install the developer environment](/HDL_workflow/devscripts)
+and directly run the test scripts referenced above.
**4) Additional specification of and simulation for concepts like a REMAP engine
and element width overrides**
* [REMAP documentation](https://libre-soc.org/openpower/sv/remap/)
* [Element width overrides documentation](https://libre-soc.org/openpower/sv/overview/#elwidths)
-Implemented 100% in simulator, allowing 100% successful implementation of Simple-V-PowerISA assembler to be made.
+Implemented 100% in ISA simulator, allowing 100% successful implementation of Simple-V-PowerISA assembler to be made.
(But limited budget of 2021-02-051 was insufficient to complete HDL
implementation.)